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Source at commit 1158 created 13 years 15 days ago. By azimutz, Match nvidia.c with the one on my branch (Chazi) adding dev id's from issue 99 and Asus G74SX (0DF4, 1251). | |
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1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "bootstruct.h"␊ |
9 | #include "pci.h"␊ |
10 | #include "pci_root.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_PCI␊ |
13 | #define DEBUG_PCI 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_PCI␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␊ |
20 | #endif␊ |
21 | ␊ |
22 | pci_dt_t␉*root_pci_dev;␊ |
23 | static char* dev_path;␉// TODO: Figure out what is going on here...␊ |
24 | ␊ |
25 | ␊ |
26 | uint8_t pci_config_read8(uint32_t pci_addr, uint8_t reg)␊ |
27 | {␊ |
28 | ␉pci_addr |= reg & ~3;␊ |
29 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
30 | ␉return inb(PCI_DATA_REG + (reg & 3));␊ |
31 | }␊ |
32 | ␊ |
33 | uint16_t pci_config_read16(uint32_t pci_addr, uint8_t reg)␊ |
34 | {␊ |
35 | ␉pci_addr |= reg & ~3;␊ |
36 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
37 | ␉return inw(PCI_DATA_REG + (reg & 2));␊ |
38 | }␊ |
39 | ␊ |
40 | uint32_t pci_config_read32(uint32_t pci_addr, uint8_t reg)␊ |
41 | {␊ |
42 | ␉pci_addr |= reg & ~3;␊ |
43 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
44 | ␉return inl(PCI_DATA_REG);␊ |
45 | }␊ |
46 | ␊ |
47 | void pci_config_write8(uint32_t pci_addr, uint8_t reg, uint8_t data)␊ |
48 | {␊ |
49 | ␉pci_addr |= reg & ~3;␊ |
50 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
51 | ␉outb(PCI_DATA_REG + (reg & 3), data);␊ |
52 | }␊ |
53 | ␊ |
54 | void pci_config_write16(uint32_t pci_addr, uint8_t reg, uint16_t data)␊ |
55 | {␊ |
56 | ␉pci_addr |= reg & ~3;␊ |
57 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
58 | ␉outw(PCI_DATA_REG + (reg & 2), data);␊ |
59 | }␊ |
60 | ␊ |
61 | void pci_config_write32(uint32_t pci_addr, uint8_t reg, uint32_t data)␊ |
62 | {␊ |
63 | ␉pci_addr |= reg & ~3;␊ |
64 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
65 | ␉outl(PCI_DATA_REG, data);␊ |
66 | }␊ |
67 | ␊ |
68 | void scan_pci_bus(pci_dt_t *start, uint8_t bus)␊ |
69 | {␊ |
70 | ␉pci_dt_t␉*new;␊ |
71 | ␉pci_dt_t␉**current = &start->children;␊ |
72 | ␉uint32_t␉id;␊ |
73 | ␉uint32_t␉pci_addr;␊ |
74 | ␉uint8_t␉␉dev;␊ |
75 | ␉uint8_t␉␉func;␊ |
76 | ␉uint8_t␉␉secondary_bus;␊ |
77 | ␉uint8_t␉␉header_type;␊ |
78 | ␉␊ |
79 | ␉for (dev = 0; dev < 32; dev++)␊ |
80 | ␉{␊ |
81 | ␉␉for (func = 0; func < 8; func++)␊ |
82 | ␉␉{␊ |
83 | ␉␉␉pci_addr = PCIADDR(bus, dev, func);␊ |
84 | ␉␉␉id = pci_config_read32(pci_addr, PCI_VENDOR_ID);␊ |
85 | ␉␉␉if (!id || id == 0xffffffff)␊ |
86 | ␉␉␉{␊ |
87 | ␉␉␉␉continue;␊ |
88 | ␉␉␉}␊ |
89 | ␉␉␉new = (pci_dt_t*)malloc(sizeof(pci_dt_t));␊ |
90 | ␉␉␉bzero(new, sizeof(pci_dt_t));␊ |
91 | ␉␉␉new->dev.addr␉= pci_addr;␊ |
92 | ␉␉␉new->vendor_id␉= id & 0xffff;␊ |
93 | ␉␉␉new->device_id␉= (id >> 16) & 0xffff;␊ |
94 | ␉␉␉new->class_id␉= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);␊ |
95 | ␉␉␉new->parent␉= start;␊ |
96 | ␉␉␉␊ |
97 | ␉␉␉header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);␊ |
98 | ␉␉␉switch (header_type & 0x7f)␊ |
99 | ␉␉␉{␊ |
100 | ␉␉␉␉case PCI_HEADER_TYPE_BRIDGE:␊ |
101 | ␉␉␉␉case PCI_HEADER_TYPE_CARDBUS:␊ |
102 | ␉␉␉␉␉secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS);␊ |
103 | ␉␉␉␉␉if (secondary_bus != 0)␊ |
104 | ␉␉␉␉␉{␊ |
105 | ␉␉␉␉␉␉scan_pci_bus(new, secondary_bus);␊ |
106 | ␉␉␉␉␉}␊ |
107 | ␉␉␉␉␉break;␊ |
108 | ␉␉␉}␊ |
109 | ␉␉␉*current = new;␊ |
110 | ␉␉␉current = &new->next;␊ |
111 | ␉␉␉␊ |
112 | ␉␉␉if ((func == 0) && ((header_type & 0x80) == 0))␊ |
113 | ␉␉␉{␊ |
114 | ␉␉␉␉break;␊ |
115 | ␉␉␉}␊ |
116 | ␉␉}␊ |
117 | ␉}␊ |
118 | }␊ |
119 | ␊ |
120 | void enable_pci_devs(void)␊ |
121 | {␊ |
122 | ␉uint16_t id;␊ |
123 | ␉uint32_t rcba, *fd;␊ |
124 | ␉␊ |
125 | ␉id = pci_config_read16(PCIADDR(0, 0x00, 0), 0x00);␊ |
126 | ␉/* make sure we're on Intel chipset */␊ |
127 | ␉if (id != 0x8086)␊ |
128 | ␉␉return;␊ |
129 | ␉rcba = pci_config_read32(PCIADDR(0, 0x1f, 0), 0xf0) & ~1;␊ |
130 | ␉fd = (uint32_t *)(rcba + 0x3418);␊ |
131 | ␉/* set SMBus Disable (SD) to 0 */␊ |
132 | ␉*fd &= ~0x8;␊ |
133 | ␉/* and all devices? */␊ |
134 | ␉//*fd = 0x1;␊ |
135 | }␊ |
136 | ␊ |
137 | ␊ |
138 | void build_pci_dt(void)␊ |
139 | {␊ |
140 | ␉dev_path = malloc(sizeof(char) * 256);␉// TODO: remove␊ |
141 | ␉␊ |
142 | ␉root_pci_dev = malloc(sizeof(pci_dt_t));␊ |
143 | ␉bzero(root_pci_dev, sizeof(pci_dt_t));␊ |
144 | ␉enable_pci_devs();␊ |
145 | ␉scan_pci_bus(root_pci_dev, 0);␊ |
146 | #if DEBUG_PCI␊ |
147 | ␉dump_pci_dt(root_pci_dev->children);␊ |
148 | ␉pause();␊ |
149 | #endif␊ |
150 | }␊ |
151 | ␊ |
152 | char *get_pci_dev_path(pci_dt_t *pci_dt)␊ |
153 | {␊ |
154 | ␉char* buffer = malloc(sizeof(char) * 256);␊ |
155 | ␊ |
156 | ␉pci_dt_t␉*current;␊ |
157 | ␉pci_dt_t␉*end;␊ |
158 | ␉char␉␉tmp[64];␊ |
159 | ␉␊ |
160 | ␉buffer[0] = 0;␉␊ |
161 | ␉end = root_pci_dev;␊ |
162 | ␉␊ |
163 | ␉int uid = getPciRootUID();␊ |
164 | ␉while (end != pci_dt)␊ |
165 | ␉{␊ |
166 | ␉␉current = pci_dt;␊ |
167 | ␉␉while (current->parent != end)␊ |
168 | ␉␉␉current = current->parent;␉␉␉␊ |
169 | ␉␉end = current;␊ |
170 | ␉␉if (current->parent == root_pci_dev)␊ |
171 | ␉␉{␊ |
172 | ␉␉␉sprintf(tmp, "PciRoot(0x%x)/Pci(0x%x,0x%x)", uid, ␊ |
173 | ␉␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
174 | ␉␉} ␊ |
175 | ␉␉else ␊ |
176 | ␉␉{␊ |
177 | ␉␉␉sprintf(tmp, "/Pci(0x%x,0x%x)", ␊ |
178 | ␉␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
179 | ␉␉}␊ |
180 | ␉␉sprintf(buffer, "%s%s", buffer, tmp);␊ |
181 | ␉}␊ |
182 | ␉return buffer;␊ |
183 | }␊ |
184 | ␊ |
185 | #ifndef OPTION_ROM␊ |
186 | void dump_pci_dt(pci_dt_t *pci_dt)␊ |
187 | {␊ |
188 | ␉pci_dt_t␉*current;␊ |
189 | ␉␊ |
190 | ␉current = pci_dt;␊ |
191 | ␉while (current) ␊ |
192 | ␉{␊ |
193 | ␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊ |
194 | ␉␉␉ current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊ |
195 | ␉␉␉ current->class_id, current->vendor_id, current->device_id, ␊ |
196 | ␉␉␉ get_pci_dev_path(current));␊ |
197 | ␉␉dump_pci_dt(current->children);␊ |
198 | ␉␉current = current->next;␊ |
199 | ␉}␊ |
200 | }␊ |
201 | #endif␊ |
202 |