1 | /*␊ |
2 | * usb.c␊ |
3 | * ␊ |
4 | *␊ |
5 | * Created by mackerintel on 12/20/08.␊ |
6 | * Copyright 2008 mackerintel. All rights reserved.␊ |
7 | *␊ |
8 | */␊ |
9 | ␊ |
10 | #include "libsaio.h"␊ |
11 | #include "boot.h"␊ |
12 | #include "bootstruct.h"␊ |
13 | #include "pci.h"␊ |
14 | ␊ |
15 | #ifndef DEBUG_USB␊ |
16 | #define DEBUG_USB 0␊ |
17 | #endif␊ |
18 | ␊ |
19 | #if DEBUG_USB␊ |
20 | #define DBG(x...)␉printf(x)␊ |
21 | #else␊ |
22 | #define DBG(x...)␊ |
23 | #endif␊ |
24 | ␊ |
25 | int ehci_acquire (pci_dt_t *pci_dev)␊ |
26 | {␊ |
27 | ␉int␉␉j, k;␊ |
28 | ␉uint32_t␉base;␊ |
29 | ␉uint8_t␉␉eecp;␊ |
30 | ␉uint8_t␉␉legacy[8];␊ |
31 | ␉bool␉␉isOwnershipConflict;␉␊ |
32 | ␉bool␉␉alwaysHardBIOSReset;␊ |
33 | ␊ |
34 | ␉alwaysHardBIOSReset = false;␉␊ |
35 | ␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊ |
36 | ␉␉alwaysHardBIOSReset = true;␊ |
37 | ␉}␊ |
38 | ␊ |
39 | ␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊ |
40 | ␉base = pci_config_read32(pci_dev->dev.addr, 0x10);␊ |
41 | ␊ |
42 | ␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊ |
43 | ␉␉pci_dev->vendor_id, pci_dev->device_id,␊ |
44 | ␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊ |
45 | ␉␉base);␊ |
46 | ␊ |
47 | ␉if (*((unsigned char*)base) < 0xc)␊ |
48 | ␉{␊ |
49 | ␉␉DBG("Config space too small: no legacy implementation\n");␊ |
50 | ␉␉return 1;␊ |
51 | ␉}␊ |
52 | ␉eecp = *((unsigned char*)(base + 9));␊ |
53 | ␉if (!eecp) {␊ |
54 | ␉␉DBG("No extended capabilities: no legacy implementation\n");␊ |
55 | ␉␉return 1;␊ |
56 | ␉}␊ |
57 | ␊ |
58 | ␉DBG("eecp=%x\n",eecp);␊ |
59 | ␊ |
60 | ␉// bad way to do it␊ |
61 | ␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊ |
62 | ␉for (j = 0; j < 8; j++) {␊ |
63 | ␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
64 | ␉␉DBG("%02x ", legacy[j]);␊ |
65 | ␉}␊ |
66 | ␉DBG("\n");␊ |
67 | ␊ |
68 | ␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊ |
69 | ␉//We try soft reset first - some systems hang on reboot with hard reset␊ |
70 | ␉// Definitely needed during reboot on 10.4.6␊ |
71 | ␊ |
72 | ␉isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊ |
73 | ␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊ |
74 | ␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊ |
75 | ␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊ |
76 | ␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊ |
77 | ␉␉for (k = 0; k < 25; k++) {␊ |
78 | ␉␉␉for (j = 0; j < 8; j++) {␊ |
79 | ␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
80 | ␉␉␉}␊ |
81 | ␉␉␉if (legacy[3] == 0) {␊ |
82 | ␉␉␉␉break;␊ |
83 | ␉␉␉}␊ |
84 | ␉␉␉delay(10);␊ |
85 | ␉␉}␊ |
86 | ␉}␉␊ |
87 | ␊ |
88 | ␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊ |
89 | ␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊ |
90 | ␊ |
91 | ␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊ |
92 | ␉for (k = 0; k < 25; k++) {␊ |
93 | ␉␉for (j = 0;j < 8; j++) {␊ |
94 | ␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
95 | ␉␉}␊ |
96 | ␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊ |
97 | ␉␉if (legacy[2] == 0) {␊ |
98 | ␉␉␉break;␊ |
99 | ␉␉}␊ |
100 | ␉␉delay(10);␊ |
101 | ␉}␊ |
102 | ␊ |
103 | ␉for (j = 0;j < 8; j++) {␊ |
104 | ␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
105 | ␉}␊ |
106 | ␉isOwnershipConflict = ((legacy[2]) != 0);␊ |
107 | ␉if (isOwnershipConflict) {␊ |
108 | ␉␉// Soft reset has failed. Assume SMI being ignored␊ |
109 | ␉␉// Hard reset␊ |
110 | ␉␉// Force Clear BIOS BIT␊ |
111 | ␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊ |
112 | ␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊ |
113 | ␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊ |
114 | ␊ |
115 | ␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊ |
116 | ␉␉for (k = 0; k < 25; k++) {␊ |
117 | ␉␉␉for (j = 0; j < 8; j++) {␊ |
118 | ␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
119 | ␉␉␉}␊ |
120 | ␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊ |
121 | ␊ |
122 | ␉␉␉if ((legacy[2]) == 0) {␊ |
123 | ␉␉␉␉break;␊ |
124 | ␉␉␉}␊ |
125 | ␉␉␉delay(10);␉␊ |
126 | ␉␉}␉␉␊ |
127 | ␉␉// Disable further SMI events␊ |
128 | ␉␉for (j = 4; j < 8; j++) {␊ |
129 | ␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊ |
130 | ␉␉}␊ |
131 | ␉}␊ |
132 | ␊ |
133 | ␉for (j = 0; j < 8; j++) {␊ |
134 | ␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊ |
135 | ␉}␊ |
136 | ␊ |
137 | ␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊ |
138 | ␊ |
139 | ␉// Final Ownership Resolution Check...␊ |
140 | ␉if (legacy[2] & 1) {␉␉␉␉␉␊ |
141 | ␉␉DBG("EHCI controller unable to take control from BIOS\n");␊ |
142 | ␉␉return 0;␊ |
143 | ␉}␊ |
144 | ␊ |
145 | ␉DBG("EHCI Acquire OS Ownership done\n");␉␊ |
146 | ␉return 1;␊ |
147 | }␊ |
148 | ␊ |
149 | int uhci_reset (pci_dt_t *pci_dev)␊ |
150 | {␊ |
151 | ␉uint32_t base, port_base;␊ |
152 | ␉␊ |
153 | ␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊ |
154 | ␉port_base = (base >> 5) & 0x07ff;␊ |
155 | ␊ |
156 | ␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊ |
157 | ␉␉pci_dev->vendor_id, pci_dev->device_id,␊ |
158 | ␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊ |
159 | ␉␉port_base, base);␊ |
160 | ␉␊ |
161 | ␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊ |
162 | ␊ |
163 | ␉outw (port_base, 0x0002);␊ |
164 | ␉delay(10);␊ |
165 | ␉outw (port_base+4,0);␊ |
166 | ␉delay(10);␊ |
167 | ␉outw (port_base,0);␊ |
168 | ␉return 1;␊ |
169 | }␊ |
170 | |