1 | /*␊ |
2 | * platform.h␊ |
3 | * AsereBLN: reworked and extended␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
8 | #define __LIBSAIO_PLATFORM_H␊ |
9 | ␊ |
10 | #include "libsaio.h"␊ |
11 | ␊ |
12 | extern bool platformCPUFeature(uint32_t);␊ |
13 | extern void scan_platform(void);␊ |
14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
15 | extern void scan_cpu();␊ |
16 | ␊ |
17 | #define bit(n)␉␉␉(1UL << (n))␊ |
18 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
19 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
20 | ␊ |
21 | ␊ |
22 | /* CPUID index into cpuid_raw */␊ |
23 | #define CPUID_0␉␉␉␉0␊ |
24 | #define CPUID_1␉␉␉␉1␊ |
25 | #define CPUID_2␉␉␉␉2␊ |
26 | #define CPUID_3␉␉␉␉3␊ |
27 | #define CPUID_4␉␉␉␉4␊ |
28 | #define CPUID_80␉␉␉5␊ |
29 | #define CPUID_81␉␉␉6␊ |
30 | #define CPUID_MAX␉␉␉7␊ |
31 | ␊ |
32 | #define CPU_MODEL_PENTIUM_M␉␉0x0D␊ |
33 | #define CPU_MODEL_YONAH␉␉␉0x0E␊ |
34 | #define CPU_MODEL_MEROM␉␉␉0x0F␊ |
35 | #define CPU_MODEL_PENRYN␉␉0x17␊ |
36 | #define CPU_MODEL_NEHALEM␉␉0x1A␊ |
37 | #define CPU_MODEL_ATOM␉␉␉0x1C␊ |
38 | #define CPU_MODEL_FIELDS␉␉0x1E␉/* Lynnfield, Clarksfield, Jasper */␊ |
39 | #define CPU_MODEL_DALES␉␉␉0x1F␉/* Havendale, Auburndale */␊ |
40 | #define CPU_MODEL_DALES_32NM␉0x25␉/* Clarkdale, Arrandale */␊ |
41 | #define CPU_MODEL_WESTMERE␉␉0x2C␉/* Gulftown, Westmere-EP, Westmere-WS */␊ |
42 | #define CPU_MODEL_NEHALEM_EX␉0x2E␊ |
43 | #define CPU_MODEL_WESTMERE_EX␉0x2F␊ |
44 | ␊ |
45 | /* CPU Features */␊ |
46 | // NOTE: Theses are currently mapped to the actual bit in the cpuid value␊ |
47 | #define CPU_FEATURE_MMX␉␉␉bit(23)␉␉// MMX Instruction Set␊ |
48 | #define CPU_FEATURE_SSE␉␉␉bit(25)␉␉// SSE Instruction Set␊ |
49 | #define CPU_FEATURE_SSE2␉␉bit(26)␉␉// SSE2 Instruction Set␊ |
50 | #define CPU_FEATURE_SSE3␉␉bit(0)␉␉// SSE3 Instruction Set␊ |
51 | #define CPU_FEATURE_SSE41␉␉bit(19)␉␉// SSE41 Instruction Set␊ |
52 | #define CPU_FEATURE_SSE42␉␉bit(20)␉␉// SSE42 Instruction Set␊ |
53 | #define CPU_FEATURE_EM64T␉␉bit(29)␉␉// 64Bit Support␊ |
54 | #define CPU_FEATURE_HTT␉␉␉bit(28)␉␉// HyperThreading␊ |
55 | #define CPU_FEATURE_MSR␉␉␉bit(5)␉␉// MSR Support␊ |
56 | ␊ |
57 | // NOTE: Determine correct bit for bellow (28 is already in use)␊ |
58 | #define CPU_FEATURE_MOBILE␉␉bit(1)␉␉// Mobile CPU␊ |
59 | //Slice - just use Platform->CPU.Mobile␊ |
60 | #define MEGA 1000000LL␊ |
61 | ␊ |
62 | /* SMBIOS Memory Types */ ␊ |
63 | #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
64 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
65 | #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
66 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
67 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
68 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
69 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
70 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
71 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
72 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
73 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
74 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
75 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
76 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
77 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
78 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
79 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
80 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
81 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
82 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
83 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
84 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
85 | ␊ |
86 | /* Memory Configuration Types */ ␊ |
87 | #define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊ |
88 | #define SMB_MEM_CHANNEL_SINGLE␉␉1␊ |
89 | #define SMB_MEM_CHANNEL_DUAL␉␉2␊ |
90 | #define SMB_MEM_CHANNEL_TRIPLE␉␉3␊ |
91 | ␊ |
92 | /* Maximum number of ram slots */␊ |
93 | #define MAX_RAM_SLOTS␉␉␉8␊ |
94 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
95 | ␊ |
96 | /* Maximum number of SPD bytes */␊ |
97 | #define MAX_SPD_SIZE␉␉␉256␊ |
98 | ␊ |
99 | /* Size of SMBIOS UUID in bytes */␊ |
100 | #define UUID_LEN␉␉␉16␊ |
101 | ␊ |
102 | typedef struct _RamSlotInfo_t {␊ |
103 | uint32_t␉␉ModuleSize;␉␉␉␉␉␉// Size of Module in MB␊ |
104 | uint32_t␉␉Frequency; // in Mhz␊ |
105 | const char*␉␉Vendor;␊ |
106 | const char*␉␉PartNo;␊ |
107 | const char*␉␉SerialNo;␊ |
108 | char*␉␉␉spd;␉␉␉␉␉␉␉// SPD Dump␊ |
109 | bool␉␉␉InUse;␊ |
110 | uint8_t␉␉␉Type;␊ |
111 | uint8_t␉␉␉BankConnections; // table type 6, see (3.3.7)␊ |
112 | uint8_t␉␉␉BankConnCnt;␊ |
113 | ␊ |
114 | } RamSlotInfo_t;␊ |
115 | ␊ |
116 | typedef struct _PlatformInfo_t {␊ |
117 | ␉struct PCI {␊ |
118 | ␉␉uint8_t␉␉␉NoDevices;␉␉␉␉// No of PCI devices␊ |
119 | ␉} PCI;␊ |
120 | ␉struct CPU {␊ |
121 | ␉␉uint32_t␉␉Features;␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
122 | ␉␉uint32_t␉␉Vendor;␉␉␉// Vendor␊ |
123 | ␉␉uint32_t␉␉Signature;␉␉// Signature␊ |
124 | ␉␉uint32_t␉␉Stepping;␉␉// Stepping␊ |
125 | ␉␉uint32_t␉␉Model;␉␉␉// Model␊ |
126 | ␉␉uint32_t␉␉ExtModel;␉␉// Extended Model␊ |
127 | ␉␉uint32_t␉␉Family;␉␉␉// Family␊ |
128 | ␉␉uint32_t␉␉ExtFamily;␉␉// Extended Family␊ |
129 | ␉␉uint32_t␉␉NoCores;␉␉// No Cores per Package␊ |
130 | ␉␉uint32_t␉␉NoThreads;␉␉// Threads per Package␊ |
131 | ␉␉uint8_t␉␉␉MaxCoef;␉␉// Max Multiplier␊ |
132 | ␉␉uint8_t␉␉␉MaxDiv;␉␉␉// Possible 0,5␊ |
133 | ␉␉uint8_t␉␉␉MinCoef;␉␉// Min Multiplier␊ |
134 | ␉␉uint8_t␉␉␉CurrCoef;␉␉// Current Multiplier␊ |
135 | ␉␉uint8_t␉␉␉CurrDiv;␊ |
136 | ␉␉float␉␉␉MaxRatio;␉␉// non-integer ratio␉␉␊ |
137 | ␉␉float␉␉␉CurrRatio;␉␉␉␉␊ |
138 | ␉␉uint64_t␉␉TSCFrequency;␉␉// TSC Frequency Hz␊ |
139 | ␉␉uint64_t␉␉FSBFrequency;␉␉// FSB Frequency Hz␊ |
140 | ␉␉uint64_t␉␉CPUFrequency;␉␉// CPU Frequency Hz␊ |
141 | ␉␉bool␉␉␉Mobile;␉␉␉␉␉// Mobile CPU␊ |
142 | ␉␉char␉␉␉BrandString[48];␉// 48 Byte Branding String␊ |
143 | ␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
144 | ␉} CPU;␊ |
145 | ␊ |
146 | ␉struct RAM {␊ |
147 | ␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊ |
148 | ␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊ |
149 | ␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
150 | ␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊ |
151 | ␉␉uint8_t␉␉␉TRP;␊ |
152 | ␉␉uint8_t␉␉␉RAS;␊ |
153 | ␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊ |
154 | ␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊ |
155 | ␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
156 | ␉␉char␉␉␉BrandString[48];␉␉␉// Branding String Memory Controller␊ |
157 | ␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊ |
158 | ␉} RAM;␊ |
159 | ␊ |
160 | ␉struct DMI {␊ |
161 | ␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots polulated by SMBIOS␊ |
162 | ␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊ |
163 | ␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊ |
164 | ␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
165 | ␉} DMI;␊ |
166 | ␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊ |
167 | ␉uint8_t␉␉␉␉*UUID;␊ |
168 | } PlatformInfo_t;␊ |
169 | ␊ |
170 | extern PlatformInfo_t* Platform;␊ |
171 | ␊ |
172 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
173 | |