Root/
Source at commit 1164 created 13 years 12 days ago. By azimutz, Add some pauses to nvidia.c and ati.c to help user feedback collection. | |
---|---|
1 | /*␊ |
2 | * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.␊ |
3 | *␊ |
4 | * @APPLE_LICENSE_HEADER_START@␊ |
5 | * ␊ |
6 | * This file contains Original Code and/or Modifications of Original Code␊ |
7 | * as defined in and that are subject to the Apple Public Source License␊ |
8 | * Version 2.0 (the 'License'). You may not use this file except in␊ |
9 | * compliance with the License. Please obtain a copy of the License at␊ |
10 | * http://www.opensource.apple.com/apsl/ and read it before using this␊ |
11 | * file.␊ |
12 | * ␊ |
13 | * The Original Code and all software distributed under the License are␊ |
14 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER␊ |
15 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,␊ |
16 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,␊ |
17 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.␊ |
18 | * Please see the License for the specific language governing rights and␊ |
19 | * limitations under the License.␊ |
20 | * ␊ |
21 | * @APPLE_LICENSE_HEADER_END@␊ |
22 | */␊ |
23 | /* Copyright (c) 1996 NeXT Software, Inc. All rights reserved.␊ |
24 | *␊ |
25 | *␉File:␉architecture/ppc/basic_regs.h␊ |
26 | *␉Author:␉Doug Mitchell, NeXT Software, Inc.␊ |
27 | *␊ |
28 | *␉Basic ppc registers.␊ |
29 | *␊ |
30 | * HISTORY␊ |
31 | * 22-May-97 Umesh Vaishampayan (umeshv@apple.com)␊ |
32 | ␉Updated to match MPCFPE32B/AD 1/97 REV. 1 ␊ |
33 | * 29-Dec-96 Umesh Vaishampayan (umeshv@NeXT.com)␊ |
34 | *␉Ported from m98k.␊ |
35 | * 05-Nov-92 Doug Mitchell at NeXT␊ |
36 | *␉Created.␊ |
37 | */␊ |
38 | ␊ |
39 | #ifndef _ARCH_PPC_BASIC_REGS_H_␊ |
40 | #define _ARCH_PPC_BASIC_REGS_H_␊ |
41 | ␊ |
42 | #include <architecture/ppc/reg_help.h>␊ |
43 | #include <architecture/ppc/macro_help.h>␊ |
44 | ␊ |
45 | #if !defined(__ASSEMBLER__)␊ |
46 | ␊ |
47 | /*␊ |
48 | * Number of General Purpose registers.␊ |
49 | */␊ |
50 | #define PPC_NGP_REGS␉32␊ |
51 | ␊ |
52 | /*␊ |
53 | * Common half-word used in Machine State Register and in ␊ |
54 | * various exception frames. Defined as a macro because the compiler␊ |
55 | * will align a struct to a word boundary when used inside another struct.␊ |
56 | */␊ |
57 | #define MSR_BITS␉␉␉␉␉␉␉ \␊ |
58 | ␉unsigned␉ee:BIT_WIDTH(15),␉/* external intr enable */ \␊ |
59 | ␉␉␉pr:BIT_WIDTH(14),␉/* problem state␉ */ \␊ |
60 | ␉␉␉fp:BIT_WIDTH(13),␉/* floating point avail␉ */ \␊ |
61 | ␉␉␉me:BIT_WIDTH(12),␉/* machine check enable␉ */ \␊ |
62 | ␉␉␉fe0:BIT_WIDTH(11),␉/* fp exception mode 0␉ */ \␊ |
63 | ␉␉␉se:BIT_WIDTH(10),␉/* single step enable␉ */ \␊ |
64 | ␉␉␉be:BIT_WIDTH(9),␉/* branch trace enable␉ */ \␊ |
65 | ␉␉␉fe1:BIT_WIDTH(8),␉/* fp exception mode 0␉ */ \␊ |
66 | ␉␉␉rsvd1:BIT_WIDTH(7),␉/* reserved␉␉ */ \␊ |
67 | ␉␉␉ip:BIT_WIDTH(6),␉/* interrupt prefix␉ */ \␊ |
68 | ␉␉␉ir:BIT_WIDTH(5),␉/* instruction relocate␉ */ \␊ |
69 | ␉␉␉dr:BIT_WIDTH(4),␉/* data relocate␉ */ \␊ |
70 | ␉␉␉rsvd2:BITS_WIDTH(3,2),␉/* reserved␉␉ */ \␊ |
71 | ␉␉␉ri:BIT_WIDTH(1),␉/* recoverable exception */ \␊ |
72 | ␉␉␉le:BIT_WIDTH(0)␉␉/* Little-endian mode␉ */␊ |
73 | ␊ |
74 | /*␊ |
75 | * Machine state register.␊ |
76 | * Read and written via get_msr() and set_msr() inlines, below.␊ |
77 | */␊ |
78 | typedef struct {␊ |
79 | ␉unsigned␉rsvd3:BITS_WIDTH(31,19),␉// reserved␊ |
80 | ␉␉␉pow:BIT_WIDTH(18),␉// Power management enable␊ |
81 | ␉␉␉rsvd0: BIT_WIDTH(17),␉// reserved␊ |
82 | ␉␉␉ile: BIT_WIDTH(16);␉// exception little endian␊ |
83 | ␊ |
84 | ␉␉␉MSR_BITS;␉␉␉// see above␊ |
85 | } msr_t;␊ |
86 | ␊ |
87 | /*␊ |
88 | * Data Storage Interrupt Status Register (DSISR)␊ |
89 | */␊ |
90 | typedef struct {␊ |
91 | ␉unsigned␉dse:BIT_WIDTH(31);␉// direct-store error␊ |
92 | ␉unsigned␉tnf:BIT_WIDTH(30);␉// translation not found␊ |
93 | ␉unsigned␉:BITS_WIDTH(29,28);␊ |
94 | ␉unsigned␉pe:BIT_WIDTH(27);␉// protection error␊ |
95 | ␉unsigned␉dsr:BIT_WIDTH(26);␉// lwarx/stwcx to direct-store␊ |
96 | ␉unsigned␉rw:BIT_WIDTH(25);␉// 1 => store, 0 => load␊ |
97 | ␉unsigned␉:BITS_WIDTH(24,23);␊ |
98 | ␉unsigned␉dab:BIT_WIDTH(22);␉// data address bkpt (601)␊ |
99 | ␉unsigned␉ssf:BIT_WIDTH(21);␉// seg table search failed␊ |
100 | ␉unsigned␉:BITS_WIDTH(20,0);␊ |
101 | } dsisr_t;␊ |
102 | ␊ |
103 | /*␊ |
104 | * Instruction Storage Interrupt Status Register (really SRR1)␊ |
105 | */␊ |
106 | typedef struct {␊ |
107 | ␉unsigned␉:BIT_WIDTH(31);␊ |
108 | ␉unsigned␉tnf:BIT_WIDTH(30);␉// translation not found␊ |
109 | ␉unsigned␉:BIT_WIDTH(29);␊ |
110 | ␉unsigned␉dse:BIT_WIDTH(28);␉// direct-store fetch error␊ |
111 | ␉unsigned␉pe:BIT_WIDTH(27);␉// protection error␊ |
112 | ␉unsigned␉:BITS_WIDTH(26,22);␊ |
113 | ␉unsigned␉ssf:BIT_WIDTH(21);␉// seg table search failed␊ |
114 | ␉unsigned␉:BITS_WIDTH(20,16);␊ |
115 | ␉MSR_BITS;␊ |
116 | } isisr_t;␊ |
117 | ␊ |
118 | /*␊ |
119 | * Alignment Interrupt Status Register (really DSISR)␊ |
120 | * NOTE: bit numbers in field *names* are in IBM'ese (0 is MSB).␊ |
121 | * FIXME: Yuck!!! Double Yuck!!!␊ |
122 | */␊ |
123 | typedef struct {␊ |
124 | ␉unsigned␉:BITS_WIDTH(31,20);␊ |
125 | ␉unsigned␉ds3031:BITS_WIDTH(19,18);// bits 30:31 if DS form␊ |
126 | ␉unsigned␉:BIT_WIDTH(17);␊ |
127 | ␉unsigned␉x2930:BITS_WIDTH(16,15); // bits 29:30 if X form␊ |
128 | ␉unsigned␉x25:BIT_WIDTH(14);␉ // bit 25 if X form or␊ |
129 | ␉␉␉␉␉␉ // bit 5 if D or DS form␊ |
130 | ␉unsigned␉x2124:BITS_WIDTH(13,10); // bits 21:24 if X form or␊ |
131 | ␉␉␉␉␉␉ // bits 1:4 if D or DS form␊ |
132 | ␉unsigned␉all615:BITS_WIDTH(9,0);␉ // bits 6:15 of instr␊ |
133 | ␉MSR_BITS;␊ |
134 | } aisr_t;␊ |
135 | ␊ |
136 | /*␊ |
137 | * Program Interrupt Status Register (really SRR1)␊ |
138 | */␊ |
139 | typedef struct {␊ |
140 | ␉unsigned␉:BITS_WIDTH(31,21);␊ |
141 | ␉unsigned␉fpee:BIT_WIDTH(20);␉// floating pt enable exception␊ |
142 | ␉unsigned␉ill:BIT_WIDTH(19);␉// illegal instruction␊ |
143 | ␉unsigned␉priv:BIT_WIDTH(18);␉// privileged instruction␊ |
144 | ␉unsigned␉trap:BIT_WIDTH(17);␉// trap program interrupt␊ |
145 | ␉unsigned␉subseq:BIT_WIDTH(16);␉// 1 => SRR0 points to␊ |
146 | ␉␉␉␉␉␉// subsequent instruction␊ |
147 | ␉MSR_BITS;␊ |
148 | } pisr_t;␊ |
149 | ␊ |
150 | /*␊ |
151 | * Condition register. May not be useful in C, let's see...␊ |
152 | */␊ |
153 | typedef struct {␊ |
154 | ␉unsigned␉lt:BIT_WIDTH(31),␉// negative␊ |
155 | ␉␉␉gt:BIT_WIDTH(30),␉// positive␊ |
156 | ␉␉␉eq:BIT_WIDTH(29),␉// equal to zero␊ |
157 | ␉␉␉so:BIT_WIDTH(28),␉// summary overflow␊ |
158 | ␉␉␉fx:BIT_WIDTH(27),␉// floating point exception␊ |
159 | ␉␉␉fex:BIT_WIDTH(26),␉// fp enabled exception␊ |
160 | ␉␉␉vx:BIT_WIDTH(25),␉// fp invalid operation␊ |
161 | ␉␉␉␉␉␉// exception␊ |
162 | ␉␉␉ox:BIT_WIDTH(24),␉// fp overflow exception␊ |
163 | ␉␉␉rsvd:BITS_WIDTH(23,0);␉// reserved␊ |
164 | } cr_t;␊ |
165 | ␊ |
166 | /*␊ |
167 | * Abstract values representing fe0:fe1.␊ |
168 | * See get_fp_exc_mode(), below.␊ |
169 | */␊ |
170 | typedef enum {␊ |
171 | ␉FEM_IGNORE_EXCEP,␉// ignore exceptions␊ |
172 | ␉FEM_IMPR_NONREC,␉// imprecise nonrecoverable␊ |
173 | ␉FEM_IMPR_RECOV,␉␉// imprecise recoverable␊ |
174 | ␉FEM_PRECISE␊ |
175 | } fp_exc_mode_t;␊ |
176 | ␊ |
177 | ␊ |
178 | /*␊ |
179 | * Special purpose registers.␊ |
180 | */␊ |
181 | ␊ |
182 | /*␊ |
183 | * Processor version register (special purpose register pvr).␊ |
184 | */␊ |
185 | typedef struct {␊ |
186 | ␉unsigned␉version:BITS_WIDTH(31,16),␉␊ |
187 | ␉␉␉revision:BITS_WIDTH(15,0);␊ |
188 | } pvr_t;␊ |
189 | ␊ |
190 | /*␊ |
191 | * Fixed point exception register (special purpose register xer)␊ |
192 | */␊ |
193 | typedef struct {␊ |
194 | ␉unsigned␉so:BIT_WIDTH(31),␉// summary overflow␊ |
195 | ␉␉␉ov:BIT_WIDTH(30),␉// overflow␊ |
196 | ␉␉␉ca:BIT_WIDTH(29),␉// carry␊ |
197 | ␉␉␉rsvd1:BITS_WIDTH(28,7), // reserved␊ |
198 | ␉␉␉byte_count:BITS_WIDTH(6,0);␉␊ |
199 | } xer_t;␊ |
200 | ␊ |
201 | /*␊ |
202 | * Inlines and macros to manipulate the above registers.␊ |
203 | */␊ |
204 | ␊ |
205 | /*␊ |
206 | * Get/set machine state register.␊ |
207 | */␊ |
208 | static __inline__ msr_t␊ |
209 | get_msr()␊ |
210 | {␊ |
211 | ␉msr_t␉__msr_tmp;␉␊ |
212 | ␉__asm__ volatile ("mfmsr %0 /* mfmsr */" : "=r" (__msr_tmp));␊ |
213 | ␉return __msr_tmp;␊ |
214 | }␊ |
215 | ␊ |
216 | static __inline__ void␊ |
217 | set_msr(msr_t msr)␊ |
218 | {␊ |
219 | ␉__asm__ volatile ("mtmsr %0 /* mtmsr */ " : : "r" (msr));␉␊ |
220 | }␊ |
221 | ␊ |
222 | /* ␊ |
223 | * Determine current fp_exc_mode_t given prog_mode.␊ |
224 | */␊ |
225 | static __inline__ fp_exc_mode_t␊ |
226 | get_fp_exc_mode(pmr_t pmr)␊ |
227 | {␊ |
228 | ␉if(pmr.fe0)␊ |
229 | ␉␉return pmr.fe1 ? FEM_PRECISE : FEM_IMPR_RECOV;␊ |
230 | ␉else␊ |
231 | ␉␉return pmr.fe1 ? FEM_IMPR_NONREC : FEM_IGNORE_EXCEP;␊ |
232 | }␊ |
233 | ␊ |
234 | /*␊ |
235 | * Software definitions for special purpose registers.␊ |
236 | * The same register is used as per_cpu data pointer and␊ |
237 | * vector base register. This requires that the vector␊ |
238 | * table be the first item in the per_cpu table.␊ |
239 | */␊ |
240 | #define SR_EXCEPTION_TMP_LR␉sprg0␊ |
241 | #define SR_EXCEPTION_TMP_CR␉sprg1␊ |
242 | #define SR_EXCEPTION_TMP_AT␉sprg2␊ |
243 | #define SR_PER_CPU_DATA␉␉sprg3␊ |
244 | #define SR_VBR␉␉␉sprg3␊ |
245 | ␊ |
246 | /*␊ |
247 | * Get/set special purpose registers.␊ |
248 | *␊ |
249 | * GET_SPR - get SPR by name.␊ |
250 | *␊ |
251 | * Example usage:␊ |
252 | *␊ |
253 | * {␊ |
254 | *␉xer_t␉some_xer;␊ |
255 | *␊ |
256 | *␉some_xer = GET_SPR(xer_t, xer);␊ |
257 | *␉...␊ |
258 | * }␊ |
259 | *␊ |
260 | * This is a strange one. We're creating a list of C expressions within␊ |
261 | * a set of curlies; the last expression ("__spr_tmp;") is the return value␊ |
262 | * of the statement created by the curlies.␊ |
263 | *␊ |
264 | */␊ |
265 | ␊ |
266 | #define GET_SPR(type, spr)␉␉␉␉␉\␊ |
267 | ({␉␉␉␉␉␉␉␉\␊ |
268 | ␉unsigned␉__spr_tmp;␉␉␉␉\␊ |
269 | ␉__asm__ volatile ("mfspr %0, " STRINGIFY(spr) : "=r" (__spr_tmp));␉␉␉␉\␊ |
270 | ␉*(type *)&__spr_tmp;␉␉␉␉␉\␊ |
271 | })␊ |
272 | ␊ |
273 | /* ␊ |
274 | * Example usage of SET_SPR:␊ |
275 | *␊ |
276 | * {␊ |
277 | *␉xer_t some_xer;␊ |
278 | *␊ |
279 | *␉...set up some_xer...␊ |
280 | *␉SET_SPR(xer, some_xer);␊ |
281 | * }␊ |
282 | */␊ |
283 | #define␉SET_SPR(spr, val)␉␉␉␉␉\␊ |
284 | MACRO_BEGIN␉␉␉␉␉␉␉\␊ |
285 | ␉__typeof__ (val) __spr_tmp = (val);␉␉␉\␊ |
286 | ␉__asm__ volatile ("mtspr "STRINGIFY(spr) ", %0" : : "r" (__spr_tmp));␉␉␉␉␉\␊ |
287 | MACRO_END␊ |
288 | ␊ |
289 | /*␊ |
290 | * Fully synchronize instruction stream.␊ |
291 | */␊ |
292 | static __inline__ void␊ |
293 | ppc_sync()␊ |
294 | {␊ |
295 | ␉__asm__ volatile ("sync /* sync */" : : );␊ |
296 | }␊ |
297 | ␊ |
298 | #endif /* ! __ASSEMBLER__ */␊ |
299 | ␊ |
300 | #endif /* _ARCH_PPC_BASIC_REGS_H_ */␊ |
301 | ␊ |
302 |