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Root/branches/meklortOld/i386/modules/USBFix/usb.c

Source at commit 1166 created 13 years 10 days ago.
By meklort, Fixed recent Makefile changes. Please do not use /Users/evan/SourceCode/tmp/chameleon/trunk or VPATH. the *only* time you should use /Users/evan/SourceCode/tmp/chameleon/trunk is when setting the SRCROOT variable. Also note that very soon make pkg is going to be removed. The pkg build script in trunk is very out of date. Instead please use the package maker at http://forge.voodooprojects.org/p/chameleonApplications/. Once this is ready for trunk it will be merged.
1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10#include "libsaio.h"␊
11#include "boot.h"␊
12#include "bootstruct.h"␊
13#include "pci.h"␊
14␊
15#ifndef DEBUG_USB␊
16#define DEBUG_USB 0␊
17#endif␊
18␊
19#if DEBUG_USB␊
20#define DBG(x...)␉printf(x)␊
21#else␊
22#define DBG(x...)␊
23#endif␊
24␊
25␊
26struct pciList␊
27{␊
28␉pci_dt_t* pciDev;␊
29␉struct pciList* next;␊
30};␊
31␊
32struct pciList* usbList = NULL;␊
33␊
34int legacy_off (pci_dt_t *pci_dev);␊
35int ehci_acquire (pci_dt_t *pci_dev);␊
36int uhci_reset (pci_dt_t *pci_dev);␊
37␊
38// Add usb device to the list␊
39void notify_usb_dev(pci_dt_t *pci_dev)␊
40{␊
41␉struct pciList* current = (struct pciList*)malloc(sizeof(struct pciList));␊
42␉current->next = usbList;␊
43␉current->pciDev = pci_dev;␊
44␉␊
45␉usbList = current;␊
46}␊
47␊
48// Loop through the list and call the apropriate patch function␊
49int usb_loop()␊
50{␊
51␉int retVal = 1;␊
52␉bool fix_ehci, fix_uhci, fix_usb, fix_legacy = false;␊
53␉fix_ehci = fix_uhci = fix_usb = true;␊
54␉␊
55␉if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig))␊
56␉{␊
57␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Disable all if none set␊
58␉}␊
59␉else ␊
60␉{␊
61␉␉getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);␊
62␉␉getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);␊
63␉␉getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);␊
64␉}␊
65␉␊
66␉struct pciList* current = usbList;␊
67␉␊
68␉while(current)␊
69␉{␊
70␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊
71␉␉{␊
72␉␉␉// EHCI␊
73␉␉␉case 0x20:␊
74␉␉ ␉if(fix_legacy) retVal &= legacy_off(current->pciDev);␊
75␉␉ ␉if(fix_ehci) retVal &= ehci_acquire(current->pciDev);␊
76␉␉␉␉␊
77␉␉␉␉break;␊
78␉␉␉␉␊
79␉␉␉// UHCI␊
80␉␉␉case 0x00:␊
81␉␉␉␉if (fix_uhci) retVal &= uhci_reset(current->pciDev);␊
82␊
83␉␉␉␉break;␊
84␉␉}␊
85␉␉␊
86␉␉current = current->next;␊
87␉}␊
88␉return retVal;␊
89}␊
90␊
91int legacy_off (pci_dt_t *pci_dev)␊
92{␊
93␉// Set usb legacy off modification by Signal64␊
94␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
95␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊
96␉// AKA: Make this run immediatly before the kernel is called␊
97␉uint32_t␉capaddr, opaddr; ␉␉␊
98␉uint8_t␉␉eecp;␉␉␉␊
99␉uint32_t␉usbcmd, usbsts, usbintr;␉␉␉␊
100␉uint32_t␉usblegsup, usblegctlsts;␉␉␊
101␉␊
102␉int isOSowned;␊
103␉int isBIOSowned;␊
104␉␊
105␉verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
106␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
107␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
108␉␊
109␉␊
110␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
111␉capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
112␉␊
113␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
114␉opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
115␉␊
116␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
117␉eecp=*((unsigned char*)(capaddr + 9));␊
118␉␊
119␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
120␉␊
121␉usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
122␉usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
123␉usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
124␉␊
125␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
126␉␊
127␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊
128␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
129␉␊
130␉// informational only␊
131␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
132␉isOSowned = !!((usblegsup) & (1 << (24)));␊
133␉␊
134␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
135␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
136␉␊
137␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
138␉␊
139␉// Reset registers to Legacy OFF␊
140␉DBG("Clearing USBLEGCTLSTS\n");␊
141␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
142␉␊
143␉// if delay value is in milliseconds it doesn't appear to work. ␊
144␉// setting value to anything up to 65535 does not add the expected delay here.␊
145␉delay(100);␊
146␉␊
147␉usbcmd = *((unsigned int*)(opaddr));␊
148␉usbsts = *((unsigned int*)(opaddr + 4));␊
149␉usbintr = *((unsigned int*)(opaddr + 8));␊
150␉␊
151␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
152␉␊
153␉DBG("Clearing Registers\n");␊
154␉␊
155␉// clear registers to default␊
156␉usbcmd = (usbcmd & 0xffffff00);␊
157␉*((unsigned int*)(opaddr)) = usbcmd;␊
158␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
159␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
160␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
161␉␊
162␉// get the results␊
163␉usbcmd = *((unsigned int*)(opaddr));␊
164␉usbsts = *((unsigned int*)(opaddr + 4));␊
165␉usbintr = *((unsigned int*)(opaddr + 8));␊
166␉␊
167␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
168␉␊
169␉// read 32bit USBLEGSUP (eecp+0) ␊
170␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
171␉␊
172␉// informational only␊
173␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
174␉isOSowned = !!((usblegsup) & (1 << (24)));␊
175␉␊
176␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
177␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
178␉␊
179␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
180␉␊
181␉verbose("Legacy USB Off Done\n");␉␊
182␉return 1;␊
183}␊
184␊
185int ehci_acquire (pci_dt_t *pci_dev)␊
186{␊
187␉int␉␉j, k;␊
188␉uint32_t␉base;␊
189␉uint8_t␉␉eecp;␊
190␉uint8_t␉␉legacy[8];␊
191␉bool␉␉isOwnershipConflict;␉␊
192␉bool␉␉alwaysHardBIOSReset;␊
193␊
194␉alwaysHardBIOSReset = false;␉␊
195␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊
196␉␉alwaysHardBIOSReset = true;␊
197␉}␊
198␊
199␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
200␉base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
201␊
202␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
203␉␉pci_dev->vendor_id, pci_dev->device_id,␊
204␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
205␉␉base);␊
206␊
207␉if (*((unsigned char*)base) < 0xc)␊
208␉{␊
209␉␉DBG("Config space too small: no legacy implementation\n");␊
210␉␉return 1;␊
211␉}␊
212␉eecp = *((unsigned char*)(base + 9));␊
213␉if (!eecp) {␊
214␉␉DBG("No extended capabilities: no legacy implementation\n");␊
215␉␉return 1;␊
216␉}␊
217␊
218␉DBG("eecp=%x\n",eecp);␊
219␊
220␉// bad way to do it␊
221␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
222␉for (j = 0; j < 8; j++) {␊
223␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
224␉␉DBG("%02x ", legacy[j]);␊
225␉}␊
226␉DBG("\n");␊
227␊
228␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
229␉//We try soft reset first - some systems hang on reboot with hard reset␊
230␉// Definitely needed during reboot on 10.4.6␊
231␊
232␉isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊
233␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
234␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
235␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
236␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
237␉␉for (k = 0; k < 25; k++) {␊
238␉␉␉for (j = 0; j < 8; j++) {␊
239␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
240␉␉␉}␊
241␉␉␉if (legacy[3] == 0) {␊
242␉␉␉␉break;␊
243␉␉␉}␊
244␉␉␉delay(10);␊
245␉␉}␊
246␉}␉␊
247␊
248␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
249␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
250␊
251␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
252␉for (k = 0; k < 25; k++) {␊
253␉␉for (j = 0;j < 8; j++) {␊
254␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
255␉␉}␊
256␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
257␉␉if (legacy[2] == 0) {␊
258␉␉␉break;␊
259␉␉}␊
260␉␉delay(10);␊
261␉}␊
262␊
263␉for (j = 0;j < 8; j++) {␊
264␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
265␉}␊
266␉isOwnershipConflict = ((legacy[2]) != 0);␊
267␉if (isOwnershipConflict) {␊
268␉␉// Soft reset has failed. Assume SMI being ignored␊
269␉␉// Hard reset␊
270␉␉// Force Clear BIOS BIT␊
271␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
272␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
273␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
274␊
275␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
276␉␉for (k = 0; k < 25; k++) {␊
277␉␉␉for (j = 0; j < 8; j++) {␊
278␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
279␉␉␉}␊
280␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
281␊
282␉␉␉if ((legacy[2]) == 0) {␊
283␉␉␉␉break;␊
284␉␉␉}␊
285␉␉␉delay(10);␉␊
286␉␉}␉␉␊
287␉␉// Disable further SMI events␊
288␉␉for (j = 4; j < 8; j++) {␊
289␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
290␉␉}␊
291␉}␊
292␊
293␉for (j = 0; j < 8; j++) {␊
294␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
295␉}␊
296␊
297␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
298␊
299␉// Final Ownership Resolution Check...␊
300␉if (legacy[2] & 1) {␉␉␉␉␉␊
301␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
302␉␉return 0;␊
303␉}␊
304␊
305␉DBG("EHCI Acquire OS Ownership done\n");␉␊
306␉return 1;␊
307}␊
308␊
309int uhci_reset (pci_dt_t *pci_dev)␊
310{␊
311␉uint32_t base, port_base;␊
312␉␊
313␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
314␉port_base = (base >> 5) & 0x07ff;␊
315␊
316␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
317␉␉pci_dev->vendor_id, pci_dev->device_id,␊
318␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
319␉␉port_base, base);␊
320␉␊
321␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
322␊
323␉outw (port_base, 0x0002);␊
324␉delay(10);␊
325␉outw (port_base+4,0);␊
326␉delay(10);␊
327␉outw (port_base,0);␊
328␉return 1;␊
329}␊
330

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