1 | /*␊ |
2 | * Copyright (c) 2009 Evan Lojewski. All rights reserved.␊ |
3 | *␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "modules.h"␊ |
8 | #include "boot.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "pci.h"␊ |
11 | #include "hpet.h"␊ |
12 | ␊ |
13 | #ifndef DEBUG_HPET␊ |
14 | #define DEBUG_HPET 0␊ |
15 | #endif␊ |
16 | ␊ |
17 | #if DEBUG_HPET␊ |
18 | #define DBG(x...) printf(x)␊ |
19 | #else␊ |
20 | #define DBG(x...)␊ |
21 | #endif␊ |
22 | ␊ |
23 | void force_enable_hpet_intel(pci_dt_t *lpc_dev);␊ |
24 | void force_enable_hpet_via(pci_dt_t *lpc_dev);␊ |
25 | ␊ |
26 | ␊ |
27 | void HPET_hook(void* arg1, void* arg2, void* arg3, void* arg4, void* arg5, void* arg6)␊ |
28 | {␊ |
29 | ␉pci_dt_t* current = arg1;␊ |
30 | ␉␊ |
31 | ␉if(current->class_id != PCI_CLASS_BRIDGE_ISA) return;␊ |
32 | ␉␊ |
33 | ␉␊ |
34 | ␉force_enable_hpet(current);␊ |
35 | }␊ |
36 | ␊ |
37 | void HPET_start()␊ |
38 | {␊ |
39 | ␉bool enable = true;␊ |
40 | ␉getBoolForKey(EnableHPETModule, &enable, &bootInfo->bootConfig);␊ |
41 | ␉␊ |
42 | ␉if (enable)␉␊ |
43 | ␉␉register_hook_callback("PCIDevice", &HPET_hook);␊ |
44 | }␊ |
45 | ␊ |
46 | /*␊ |
47 | * Force HPET enabled␊ |
48 | *␊ |
49 | * via fix from http://forum.voodooprojects.org/index.php/topic,1596.0.html␊ |
50 | */␊ |
51 | ␊ |
52 | static struct lpc_controller_t lpc_controllers_intel[] = {␊ |
53 | ␉␊ |
54 | ␉// Default unknown chipset␊ |
55 | ␉{ 0, 0, "" },␊ |
56 | ␉␊ |
57 | ␉// Intel␊ |
58 | ␉{ 0x8086, 0x24dc, "ICH5" },␊ |
59 | ␉{ 0x8086, 0x2640, "ICH6" },␊ |
60 | ␉{ 0x8086, 0x2641, "ICH6M" },␊ |
61 | ␉␊ |
62 | ␉{ 0x8086, 0x27b0, "ICH7 DH" },␊ |
63 | ␉{ 0x8086, 0x27b8, "ICH7" },␊ |
64 | ␉{ 0x8086, 0x27b9, "ICH7M" },␊ |
65 | ␉{ 0x8086, 0x27bd, "ICH7M DH" },␊ |
66 | ␊ |
67 | ␉{ 0x8086, 0x27bc, "NM10" },␊ |
68 | ␊ |
69 | ␉{ 0x8086, 0x2810, "ICH8R" },␊ |
70 | ␉{ 0x8086, 0x2811, "ICH8M-E" },␊ |
71 | ␉{ 0x8086, 0x2812, "ICH8DH" },␊ |
72 | ␉{ 0x8086, 0x2814, "ICH8DO" },␊ |
73 | ␉{ 0x8086, 0x2815, "ICH8M" },␊ |
74 | ␉␊ |
75 | ␉{ 0x8086, 0x2912, "ICH9DH" },␊ |
76 | ␉{ 0x8086, 0x2914, "ICH9DO" },␊ |
77 | ␉{ 0x8086, 0x2916, "ICH9R" },␊ |
78 | ␉{ 0x8086, 0x2917, "ICH9M-E" },␊ |
79 | ␉{ 0x8086, 0x2918, "ICH9" },␊ |
80 | ␉{ 0x8086, 0x2919, "ICH9M" },␊ |
81 | ␉␊ |
82 | ␉{ 0x8086, 0x3a14, "ICH10DO" },␊ |
83 | ␉{ 0x8086, 0x3a16, "ICH10R" },␊ |
84 | ␉{ 0x8086, 0x3a18, "ICH10" },␊ |
85 | ␉{ 0x8086, 0x3a1a, "ICH10D" },␊ |
86 | };␊ |
87 | ␊ |
88 | static struct lpc_controller_t lpc_controllers_via[] = {␊ |
89 | ␉// Default unknown chipset␊ |
90 | ␉{ 0, 0, "" },␊ |
91 | ␉␊ |
92 | ␉{ 0x1106, 0x3372, "VT8237S" },␊ |
93 | };␊ |
94 | ␊ |
95 | ␊ |
96 | void force_enable_hpet(pci_dt_t *lpc_dev)␊ |
97 | {␊ |
98 | ␉switch(lpc_dev->vendor_id)␊ |
99 | ␉{␊ |
100 | ␉␉case 0x8086:␊ |
101 | ␉␉␉force_enable_hpet_intel(lpc_dev);␊ |
102 | ␉␉␉break;␊ |
103 | ␉␉␉␊ |
104 | ␉␉case 0x1106:␊ |
105 | ␉␉␉force_enable_hpet_via(lpc_dev);␊ |
106 | ␉␉␉break;␊ |
107 | ␉␉default:␊ |
108 | ␉␉␉break;␊ |
109 | ␉}␊ |
110 | ␉␊ |
111 | ␉␊ |
112 | #if DEBUG_HPET␊ |
113 | ␉printf("Press [Enter] to continue...\n");␊ |
114 | ␉getc();␊ |
115 | #endif␊ |
116 | }␊ |
117 | ␊ |
118 | void force_enable_hpet_via(pci_dt_t *lpc_dev)␊ |
119 | {␊ |
120 | ␉uint32_t␉val, hpet_address = 0xFED00000;␊ |
121 | ␉unsigned int i;␊ |
122 | ␉␊ |
123 | ␉for(i = 1; i < sizeof(lpc_controllers_via) / sizeof(lpc_controllers_via[0]); i++)␊ |
124 | ␉{␊ |
125 | ␉␉if (␉(lpc_controllers_via[i].vendor == lpc_dev->vendor_id) ␊ |
126 | ␉␉␉&& (lpc_controllers_via[i].device == lpc_dev->device_id))␊ |
127 | ␉␉{␉␊ |
128 | ␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊ |
129 | ␉␉␉␊ |
130 | ␉␉␉DBG("VIA %s LPC Interface [%04x:%04x], MMIO\n", ␊ |
131 | ␉␉␉␉lpc_controllers_via[i].name, lpc_dev->vendor_id, lpc_dev->device_id);␊ |
132 | ␉␉␉␊ |
133 | ␉␉␉if (val & 0x80) {␊ |
134 | ␉␉␉␉hpet_address = (val & ~0x3ff);␊ |
135 | ␉␉␉␉DBG("HPET at 0x%lx\n", hpet_address);␊ |
136 | ␉␉␉}␊ |
137 | ␉␉␉else ␊ |
138 | ␉␉␉{␊ |
139 | ␉␉␉␉val = 0xfed00000 | 0x80;␊ |
140 | ␉␉␉␉pci_config_write32(lpc_dev->dev.addr, 0x68, val);␊ |
141 | ␉␉␉␉val = pci_config_read32(lpc_dev->dev.addr, 0x68);␊ |
142 | ␉␉␉␉if (val & 0x80) {␊ |
143 | ␉␉␉␉␉hpet_address = (val & ~0x3ff);␊ |
144 | ␉␉␉␉␉DBG("Force enabled HPET at 0x%lx\n", hpet_address);␊ |
145 | ␉␉␉␉}␊ |
146 | ␉␉␉␉else {␊ |
147 | ␉␉␉␉␉DBG("Unable to enable HPET");␊ |
148 | ␉␉␉␉}␊ |
149 | ␉␉␉}␊ |
150 | ␉␉}␊ |
151 | ␉}␊ |
152 | }␊ |
153 | ␊ |
154 | ␊ |
155 | ␊ |
156 | void force_enable_hpet_intel(pci_dt_t *lpc_dev)␊ |
157 | {␊ |
158 | ␉uint32_t␉val, hpet_address = 0xFED00000;␊ |
159 | ␉unsigned int i;␊ |
160 | ␉void␉␉*rcba;␊ |
161 | ␉␊ |
162 | ␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊ |
163 | ␉for(i = 1; i < sizeof(lpc_controllers_intel) / sizeof(lpc_controllers_intel[0]); i++)␊ |
164 | ␉{␊ |
165 | ␉␉if (␉(lpc_controllers_intel[i].vendor == lpc_dev->vendor_id) ␊ |
166 | ␉␉␉&& (lpc_controllers_intel[i].device == lpc_dev->device_id))␊ |
167 | ␉␉{␉␊ |
168 | ␉␉␉␊ |
169 | ␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊ |
170 | ␉␉␉␊ |
171 | ␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊ |
172 | ␉␉␉␉lpc_controllers_intel[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊ |
173 | ␉␉␉␊ |
174 | ␉␉␉if (rcba == 0)␊ |
175 | ␉␉␉␉DBG(" RCBA disabled; cannot force enable HPET\n");␊ |
176 | ␉␉␉else␊ |
177 | ␉␉␉{␊ |
178 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
179 | ␉␉␉␉if (val & 0x80)␊ |
180 | ␉␉␉␉{␊ |
181 | ␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊ |
182 | ␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊ |
183 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
184 | ␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊ |
185 | ␉␉␉␉}␊ |
186 | ␉␉␉␉else␊ |
187 | ␉␉␉␉{␊ |
188 | ␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊ |
189 | ␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊ |
190 | ␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊ |
191 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
192 | ␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊ |
193 | ␉␉␉␉}␊ |
194 | ␉␉␉␉␊ |
195 | ␉␉␉␉// verify if the job is done␊ |
196 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
197 | #if DEBUG_HPET␉␊ |
198 | ␉␉␉␉if (!(val & 0x80))␊ |
199 | ␉␉␉␉␉printf(" Failed to force enable HPET\n");␊ |
200 | #endif␊ |
201 | /*␊ |
202 | #define HPET_CONFIG 0x10 // General configuration register ␊ |
203 | #define HPET_CNF_LEG_RT 0x00000002␊ |
204 | #define HPET_CNF_ENABLE 0x00000001␊ |
205 | ␊ |
206 | val = REG32(hpet_address, HPET_CONFIG);␊ |
207 | val &= ~HPET_CNF_LEG_RT;␊ |
208 | val |= HPET_CNF_ENABLE;␊ |
209 | REG32(hpet_address, HPET_CONFIG) = val;␊ |
210 | */␊ |
211 | ␉␉␉}␊ |
212 | ␉␉␉break;␊ |
213 | ␉␉␉␊ |
214 | ␉␉}␊ |
215 | ␉}␊ |
216 | } |