1 | /*␊ |
2 | * Copyright (c) 1999 Apple Computer, Inc. All rights reserved.␊ |
3 | *␊ |
4 | * @APPLE_LICENSE_HEADER_START@␊ |
5 | * ␊ |
6 | * This file contains Original Code and/or Modifications of Original Code␊ |
7 | * as defined in and that are subject to the Apple Public Source License␊ |
8 | * Version 2.0 (the 'License'). You may not use this file except in␊ |
9 | * compliance with the License. Please obtain a copy of the License at␊ |
10 | * http://www.opensource.apple.com/apsl/ and read it before using this␊ |
11 | * file.␊ |
12 | * ␊ |
13 | * The Original Code and all software distributed under the License are␊ |
14 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER␊ |
15 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,␊ |
16 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,␊ |
17 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.␊ |
18 | * Please see the License for the specific language governing rights and␊ |
19 | * limitations under the License.␊ |
20 | * ␊ |
21 | * @APPLE_LICENSE_HEADER_END@␊ |
22 | */␊ |
23 | /* Copyright (c) 1996 NeXT Software, Inc. All rights reserved.␊ |
24 | *␊ |
25 | *␉File:␉architecture/ppc/fp_regs.h␊ |
26 | *␉Author:␉Doug Mitchell, NeXT Software, Inc.␊ |
27 | *␊ |
28 | *␉ppc floating point registers.␊ |
29 | *␊ |
30 | * HISTORY␊ |
31 | * 29-Dec-96 Umesh Vaishampayan (umeshv@NeXT.com)␊ |
32 | *␉Ported from m98k.␊ |
33 | * 05-Nov-92 Doug Mitchell at NeXT␊ |
34 | *␉Created.␊ |
35 | */␊ |
36 | ␊ |
37 | #ifndef _ARCH_PPC_FP_REGS_H_␊ |
38 | #define _ARCH_PPC_FP_REGS_H_␊ |
39 | ␊ |
40 | #include <architecture/ppc/reg_help.h>␊ |
41 | ␊ |
42 | #if !defined(__ASSEMBLER__)␊ |
43 | /*␊ |
44 | * Floating point status and control register.␊ |
45 | *␊ |
46 | * This struct is aligned to an 8-byte boundary because 64-bit␊ |
47 | * load/store instructions (lfd/stfd) are used to access it. The␊ |
48 | * FPSCR can only be read/written through other FP registers.␊ |
49 | */␊ |
50 | typedef struct {␊ |
51 | unsigned unused[1] __attribute__(( aligned(8) ));␊ |
52 | ␉unsigned␉fx:BIT_WIDTH(31),␉// exception summary␊ |
53 | ␉␉␉fex:BIT_WIDTH(30),␉// enabled exception summary␊ |
54 | ␉␉␉vx:BIT_WIDTH(29),␉// invalid op exception␊ |
55 | ␉␉␉␉␉␉// summary␊ |
56 | ␉␉␉ox:BIT_WIDTH(28),␉// overflow exception␊ |
57 | ␉␉␉ux:BIT_WIDTH(27),␉// underflow exception␊ |
58 | ␉␉␉zx:BIT_WIDTH(26),␉// divide by zero exception␊ |
59 | ␉␉␉xx:BIT_WIDTH(25),␉// inexact exception␊ |
60 | ␉␉␉vx_snan:BIT_WIDTH(24),␉// not a number exception␊ |
61 | ␉␉␉vx_isi:BIT_WIDTH(23),␉// exception␊ |
62 | ␉␉␉vx_idi:BIT_WIDTH(22),␉// exception␊ |
63 | ␉␉␉vx_zdz:BIT_WIDTH(21),␉// exception␊ |
64 | ␉␉␉vx_imz:BIT_WIDTH(20),␉// exception␊ |
65 | ␉␉␉vx_xvc:BIT_WIDTH(19),␉// exception␊ |
66 | ␉␉␉fr:BIT_WIDTH(18),␉// fraction rounded␊ |
67 | ␉␉␉fi:BIT_WIDTH(17),␉// fraction inexact␊ |
68 | ␉␉␉class:BIT_WIDTH(16),␉// class descriptor␊ |
69 | ␉␉␉fl:BIT_WIDTH(15),␉// negative␊ |
70 | ␉␉␉fg:BIT_WIDTH(14),␉// positive␊ |
71 | ␉␉␉fe:BIT_WIDTH(13),␉// equal or zero␊ |
72 | ␉␉␉fu:BIT_WIDTH(12),␉// not a number␊ |
73 | ␉␉␉rsvd1:BIT_WIDTH(11),␉// reserved␊ |
74 | ␉␉␉vx_soft:BIT_WIDTH(10),␉// software request exception␊ |
75 | ␉␉␉rsvd2:BIT_WIDTH(9),␉// reserved␊ |
76 | ␉␉␉vx_cvi:BIT_WIDTH(8),␉// invalid integer convert␊ |
77 | ␉␉␉␉␉␉// exception␊ |
78 | ␉␉␉ve:BIT_WIDTH(7),␉// invalid op exception enable␊ |
79 | ␉␉␉oe:BIT_WIDTH(6),␉// overflow exception enable␊ |
80 | ␉␉␉ue:BIT_WIDTH(5),␉// underflow exception enable␊ |
81 | ␉␉␉ze:BIT_WIDTH(4),␉// divide by zero exception␊ |
82 | ␉␉␉␉␉␉// enable␊ |
83 | ␉␉␉xe:BIT_WIDTH(3),␉// inexact exception enable␊ |
84 | ␉␉␉ni:BIT_WIDTH(2),␉// non-IEEE exception enable␊ |
85 | ␉␉␉rn:BITS_WIDTH(1,0);␉// rounding control␊ |
86 | } ppc_fp_scr_t;␊ |
87 | ␊ |
88 | /*␊ |
89 | * Values for fp_scr_t.rn (rounding control).␊ |
90 | */␊ |
91 | typedef enum {␊ |
92 | ␉RN_NEAREST = 0,␊ |
93 | ␉RN_TOWARD_ZERO = 1,␊ |
94 | ␉RN_TOWARD_PLUS = 2,␊ |
95 | ␉RN_TOWARD_MINUS = 3␊ |
96 | } ppc_fp_rn_t;␊ |
97 | ␊ |
98 | /*␊ |
99 | * ppc_fpf_t -- data types that MAY be in floating point register file␊ |
100 | * Actual data types supported is implementation dependent␊ |
101 | */␊ |
102 | typedef union {␊ |
103 | float f; // 32 bit IEEE single␊ |
104 | double d; // 64 bit IEEE double␊ |
105 | ␊ |
106 | /* ␊ |
107 | ␉ * Insure compiler aligns struct appropriately ␊ |
108 | ␉ */␊ |
109 | unsigned x[2] __attribute__(( aligned(8) ));␊ |
110 | } ppc_fpf_t;␊ |
111 | ␊ |
112 | /*␊ |
113 | * Number of FP registers.␊ |
114 | */␊ |
115 | #define PPC_NFP_REGS␉32␊ |
116 | ␊ |
117 | /*␊ |
118 | * Read/write FPSCR.␊ |
119 | * FIXME - these don't work, you need to go thru a fp register.␊ |
120 | */␊ |
121 | typedef union {␊ |
122 | ␉double ␉␉__dbl;␊ |
123 | ␉ppc_fp_scr_t ␉__scr;␊ |
124 | } __fp_un_t;␊ |
125 | ␊ |
126 | static __inline__ ppc_fp_scr_t␊ |
127 | get_fp_scr()␊ |
128 | {␊ |
129 | ␉__fp_un_t ␉__fp_un;␊ |
130 | ␉␊ |
131 | ␉__asm__ volatile ("mffs. %0 /* mffs */"␉\␊ |
132 | ␉ ␉: "=f" (__fp_un.__dbl));␊ |
133 | ␉return (__fp_un.__scr);␉␉␊ |
134 | }␊ |
135 | ␊ |
136 | static __inline__ void␊ |
137 | set_fp_scr(ppc_fp_scr_t fp_scr)␊ |
138 | {␊ |
139 | ␉__fp_un_t ␉__fp_un;␊ |
140 | ␊ |
141 | ␉__fp_un.__scr = fp_scr;␊ |
142 | ␉__asm__ volatile ("mtfsf 0xff, %0; /* mtfsf */ "␉\␊ |
143 | ␉ : : "f" (__fp_un.__dbl));␉␊ |
144 | }␊ |
145 | ␊ |
146 | #endif /* ! __ASSEMBLER__ */␊ |
147 | ␊ |
148 | #endif /* _ARCH_PPC_FP_REGS_H_ */␊ |
149 | |