1 | /*␊ |
2 | * resolution.h␊ |
3 | * ␊ |
4 | *␉NOTE: I don't beleive this code is production ready / should be in trunk␊ |
5 | * Atleast, not in it's current state. ␊ |
6 | *␊ |
7 | * Created by Evan Lojewski on 3/4/10.␊ |
8 | * Copyright 2009. All rights reserved.␊ |
9 | *␊ |
10 | */␊ |
11 | #ifndef _RESOLUTION_H_␊ |
12 | #define _RESOLUTION_H_␊ |
13 | ␊ |
14 | //#include "libsaio.h"␊ |
15 | //#include "edid.h" //included␊ |
16 | #include "915resolution.h"␊ |
17 | ␊ |
18 | ␊ |
19 | void patchVideoBios()␊ |
20 | {␉␉␊ |
21 | ␉UInt32 x = 0, y = 0, bp = 0;␊ |
22 | ␉␊ |
23 | ␉getResolution(&x, &y, &bp);␊ |
24 | ␉verbose("getResolution: %dx%dx%d\n", (int)x, (int)y, (int)bp);␊ |
25 | ␉␊ |
26 | ␉if (x != 0 &&␊ |
27 | ␉␉y != 0 && ␊ |
28 | ␉␉bp != 0)␊ |
29 | ␉{␊ |
30 | ␉␉vbios_map * map;␊ |
31 | ␉␉␊ |
32 | ␉␉map = open_vbios(CT_UNKWN);␊ |
33 | ␉//␉verbose("open_vbios\n");␊ |
34 | ␉␉if(map)␊ |
35 | ␉␉{␊ |
36 | ␉␉␉unlock_vbios(map);␊ |
37 | ␉␉␉␊ |
38 | ␉␉␉set_mode(map, x, y, bp, 0, 0);␊ |
39 | ␉␉␉␊ |
40 | ␉␉␉relock_vbios(map);␊ |
41 | ␉␉␉␊ |
42 | ␉␉␉close_vbios(map);␊ |
43 | ␉␉}␊ |
44 | ␉}␉␉␊ |
45 | ␉␊ |
46 | }␊ |
47 | ␊ |
48 | ␊ |
49 | /* Copied from 915 resolution created by steve tomljenovic␊ |
50 | *␊ |
51 | * This code is based on the techniques used in :␊ |
52 | *␊ |
53 | * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊ |
54 | * for demonstrating how to shadow the VBIOS into system RAM␊ |
55 | * and then modify it.␊ |
56 | *␊ |
57 | * - 1280patch by Andrew Tipton (andrewtipton null li).␊ |
58 | *␊ |
59 | * - 855resolution by Alain Poirier␊ |
60 | *␊ |
61 | * This source code is into the public domain.␊ |
62 | */␊ |
63 | ␊ |
64 | /**␊ |
65 | **␊ |
66 | **/␊ |
67 | ␊ |
68 | #define CONFIG_MECH_ONE_ADDR␉0xCF8␊ |
69 | #define CONFIG_MECH_ONE_DATA␉0xCFC␊ |
70 | ␊ |
71 | int freqs[] = { 60, 75, 85 };␊ |
72 | ␊ |
73 | UInt32 get_chipset_id(void)␊ |
74 | {␊ |
75 | ␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊ |
76 | ␉return inl(CONFIG_MECH_ONE_DATA);␊ |
77 | }␊ |
78 | ␊ |
79 | chipset_type get_chipset(UInt32 id)␊ |
80 | {␊ |
81 | ␉chipset_type type;␊ |
82 | ␉␉␊ |
83 | ␉switch (id) {␊ |
84 | ␉␉case 0x35758086:␊ |
85 | ␉␉␉type = CT_830;␊ |
86 | ␉␉␉break;␊ |
87 | ␉␉␉␊ |
88 | ␉␉case 0x25608086:␊ |
89 | ␉␉␉type = CT_845G;␊ |
90 | ␉␉␉break;␊ |
91 | ␉␉␉␊ |
92 | ␉␉case 0x35808086:␊ |
93 | ␉␉␉type = CT_855GM;␊ |
94 | ␉␉␉break;␊ |
95 | ␉␉␉␊ |
96 | ␉␉case 0x25708086:␊ |
97 | ␉␉␉type = CT_865G;␊ |
98 | ␉␉␉break;␊ |
99 | ␉␉␉␊ |
100 | ␉␉case 0x25808086:␊ |
101 | ␉␉␉type = CT_915G;␊ |
102 | ␉␉␉break;␊ |
103 | ␉␉␉␊ |
104 | ␉␉case 0x25908086:␊ |
105 | ␉␉␉type = CT_915GM;␊ |
106 | ␉␉␉break;␊ |
107 | ␉␉␉␊ |
108 | ␉␉case 0x27708086:␊ |
109 | ␉␉␉type = CT_945G;␊ |
110 | ␉␉␉break;␊ |
111 | ␉␉␉␊ |
112 | ␉␉case 0x27a08086:␊ |
113 | ␉␉␉type = CT_945GM;␊ |
114 | ␉␉␉break;␊ |
115 | ␉␉␉␊ |
116 | ␉␉case 0x27ac8086:␊ |
117 | ␉␉␉type = CT_945GME;␊ |
118 | ␉␉␉break;␊ |
119 | ␉␉␉␊ |
120 | ␉␉case 0x29708086:␊ |
121 | ␉␉␉type = CT_946GZ;␊ |
122 | ␉␉␉break;␊ |
123 | ␉␉␉␊ |
124 | ␉␉case 0x27748086:␊ |
125 | ␉␉␉type = CT_955X;␊ |
126 | ␉␉␉break;␊ |
127 | ␉␉␉␊ |
128 | ␉␉case 0x277c8086:␊ |
129 | ␉␉␉type = CT_975X;␊ |
130 | ␉␉␉break;␊ |
131 | ␊ |
132 | ␉␉case 0x29a08086:␊ |
133 | ␉␉␉type = CT_G965;␊ |
134 | ␉␉␉break;␊ |
135 | ␉␉␉␊ |
136 | ␉␉case 0x29908086:␊ |
137 | ␉␉␉type = CT_Q965;␊ |
138 | ␉␉␉break;␊ |
139 | ␉␉␉␊ |
140 | ␉␉case 0x81008086:␊ |
141 | ␉␉␉type = CT_500;␊ |
142 | ␉␉␉break;␊ |
143 | ␉␉␉␊ |
144 | ␉␉case 0x2e108086:␊ |
145 | ␉␉case 0X2e908086:␊ |
146 | ␉␉␉type = CT_B43;␊ |
147 | ␉␉␉break;␊ |
148 | ␊ |
149 | ␉␉case 0x2e208086:␊ |
150 | ␉␉␉type = CT_P45;␊ |
151 | ␉␉␉break;␊ |
152 | ␊ |
153 | ␉␉case 0x2e308086:␊ |
154 | ␉␉␉type = CT_G41;␊ |
155 | ␉␉␉break;␊ |
156 | ␉␉␉␉␉␊ |
157 | ␉␉case 0x29c08086:␊ |
158 | ␉␉␉type = CT_G31;␊ |
159 | ␉␉␉break;␊ |
160 | ␉␉␉␊ |
161 | ␉␉case 0x29208086:␊ |
162 | ␉␉␉type = CT_G45;␊ |
163 | ␉␉␉break;␊ |
164 | ␉␉␉␊ |
165 | ␉␉case 0xA0108086:␉// mobile␊ |
166 | ␉␉case 0xA0008086:␉// desktop␊ |
167 | ␉␉␉type = CT_3150;␊ |
168 | ␉␉␉break;␊ |
169 | ␉␉␉␊ |
170 | ␉␉case 0x2a008086:␊ |
171 | ␉␉␉type = CT_965GM;␊ |
172 | ␉␉␉break;␊ |
173 | ␉␉␉␊ |
174 | ␉␉case 0x29e08086:␊ |
175 | ␉␉␉type = CT_X48;␊ |
176 | ␉␉␉break;␉␉␉␊ |
177 | ␉␉␉␉␊ |
178 | ␉␉case 0x2a408086:␊ |
179 | ␉␉␉type = CT_GM45;␊ |
180 | ␉␉␉break;␊ |
181 | ␉␉␉␊ |
182 | ␉␉␉␊ |
183 | ␉␉default:␊ |
184 | ␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊ |
185 | ␉␉␉{␊ |
186 | ␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊ |
187 | ␉␉␉␉//getc();␊ |
188 | ␉␉␉␉//type = CT_UNKWN_INTEL;␊ |
189 | ␉␉␉␉type = CT_UNKWN;␊ |
190 | ␊ |
191 | ␉␉␉}␊ |
192 | ␉␉␉type = CT_UNKWN;␊ |
193 | ␉␉␉break;␊ |
194 | ␉}␊ |
195 | ␉return type;␊ |
196 | }␊ |
197 | ␊ |
198 | vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊ |
199 | {␊ |
200 | ␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊ |
201 | ␉return ptr;␊ |
202 | }␊ |
203 | ␊ |
204 | vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊ |
205 | {␊ |
206 | ␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊ |
207 | ␉return ptr;␊ |
208 | }␊ |
209 | ␊ |
210 | vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊ |
211 | {␊ |
212 | ␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊ |
213 | ␉return ptr;␊ |
214 | }␊ |
215 | ␊ |
216 | char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊ |
217 | {␊ |
218 | ␉UInt32 i;␊ |
219 | ␉UInt16 r1, r2;␊ |
220 | ␉␊ |
221 | ␉r1 = r2 = 32000;␊ |
222 | ␉␊ |
223 | ␉for (i=0; i < map->mode_table_size; i++)␊ |
224 | ␉{␊ |
225 | ␉␉if (map->mode_table[i].resolution <= r1)␊ |
226 | ␉␉{␊ |
227 | ␉␉␉r1 = map->mode_table[i].resolution;␊ |
228 | ␉␉}␊ |
229 | ␉␉else␊ |
230 | ␉␉{␊ |
231 | ␉␉␉if (map->mode_table[i].resolution <= r2)␊ |
232 | ␉␉␉{␊ |
233 | ␉␉␉␉r2 = map->mode_table[i].resolution;␊ |
234 | ␉␉␉}␊ |
235 | ␉␉}␊ |
236 | ␉␉␊ |
237 | ␉␉/*printf("r1 = %d r2 = %d\n", r1, r2);*/␊ |
238 | ␉}␊ |
239 | ␉␊ |
240 | ␉return (r2-r1-6) % entry_size == 0;␊ |
241 | }␊ |
242 | ␊ |
243 | void close_vbios(vbios_map * map);␊ |
244 | ␊ |
245 | char detect_ati_bios_type(vbios_map * map)␊ |
246 | {␉␊ |
247 | ␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊ |
248 | }␊ |
249 | ␊ |
250 | ␊ |
251 | vbios_map * open_vbios(chipset_type forced_chipset)␊ |
252 | {␊ |
253 | ␉UInt32 z;␊ |
254 | ␉vbios_map * map = malloc(sizeof(vbios_map));␊ |
255 | ␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊ |
256 | ␉/*␊ |
257 | ␉ * Determine chipset␊ |
258 | ␉ */␊ |
259 | ␉␊ |
260 | ␉if (forced_chipset == CT_UNKWN)␊ |
261 | ␉{␊ |
262 | ␉␉map->chipset_id = get_chipset_id();␊ |
263 | ␉␉map->chipset = get_chipset(map->chipset_id);␊ |
264 | ␉}␊ |
265 | ␉else if (forced_chipset != CT_UNKWN)␊ |
266 | ␉{␊ |
267 | ␉␉map->chipset = forced_chipset;␊ |
268 | ␉}␊ |
269 | ␉␊ |
270 | ␉␊ |
271 | ␉if (map->chipset == CT_UNKWN)␊ |
272 | ␉{␊ |
273 | ␉␉//verbose("Unknown chipset type.\n");␊ |
274 | ␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊ |
275 | ␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊ |
276 | ␉␉close_vbios(map);␊ |
277 | ␉␉return 0;␊ |
278 | ␉}␊ |
279 | ␉␊ |
280 | ␉␊ |
281 | ␉/*␊ |
282 | ␉ * Map the video bios to memory␊ |
283 | ␉ */␊ |
284 | ␉map->bios_ptr=(char*)VBIOS_START;␊ |
285 | ␉␊ |
286 | ␉/*␊ |
287 | ␉ * check if we have ATI Radeon␊ |
288 | ␉ */␊ |
289 | ␉map->ati_tables.base = map->bios_ptr;␊ |
290 | ␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊ |
291 | ␉if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)␊ |
292 | ␉{␊ |
293 | ␉␉// ATI Radeon Card␊ |
294 | ␉␉map->bios = BT_ATI_1;␊ |
295 | ␉␉␊ |
296 | ␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊ |
297 | ␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊ |
298 | ␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊ |
299 | ␉␉␊ |
300 | ␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊ |
301 | ␉␉if (map->ati_mode_table == 0)␊ |
302 | ␉␉{␊ |
303 | ␉␉␉verbose("Unable to locate the mode table.\n");␊ |
304 | ␉␉␉verbose("Please run the program 'dump_bios' as root and\n");␊ |
305 | ␉␉␉verbose("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
306 | ␉␉␉verbose("Chipset: %d\n", map->chipset);␊ |
307 | ␉␉␉close_vbios(map);␊ |
308 | ␉␉␉return 0;␊ |
309 | ␉␉}␊ |
310 | ␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊ |
311 | ␉␉␊ |
312 | ␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊ |
313 | ␉␉␊ |
314 | ␉}␊ |
315 | ␉else {␊ |
316 | ␉␉␊ |
317 | ␉␉/*␊ |
318 | ␉␉ * check if we have NVIDIA␊ |
319 | ␉␉ */␊ |
320 | ␊ |
321 | ␉␉int i = 0;␊ |
322 | ␉␉while (i < 512)␊ |
323 | ␉␉{ // we don't need to look through the whole bios, just the first 512 bytes␊ |
324 | ␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊ |
325 | ␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊ |
326 | ␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊ |
327 | ␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊ |
328 | ␉␉␉{␊ |
329 | ␉␉␉␉map->bios = BT_NVDA;␊ |
330 | ␉␉␉␉unsigned short nv_data_table_offset = 0;␊ |
331 | ␉␉␉␉unsigned short * nv_data_table;␊ |
332 | ␉␉␉␉NV_VESA_TABLE * std_vesa;␊ |
333 | ␉␉␉␉␊ |
334 | ␉␉␉␉int i = 0;␊ |
335 | ␉␉␉␉␊ |
336 | ␉␉␉␉while (i < 0x300)␊ |
337 | ␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊ |
338 | ␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊ |
339 | ␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊ |
340 | ␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊ |
341 | ␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊ |
342 | ␉␉␉␉␉{␊ |
343 | ␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊ |
344 | ␉␉␉␉␉␉break;␊ |
345 | ␉␉␉␉␉}␊ |
346 | ␉␉␉␉␉i++;␊ |
347 | ␉␉␉␉}␊ |
348 | ␉␉␉␉␊ |
349 | ␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊ |
350 | ␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊ |
351 | ␉␉␉␉␊ |
352 | ␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊ |
353 | ␉␉␉␉if (map->nv_mode_table == 0)␊ |
354 | ␉␉␉␉{␊ |
355 | ␉␉␉␉␉verbose("Unable to locate the mode table.\n");␊ |
356 | ␉␉␉␉␉verbose("Please run the program 'dump_bios' as root and\n");␊ |
357 | ␉␉␉␉␉verbose("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
358 | ␉␉␉␉␉verbose("Chipset: %s\n", map->chipset);␊ |
359 | ␉␉␉␉␉close_vbios(map);␊ |
360 | ␉␉␉␉␉return 0;␊ |
361 | ␉␉␉␉}␊ |
362 | ␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊ |
363 | ␉␉␉␉␊ |
364 | ␉␉␉␉break;␊ |
365 | ␉␉␉}␊ |
366 | ␉␉␉i++;␊ |
367 | ␉␉}␊ |
368 | ␉}␊ |
369 | ␉␊ |
370 | ␉␊ |
371 | ␉/*␊ |
372 | ␉ * check if we have Intel␊ |
373 | ␉ */␊ |
374 | ␉␊ |
375 | ␉/*if (map->chipset == CT_UNKWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊ |
376 | ␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊ |
377 | ␉ ␊ |
378 | ␉ printf("Chipset Id: %x\n", map->chipset_id);␊ |
379 | ␉ ␊ |
380 | ␉ printf("Please report this problem to stomljen@yahoo.com\n");␊ |
381 | ␉ ␊ |
382 | ␉ close_vbios(map);␊ |
383 | ␉ return 0;␊ |
384 | ␉ }*/␊ |
385 | ␉//Slice - Intel = 49 6E 74 65 6C located @ 0xBE6␊ |
386 | ␉/*␊ |
387 | ␉ PCIptr @0x18 = 0x0040␊ |
388 | ␉ version @0x20 = 0x0AE0␊ |
389 | ␉ */␊ |
390 | ␉int i = 0;␊ |
391 | ␉while (i < 4096)␊ |
392 | ␉{ // we don't need to look through the whole bios, just the first 0x1000 bytes␊ |
393 | ␉␉if ((␉map->bios_ptr[i] == 0x49) ␊ |
394 | ␉␉␉&& (map->bios_ptr[i+1] == 0x6E) ␊ |
395 | ␉␉␉&& (map->bios_ptr[i+2] == 0x74) ␊ |
396 | ␉␉␉&& (map->bios_ptr[i+3] == 0x65) ␊ |
397 | ␉␉␉&& (map->bios_ptr[i+4] == 0x6C)) ␊ |
398 | ␉␉{␊ |
399 | ␉␉␉verbose( "Intel VideoBIOS detected. \n");␊ |
400 | ␉␉␉map->bios = BT_INTEL;␊ |
401 | ␉␉␉close_vbios(map);␊ |
402 | ␉␉␉return 0;␉␉␊ |
403 | ␉␉␉//break;␊ |
404 | ␉␉}␊ |
405 | ␉␉i++;␊ |
406 | ␉}␊ |
407 | ␉␊ |
408 | ␉/*␊ |
409 | ␉ * check for others␊ |
410 | ␉ */␊ |
411 | ␉␊ |
412 | ␊ |
413 | ␉␊ |
414 | ␉/*␊ |
415 | ␉ * Figure out where the mode table is ␊ |
416 | ␉ */␊ |
417 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA)) ␊ |
418 | ␉{␊ |
419 | ␉␉char* p = map->bios_ptr + 16;␊ |
420 | ␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊ |
421 | ␉␉␊ |
422 | ␉␉while (p < limit && map->mode_table == 0)␊ |
423 | ␉␉{␊ |
424 | ␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊ |
425 | ␉␉␉␊ |
426 | ␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊ |
427 | ␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊ |
428 | ␉␉␉{␊ |
429 | ␉␉␉␉map->mode_table = mode_ptr;␊ |
430 | ␉␉␉}␊ |
431 | ␉␉␉␊ |
432 | ␉␉␉p++;␊ |
433 | ␉␉}␊ |
434 | ␉␉␊ |
435 | ␉␉if (map->mode_table == 0) ␊ |
436 | ␉␉{␊ |
437 | ␉␉␉close_vbios(map);␊ |
438 | ␉␉␉return 0;␊ |
439 | ␉␉}␊ |
440 | ␉}␊ |
441 | ␉␊ |
442 | ␉␊ |
443 | ␉/*␊ |
444 | ␉ * Determine size of mode table␊ |
445 | ␉ */␊ |
446 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
447 | ␉{␊ |
448 | ␉␉vbios_mode * mode_ptr = map->mode_table;␊ |
449 | ␉␉␊ |
450 | ␉␉while (mode_ptr->mode != 0xff)␊ |
451 | ␉␉{␊ |
452 | ␉␉␉map->mode_table_size++;␊ |
453 | ␉␉␉mode_ptr++;␊ |
454 | ␉␉}␊ |
455 | ␉}␊ |
456 | ␉␊ |
457 | ␉/*␊ |
458 | ␉ * Figure out what type of bios we have␊ |
459 | ␉ * order of detection is important␊ |
460 | ␉ */␊ |
461 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
462 | ␉{␊ |
463 | ␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊ |
464 | ␉␉{␊ |
465 | ␉␉␉map->bios = BT_3;␊ |
466 | ␉␉}␊ |
467 | ␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊ |
468 | ␉␉{␊ |
469 | ␉␉␉map->bios = BT_2;␊ |
470 | ␉␉}␊ |
471 | ␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊ |
472 | ␉␉{␊ |
473 | ␉␉␉map->bios = BT_1;␊ |
474 | ␉␉}␊ |
475 | ␉␉else {␊ |
476 | ␉␉␉return 0;␊ |
477 | ␉␉}␊ |
478 | ␉}␊ |
479 | ␉␊ |
480 | ␉return map;␊ |
481 | }␊ |
482 | ␊ |
483 | void close_vbios(vbios_map * map)␊ |
484 | {␊ |
485 | ␉free(map);␊ |
486 | }␊ |
487 | ␊ |
488 | void unlock_vbios(vbios_map * map)␊ |
489 | {␊ |
490 | ␉␊ |
491 | ␉map->unlocked = TRUE;␊ |
492 | ␊ |
493 | ␉switch (map->chipset) {␊ |
494 | ␉␉case CT_UNKWN:␊ |
495 | ␉␉␉break;␊ |
496 | ␉␉case CT_830:␊ |
497 | ␉␉case CT_855GM:␊ |
498 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
499 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
500 | ␉␉␉␊ |
501 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
502 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
503 | ␉␉␉break;␊ |
504 | ␉␉case CT_845G:␊ |
505 | ␉␉case CT_865G:␊ |
506 | ␉␉case CT_915G:␊ |
507 | ␉␉case CT_915GM:␊ |
508 | ␉␉case CT_945G:␊ |
509 | ␉␉case CT_945GM:␊ |
510 | ␉␉case CT_945GME:␊ |
511 | ␉␉case CT_946GZ:␊ |
512 | ␉␉case CT_G965:␊ |
513 | ␉␉case CT_Q965:␊ |
514 | ␉␉case CT_965GM:␊ |
515 | ␉␉case CT_975X:␊ |
516 | ␉␉case CT_P35:␊ |
517 | ␉␉case CT_955X:␊ |
518 | ␉␉case CT_X48:␊ |
519 | ␉␉case CT_B43:␊ |
520 | ␉␉case CT_Q45:␊ |
521 | ␉␉case CT_P45:␊ |
522 | ␉␉case CT_GM45:␊ |
523 | ␉␉case CT_G45:␊ |
524 | ␉␉case CT_G41:␊ |
525 | ␉␉case CT_G31:␊ |
526 | ␉␉case CT_500:␊ |
527 | ␉␉case CT_3150:␊ |
528 | ␉␉case CT_UNKWN_INTEL:␉// Assume newer intel chipset is the same as before␊ |
529 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
530 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
531 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
532 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
533 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
534 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
535 | ␉␉␉break;␊ |
536 | ␉}␊ |
537 | ␉␊ |
538 | #if DEBUG␊ |
539 | ␉{␊ |
540 | ␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
541 | ␉␉verbose("unlock PAM: (0x%08x)\n", t);␊ |
542 | ␉}␊ |
543 | #endif␊ |
544 | }␊ |
545 | ␊ |
546 | void relock_vbios(vbios_map * map)␊ |
547 | {␊ |
548 | ␉␊ |
549 | ␉map->unlocked = FALSE;␊ |
550 | ␉␊ |
551 | ␉switch (map->chipset)␊ |
552 | ␉{␊ |
553 | ␉␉case CT_UNKWN:␊ |
554 | ␉␉␉break;␊ |
555 | ␉␉case CT_830:␊ |
556 | ␉␉case CT_855GM:␊ |
557 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
558 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊ |
559 | ␉␉␉break;␊ |
560 | ␉␉case CT_845G:␊ |
561 | ␉␉case CT_865G:␊ |
562 | ␉␉case CT_915G:␊ |
563 | ␉␉case CT_915GM:␊ |
564 | ␉␉case CT_945G:␊ |
565 | ␉␉case CT_945GM:␊ |
566 | ␉␉case CT_945GME:␊ |
567 | ␉␉case CT_946GZ:␊ |
568 | ␉␉case CT_G965:␊ |
569 | ␉␉case CT_955X:␊ |
570 | ␉␉case CT_G45:␊ |
571 | ␉␉case CT_Q965:␊ |
572 | ␉␉case CT_965GM:␊ |
573 | ␉␉case CT_975X:␊ |
574 | ␉␉case CT_P35:␊ |
575 | ␉␉case CT_X48:␊ |
576 | ␉␉case CT_B43:␊ |
577 | ␉␉case CT_Q45:␊ |
578 | ␉␉case CT_P45:␊ |
579 | ␉␉case CT_GM45:␊ |
580 | ␉␉case CT_G41:␊ |
581 | ␉␉case CT_G31:␊ |
582 | ␉␉case CT_500:␊ |
583 | ␉␉case CT_3150:␊ |
584 | ␉␉case CT_UNKWN_INTEL:␊ |
585 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
586 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
587 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
588 | ␉␉␉break;␊ |
589 | ␉}␊ |
590 | ␉␊ |
591 | #if DEBUG␊ |
592 | ␉{␊ |
593 | UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
594 | ␉␉verbose("relock PAM: (0x%08x)\n", t);␊ |
595 | ␉}␊ |
596 | #endif␊ |
597 | }␊ |
598 | ␊ |
599 | ␊ |
600 | int getMode(edid_mode *mode)␊ |
601 | {␊ |
602 | ␉char* edidInfo = readEDID();␊ |
603 | ␉␉␉␊ |
604 | ␉if(!edidInfo) return 1;␊ |
605 | //Slice␊ |
606 | ␉if(!fb_parse_edid((struct EDID *)edidInfo, mode)) ␊ |
607 | ␉{␊ |
608 | ␉␉free( edidInfo );␊ |
609 | ␉␉return 1;␊ |
610 | ␉}␊ |
611 | /*␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊ |
612 | ␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊ |
613 | ␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊ |
614 | ␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊ |
615 | ␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊ |
616 | ␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊ |
617 | ␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊ |
618 | ␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊ |
619 | ␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊ |
620 | */␉␉␊ |
621 | ␉␉␊ |
622 | ␉free( edidInfo );␊ |
623 | ␉␉␊ |
624 | ␉if(!mode->h_active) return 1;␊ |
625 | ␉␊ |
626 | ␉return 0;␊ |
627 | ␉␉␊ |
628 | }␊ |
629 | ␊ |
630 | ␊ |
631 | static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊ |
632 | ␉␉␉␉␉␉unsigned long *clock,␊ |
633 | ␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊ |
634 | ␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊ |
635 | {␊ |
636 | ␉UInt32 hbl, vbl, vfreq;␊ |
637 | ␉␊ |
638 | ␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊ |
639 | ␉vfreq = vbl * freq;␊ |
640 | ␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊ |
641 | ␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊ |
642 | ␉␊ |
643 | ␉*vsyncstart = y;␊ |
644 | ␉*vsyncend = y + 3;␊ |
645 | ␉*vblank = vbl - 1;␊ |
646 | ␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊ |
647 | ␉*hsyncend = x + hbl / 2 - 1;␊ |
648 | ␉*hblank = x + hbl - 1;␊ |
649 | ␉*clock = (x + hbl) * vfreq / 1000;␊ |
650 | }␊ |
651 | ␊ |
652 | void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊ |
653 | ␉UInt32 xprev, yprev;␊ |
654 | ␉UInt32 i = 0, j;␊ |
655 | ␉// patch first available mode␊ |
656 | ␉␊ |
657 | ␉//␉for (i=0; i < map->mode_table_size; i++) {␊ |
658 | ␉//␉␉if (map->mode_table[0].mode == mode) {␊ |
659 | ␉switch(map->bios) {␊ |
660 | ␉␉case BT_INTEL:␊ |
661 | ␉␉␉return;␊ |
662 | ␊ |
663 | ␉␉case BT_1:␊ |
664 | ␉␉{␊ |
665 | ␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊ |
666 | ␉␉␉␊ |
667 | ␉␉␉if (bp) {␊ |
668 | ␉␉␉␉map->mode_table[i].bits_per_pixel = bp;␊ |
669 | ␉␉␉}␊ |
670 | ␉␉␉␊ |
671 | ␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊ |
672 | ␉␉␉res->x1 = (x & 0xff);␊ |
673 | ␉␉␉␊ |
674 | ␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊ |
675 | ␉␉␉res->y1 = (y & 0xff);␊ |
676 | ␉␉␉if (htotal)␊ |
677 | ␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊ |
678 | ␉␉␉␊ |
679 | ␉␉␉if (vtotal)␊ |
680 | ␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊ |
681 | ␉␉␉␊ |
682 | ␉␉␉break;␊ |
683 | ␉␉}␊ |
684 | ␉␉case BT_2:␊ |
685 | ␉␉{␊ |
686 | ␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊ |
687 | ␉␉␉␊ |
688 | ␉␉␉res->xchars = x / 8;␊ |
689 | ␉␉␉res->ychars = y / 16 - 1;␊ |
690 | ␉␉␉xprev = res->modelines[0].x1;␊ |
691 | ␉␉␉yprev = res->modelines[0].y1;␊ |
692 | ␉␉␉␊ |
693 | ␉␉␉for(j=0; j < 3; j++) {␊ |
694 | ␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊ |
695 | ␉␉␉␉␊ |
696 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊ |
697 | ␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊ |
698 | ␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊ |
699 | ␉␉␉␉␉␊ |
700 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
701 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
702 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
703 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
704 | ␉␉␉␉␉␊ |
705 | ␉␉␉␉␉if (htotal)␊ |
706 | ␉␉␉␉␉␉modeline->htotal = htotal;␊ |
707 | ␉␉␉␉␉else␊ |
708 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
709 | ␉␉␉␉␉␊ |
710 | ␉␉␉␉␉if (vtotal)␊ |
711 | ␉␉␉␉␉␉modeline->vtotal = vtotal;␊ |
712 | ␉␉␉␉␉else␊ |
713 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
714 | ␉␉␉␉}␊ |
715 | ␉␉␉}␊ |
716 | ␉␉␉break;␊ |
717 | ␉␉}␊ |
718 | ␉␉case BT_3:␊ |
719 | ␉␉{␊ |
720 | ␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊ |
721 | ␉␉␉␊ |
722 | ␉␉␉xprev = res->modelines[0].x1;␊ |
723 | ␉␉␉yprev = res->modelines[0].y1;␊ |
724 | ␉␉␉␊ |
725 | ␉␉␉for (j=0; j < 3; j++) {␊ |
726 | ␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊ |
727 | ␉␉␉␉␊ |
728 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊ |
729 | ␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊ |
730 | ␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊ |
731 | ␉␉␉␉␉␊ |
732 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
733 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
734 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
735 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
736 | ␉␉␉␉␉if (htotal)␊ |
737 | ␉␉␉␉␉␉modeline->htotal = htotal;␊ |
738 | ␉␉␉␉␉else␊ |
739 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
740 | ␉␉␉␉␉if (vtotal)␊ |
741 | ␉␉␉␉␉␉modeline->vtotal = vtotal;␊ |
742 | ␉␉␉␉␉else␊ |
743 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
744 | ␉␉␉␉␉␊ |
745 | ␉␉␉␉␉modeline->timing_h = y-1;␊ |
746 | ␉␉␉␉␉modeline->timing_v = x-1;␊ |
747 | ␉␉␉␉}␊ |
748 | ␉␉␉}␊ |
749 | ␉␉␉break;␊ |
750 | ␉␉}␊ |
751 | ␉␉case BT_ATI_1:␊ |
752 | ␉␉{␊ |
753 | ␉␉␉edid_mode mode;␊ |
754 | ␉␉␉␉␊ |
755 | ␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊ |
756 | ␊ |
757 | ␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊ |
758 | ␉␉␉if (!getMode(&mode)) {␊ |
759 | ␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊ |
760 | ␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊ |
761 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
762 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊ |
763 | ␉␉␉␉␉␊ |
764 | ␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊ |
765 | ␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊ |
766 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
767 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊ |
768 | ␊ |
769 | ␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊ |
770 | ␉␉␉}␊ |
771 | ␉␉␉/*else␊ |
772 | ␉␉␉{␊ |
773 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
774 | ␊ |
775 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
776 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
777 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
778 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
779 | ␊ |
780 | ␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊ |
781 | ␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊ |
782 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊ |
783 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
784 | ␊ |
785 | ␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊ |
786 | ␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊ |
787 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊ |
788 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊ |
789 | ␉␉␉␉␉␉␉␉␉␉␉␉␊ |
790 | ␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊ |
791 | ␉␉␉ }*/␊ |
792 | ␉␊ |
793 | ␉␉␉break;␊ |
794 | ␉␉}␊ |
795 | ␉␉case BT_ATI_2:␊ |
796 | ␉␉{␊ |
797 | ␉␉␉edid_mode mode;␊ |
798 | ␉␉␉␉␉␉␊ |
799 | ␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊ |
800 | ␉␉␉␊ |
801 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
802 | ␉␉␉if (!getMode(&mode)) {␊ |
803 | ␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊ |
804 | ␉␉␉␉mode_timing->usHActive = mode.h_active;␊ |
805 | ␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊ |
806 | ␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊ |
807 | ␉␉␉␉␉␉␉␉␉␉␊ |
808 | ␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊ |
809 | ␉␉␉␉mode_timing->usVActive = mode.v_active;␊ |
810 | ␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊ |
811 | ␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊ |
812 | ␉␉␉␉␉␉␉␉␉␉␊ |
813 | ␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊ |
814 | ␉␉␉}␊ |
815 | ␉␉␉/*else␊ |
816 | ␉␉␉{␊ |
817 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
818 | ␉␉␉␊ |
819 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
820 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
821 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
822 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
823 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
824 | ␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊ |
825 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHActive = x;␊ |
826 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊ |
827 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
828 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊ |
829 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊ |
830 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVActive = y;␊ |
831 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊ |
832 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
833 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊ |
834 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊ |
835 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉}*/␊ |
836 | ␉␉␉␉␊ |
837 | ␉␉␉␊ |
838 | ␉␉␉break;␊ |
839 | ␉␉}␊ |
840 | ␉␉case BT_NVDA:␊ |
841 | ␉␉{␊ |
842 | ␉␉␉edid_mode mode;␊ |
843 | ␉␉␉␊ |
844 | ␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊ |
845 | ␉␉␉␊ |
846 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
847 | ␉␉␉if (!getMode(&mode)) {␊ |
848 | ␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊ |
849 | ␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊ |
850 | ␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
851 | ␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊ |
852 | ␉␉␉␉␊ |
853 | ␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊ |
854 | ␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊ |
855 | ␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
856 | ␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊ |
857 | ␉␉␉␉␊ |
858 | ␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊ |
859 | ␉␉␉}␊ |
860 | ␉␉␉/*else␊ |
861 | ␉␉␉ {␊ |
862 | ␉␉␉ vbios_modeline_type2 modeline;␊ |
863 | ␉␉␉ ␊ |
864 | ␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
865 | ␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊ |
866 | ␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊ |
867 | ␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊ |
868 | ␉␉␉ ␊ |
869 | ␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊ |
870 | ␉␉␉ mode_timing[i].usH_Active = x;␊ |
871 | ␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊ |
872 | ␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊ |
873 | ␉␉␉ ␊ |
874 | ␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊ |
875 | ␉␉␉ mode_timing[i].usV_Active = y;␊ |
876 | ␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊ |
877 | ␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊ |
878 | ␉␉␉ ␊ |
879 | ␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊ |
880 | ␉␉␉ }*/␊ |
881 | ␉␉␉break;␊ |
882 | ␉␉}␊ |
883 | ␉␉case BT_UNKWN:␊ |
884 | ␉␉{␊ |
885 | ␉␉␉break;␊ |
886 | ␉␉}␊ |
887 | ␉}␊ |
888 | ␉//␉␉}␊ |
889 | ␉//␉}␊ |
890 | }␊ |
891 | ␊ |
892 | #endif // _RESOLUTION_H_ |