1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | //#include "mem.h"␊ |
9 | #include "smbios_patcher.h"␊ |
10 | #include "cpu.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␉␉msglog(x)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
24 | */␊ |
25 | static uint64_t measure_tsc_frequency(void)␊ |
26 | {␊ |
27 | uint64_t tscStart;␊ |
28 | uint64_t tscEnd;␊ |
29 | uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
30 | unsigned long pollCount;␊ |
31 | uint64_t retval = 0;␊ |
32 | int i;␊ |
33 | ␊ |
34 | /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
35 | * counter 2. We run this loop 3 times to make sure the cache␊ |
36 | * is hot and we take the minimum delta from all of the runs.␊ |
37 | * That is to say that we're biased towards measuring the minimum␊ |
38 | * number of TSC ticks that occur while waiting for the timer to␊ |
39 | * expire. That theoretically helps avoid inconsistencies when␊ |
40 | * running under a VM if the TSC is not virtualized and the host␊ |
41 | * steals time. The TSC is normally virtualized for VMware.␊ |
42 | */␊ |
43 | for(i = 0; i < 10; ++i)␊ |
44 | {␊ |
45 | enable_PIT2();␊ |
46 | set_PIT2_mode0(CALIBRATE_LATCH);␊ |
47 | tscStart = rdtsc64();␊ |
48 | pollCount = poll_PIT2_gate();␊ |
49 | tscEnd = rdtsc64();␊ |
50 | /* The poll loop must have run at least a few times for accuracy */␊ |
51 | if(pollCount <= 1)␊ |
52 | continue;␊ |
53 | /* The TSC must increment at LEAST once every millisecond. We␊ |
54 | * should have waited exactly 30 msec so the TSC delta should␊ |
55 | * be >= 30. Anything less and the processor is way too slow.␊ |
56 | */␊ |
57 | if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
58 | continue;␊ |
59 | // tscDelta = min(tscDelta, (tscEnd - tscStart))␊ |
60 | if( (tscEnd - tscStart) < tscDelta )␊ |
61 | tscDelta = tscEnd - tscStart;␊ |
62 | }␊ |
63 | /* tscDelta is now the least number of TSC ticks the processor made in␊ |
64 | * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
65 | * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
66 | * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
67 | * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
68 | * dividing by the milliseconds, we simply multiply by 1000.␊ |
69 | */␊ |
70 | ␊ |
71 | /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
72 | * that we're going to multiply by 1000 first so we do need at least some␊ |
73 | * arithmetic headroom. For now, 32-bit should be enough.␊ |
74 | * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
75 | */␊ |
76 | if(tscDelta > (1ULL<<32))␊ |
77 | retval = 0;␊ |
78 | else␊ |
79 | {␊ |
80 | retval = tscDelta * 1000 / 30;␊ |
81 | }␊ |
82 | disable_PIT2();␊ |
83 | return retval;␊ |
84 | }␊ |
85 | ␊ |
86 | /*␊ |
87 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
88 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
89 | * a max multi. (used to calculate the FSB freq.),␊ |
90 | * and a current multi. (used to calculate the CPU freq.)␊ |
91 | * - fsbFrequency = tscFrequency / multi␊ |
92 | * - cpuFrequency = fsbFrequency * multi␊ |
93 | */␊ |
94 | ␊ |
95 | void scan_cpu() //PlatformInfo_t *p)␊ |
96 | {␊ |
97 | ␉PlatformInfo_t *p = Platform;␊ |
98 | ␉int i = 0;␊ |
99 | ␉uint8_t turbo = 0;␊ |
100 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊ |
101 | ␉uint64_t␉msr; //, flex_ratio;␊ |
102 | ␉uint8_t␉␉maxcoef, maxdiv, currcoef, currdiv, mindiv;␊ |
103 | ␊ |
104 | ␉maxcoef = maxdiv = currcoef = currdiv = mindiv = 0;␊ |
105 | ␉␊ |
106 | #if DEBUG_CPU␊ |
107 | ␉printf("Enter cpuid_info\n");␊ |
108 | ␉pause();␊ |
109 | #endif␊ |
110 | ␉cpuid_update_generic_info();␊ |
111 | ␉␊ |
112 | #if DEBUG_CPU␊ |
113 | ␉printf("...OK\n");␊ |
114 | ␉pause();␊ |
115 | #endif␊ |
116 | ␉␊ |
117 | #if OLDMETHOD␉␊ |
118 | ␉/* get cpuid values */␊ |
119 | ␉for( ; i <= 3; i++)␊ |
120 | ␉{␊ |
121 | ␉␉do_cpuid(i, p->CPU.CPUID[i]);␊ |
122 | ␉}␊ |
123 | ␉␊ |
124 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
125 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
126 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊ |
127 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
128 | ␉}␊ |
129 | #if DEBUG_CPU␊ |
130 | ␉{␊ |
131 | ␉␉int␉␉i;␊ |
132 | ␉␉DBG("CPUID Raw Values:\n");␊ |
133 | ␉␉for (i=0; i<CPUID_MAX; i++) {␊ |
134 | ␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
135 | ␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
136 | ␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
137 | ␉␉}␊ |
138 | ␉}␊ |
139 | #endif␊ |
140 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
141 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
142 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
143 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
144 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
145 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
146 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
147 | ␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
148 | ␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
149 | ␊ |
150 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
151 | ␉␊ |
152 | ␉/* get brand string (if supported) */␊ |
153 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
154 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊ |
155 | ␉␉uint32_t␉reg[4];␊ |
156 | char str[128], *s;␊ |
157 | ␉␉/*␊ |
158 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
159 | ␉␉ * be NUL terminated.␊ |
160 | ␉␉ */␊ |
161 | ␉␉do_cpuid(0x80000002, reg);␊ |
162 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
163 | ␉␉do_cpuid(0x80000003, reg);␊ |
164 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
165 | ␉␉do_cpuid(0x80000004, reg);␊ |
166 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
167 | ␉␉for (s = str; *s != '\0'; s++) {␊ |
168 | ␉␉␉if (*s != ' ') break;␊ |
169 | ␉␉}␊ |
170 | ␉␉␊ |
171 | ␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊ |
172 | ␉␉␊ |
173 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
174 | ␉␉␉ /*␊ |
175 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
176 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
177 | ␉␉␉ */␊ |
178 | ␉␉␉ p->CPU.BrandString[0] = '\0';␊ |
179 | ␉␉ }␊ |
180 | ␉}␊ |
181 | ␉␊ |
182 | ␉/* setup features */␊ |
183 | ␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR) & p->CPU.CPUID[CPUID_1][3];␊ |
184 | ␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42) & p->CPU.CPUID[CPUID_1][2];␉␊ |
185 | ␉p->CPU.Features |= (CPU_FEATURE_EM64T) & p->CPU.CPUID[CPUID_81][3];␊ |
186 | ␊ |
187 | ␊ |
188 | ␉//if ((CPU_FEATURE_HTT & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
189 | ␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊ |
190 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
191 | ␉}␊ |
192 | #else //Slice␊ |
193 | ␉p->CPU.Vendor␉␉= *(UInt32*)&cpuid_info()->cpuid_vendor;␊ |
194 | ␉p->CPU.Signature␉= cpuid_info()->cpuid_signature;␊ |
195 | ␉p->CPU.Stepping␉␉= cpuid_info()->cpuid_stepping;␊ |
196 | ␉p->CPU.Model␉␉= cpuid_info()->cpuid_model;␊ |
197 | ␉p->CPU.Family␉␉= cpuid_info()->cpuid_family;␊ |
198 | ␉p->CPU.ExtModel␉␉= cpuid_info()->cpuid_extmodel;␊ |
199 | ␉p->CPU.ExtFamily␉= cpuid_info()->cpuid_extfamily;␊ |
200 | //␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊ |
201 | //␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊ |
202 | ␉␊ |
203 | ␉strlcpy(p->CPU.BrandString, cpuid_info()->cpuid_brand_string, sizeof(p->CPU.BrandString));␊ |
204 | ␉DBG("CPU: BrandString %s\n", p->CPU.BrandString);␊ |
205 | ␉p->CPU.Features = cpuid_info()->cpuid_features;␊ |
206 | ␉p->CPU.NoCores = cpuid_info()->core_count;␊ |
207 | ␉p->CPU.NoThreads = cpuid_info()->thread_count;␊ |
208 | //␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊ |
209 | //␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊ |
210 | //␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
211 | //␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
212 | //␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
213 | //␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
214 | //␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
215 | #if DEBUG_CPU␊ |
216 | ␉pause();␊ |
217 | #endif␊ |
218 | ␉␊ |
219 | #endif␊ |
220 | ␊ |
221 | ␉tscFrequency = measure_tsc_frequency();␊ |
222 | ␉DBG("measure_tsc_frequency = %dMHz\n", tscFrequency / MEGA);␊ |
223 | ␉fsbFrequency = 0;␊ |
224 | ␉cpuFrequency = 0;␊ |
225 | ␊ |
226 | ␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ␊ |
227 | ␉␉((p->CPU.Family == 0x06) || ␊ |
228 | ␉␉ (p->CPU.Family == 0x0f)))␊ |
229 | ␉{␊ |
230 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || ␊ |
231 | ␉␉␉(p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊ |
232 | ␉␉{␊ |
233 | ␉␉␉/* Nehalem CPU model */␊ |
234 | ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == 0x1a || p->CPU.Model == 0x1e ||␊ |
235 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == 0x1f || p->CPU.Model == 0x25 ||␊ |
236 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == 0x19 || p->CPU.Model == 0x2c)) ␊ |
237 | ␉␉␉{␊ |
238 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
239 | ␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊ |
240 | ␉␉␉␉(msr >> 32) & 0xffffffff, msr & 0xffffffff);␊ |
241 | ␉␉␉␉mindiv = (msr >> 40) & 0xff;␊ |
242 | ␉␉␉␉maxcoef = (msr >> 8) & 0xff; ␊ |
243 | ␉␉␉␉␊ |
244 | ␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO);␊ |
245 | ␉␉␉␉turbo = msr & 0x7f;␊ |
246 | ␉␉␉␉//Slice - doesn't work␊ |
247 | ␉␉␉␉/*␊ |
248 | ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
249 | ␉␉␉␉DBG("msr(0x%04x): flex_ratio %08x\n", MSR_FLEX_RATIO, msr & 0xffffffff);␊ |
250 | ␉␉␉␉if ((msr >> 16) & 0x01) {␊ |
251 | ␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊ |
252 | ␉␉␉␉␉if (currcoef > flex_ratio) {␊ |
253 | ␉␉␉␉␉␉currcoef = flex_ratio;␊ |
254 | ␉␉␉␉␉}␊ |
255 | ␉␉␉␉}*/␊ |
256 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
257 | ␉␉␉␉if (msr) {␊ |
258 | ␉␉␉␉␉currcoef = msr & 0x1f;␊ |
259 | ␉␉␉␉}␊ |
260 | ␉␉␉␉␊ |
261 | ␉␉␉␉if (!currcoef) {␊ |
262 | ␉␉␉␉␉currcoef = maxcoef;␊ |
263 | ␉␉␉␉}␊ |
264 | ␉␉␉␉␊ |
265 | ␉␉␉␉if (currcoef < mindiv) {␊ |
266 | ␉␉␉␉␉currcoef = mindiv;␊ |
267 | ␉␉␉␉}␊ |
268 | ␉␉␉␉␊ |
269 | ␉␉␉␉if (currcoef) {␊ |
270 | ␉␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
271 | ␉␉␉␉}␊ |
272 | ␉␉␉␉cpuFrequency = tscFrequency;␊ |
273 | ␉␉␉} ␊ |
274 | ␉␉␉else //not nehalem␊ |
275 | ␉␉␉{␊ |
276 | ␉␉␉␉//Slice - it is not FSB frequency. It is System Bus Speed: FSB = SBS * 4;␉␊ |
277 | ␉␉␉␉if (p->CPU.Family != 0x0d){␊ |
278 | ␉␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ);␊ |
279 | ␉␉␉␉␉switch (msr & 7) {␊ |
280 | ␉␉␉␉␉␉case 0:␊ |
281 | ␉␉␉␉␉␉␉fsbFrequency = 266670 * 1000;␊ |
282 | ␉␉␉␉␉␉␉break;␊ |
283 | ␉␉␉␉␉␉case 1:␊ |
284 | ␉␉␉␉␉␉␉fsbFrequency = 133330 * 1000;␊ |
285 | ␉␉␉␉␉␉␉break;␊ |
286 | ␉␉␉␉␉␉case 2:␊ |
287 | ␉␉␉␉␉␉␉fsbFrequency = 200000 * 1000;␊ |
288 | ␉␉␉␉␉␉␉break;␊ |
289 | ␉␉␉␉␉␉case 3:␊ |
290 | ␉␉␉␉␉␉␉fsbFrequency = 166670 * 1000;␊ |
291 | ␉␉␉␉␉␉␉break;␊ |
292 | ␉␉␉␉␉␉case 4:␊ |
293 | ␉␉␉␉␉␉␉fsbFrequency = 333330 * 1000;␊ |
294 | ␉␉␉␉␉␉␉break;␊ |
295 | ␉␉␉␉␉␉case 5:␊ |
296 | ␉␉␉␉␉␉␉fsbFrequency = 200000 * 1000;␊ |
297 | ␉␉␉␉␉␉␉break;␊ |
298 | ␉␉␉␉␉␉case 6:␊ |
299 | ␉␉␉␉␉␉␉fsbFrequency = 400000 * 1000;␊ |
300 | ␉␉␉␉␉␉␉break;␊ |
301 | ␉␉␉␉␉␉default:␊ |
302 | ␉␉␉␉␉␉␉fsbFrequency = 0;␊ |
303 | ␉␉␉␉␉␉␉break;␊ |
304 | ␉␉␉␉␉}␊ |
305 | ␉␉␉␉␉DBG("msr(0x%04x): MSR_FSB_FREQ %d.%dMHz\n", MSR_FSB_FREQ,␊ |
306 | ␉␉␉␉␉␉fsbFrequency/MEGA, (fsbFrequency%MEGA)/1000);␊ |
307 | ␉␉␉␉}␊ |
308 | ␉␉␉␉␊ |
309 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO); //info only?␊ |
310 | ␉␉␉␉uint32_t m2 = msr >> 32;␊ |
311 | ␉␉␉␉DBG("msr(0x%04x): platform_info %08x-%08x\n", MSR_PLATFORM_INFO,␊ |
312 | ␉␉␉␉␉m2 & 0xffffffff, msr & 0xffffffff);␊ |
313 | ␉␉␉␉turbo = (m2 >> 8) & 0x1f;␊ |
314 | ␉␉␉␉␊ |
315 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
316 | ␉␉␉␉m2 = msr >> 32;␊ |
317 | ␉␉␉␉DBG("msr(0x%04x): MSR_IA32_PERF_STATUS %08x-%08x\n", MSR_IA32_PERF_STATUS,␊ |
318 | ␉␉␉␉␉m2 & 0xffffffff, msr & 0xffffffff);␊ |
319 | ␉␉␉␉␊ |
320 | ␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊ |
321 | ␉␉␉␉mindiv = (msr >> 24) & 0xf;␊ |
322 | ␉␉␉␉if (currcoef < mindiv) {␊ |
323 | ␉␉␉␉␉currcoef = mindiv;␊ |
324 | ␉␉␉␉}␊ |
325 | ␉␉␉␉␊ |
326 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
327 | ␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊ |
328 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
329 | ␉␉␉␉currdiv = (msr >> 14) & 0x01;␊ |
330 | ␊ |
331 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || ␊ |
332 | ␉␉␉␉␉(p->CPU.Family == 0x0f)) // This will always be model >= 3␊ |
333 | ␉␉␉␉{␊ |
334 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
335 | ␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊ |
336 | ␉␉␉␉} ␊ |
337 | ␉␉␉␉else ␊ |
338 | ␉␉␉␉{␊ |
339 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
340 | ␉␉␉␉␉/* XXX */␊ |
341 | ␉␉␉␉␉maxcoef = currcoef;␊ |
342 | ␉␉␉␉}␊ |
343 | ␊ |
344 | ␉␉␉␉if (maxcoef) ␊ |
345 | ␉␉␉␉{␊ |
346 | ␉␉␉␉␉if (!fsbFrequency) {␊ |
347 | ␉␉␉␉␉␉if (maxdiv)␊ |
348 | ␉␉␉␉␉␉{␊ |
349 | ␉␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
350 | ␉␉␉␉␉␉}␊ |
351 | ␉␉␉␉␉␉else ␊ |
352 | ␉␉␉␉␉␉{␊ |
353 | ␉␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
354 | ␉␉␉␉␉␉}␊ |
355 | ␉␉␉␉␉␉␊ |
356 | ␉␉␉␉␉}␊ |
357 | ␉␉␉␉␉␊ |
358 | ␉␉␉␉␉if (currdiv) ␊ |
359 | ␉␉␉␉␉{␊ |
360 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
361 | ␉␉␉␉␉}␊ |
362 | ␉␉␉␉␉else ␊ |
363 | ␉␉␉␉␉{␊ |
364 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
365 | ␉␉␉␉␉}␊ |
366 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
367 | ␉␉␉␉}␊ |
368 | ␉␉␉}␊ |
369 | ␉␉}␊ |
370 | ␉␉/* Mobile CPU ? */␊ |
371 | //Slice ␊ |
372 | ␉␉msr = rdmsr64(MSR_IA32_PLATFORM_ID);␊ |
373 | ␉␉DBG("msr(0x%04x): MSR_IA32_PLATFORM_ID 0x%08x\n", MSR_IA32_PLATFORM_ID, msr & 0xffffffff); //__LINE__ - source line number :)␊ |
374 | ␉␉if (!scanDMI() && msr) {␊ |
375 | ␉␉␉p->CPU.Mobile = FALSE;␊ |
376 | ␉␉␉switch (p->CPU.Model) {␊ |
377 | ␉␉␉␉case 0x0D:␊ |
378 | ␉␉␉␉␉p->CPU.Mobile = TRUE; // CPU_FEATURE_MOBILE;␊ |
379 | ␉␉␉␉␉break;␊ |
380 | ␉␉␉␉case 0x0F:␊ |
381 | ␉␉␉␉␉p->CPU.Mobile = FALSE; // CPU_FEATURE_MOBILE;␊ |
382 | ␉␉␉␉␉break;␊ |
383 | ␉␉␉␉case 0x02:␊ |
384 | ␉␉␉␉case 0x03:␊ |
385 | ␉␉␉␉case 0x04:␊ |
386 | ␉␉␉␉case 0x06:␉␊ |
387 | ␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_P4_EBC_FREQUENCY_ID) && (1 << 21));␊ |
388 | ␉␉␉␉␉break;␊ |
389 | ␉␉␉␉default:␊ |
390 | ␉␉␉␉␉p->CPU.Mobile = (rdmsr64(MSR_IA32_PLATFORM_ID) && (1<<28));␊ |
391 | ␉␉␉␉␉break;␊ |
392 | ␉␉␉}␊ |
393 | ␉␉␉if (p->CPU.Mobile) {␊ |
394 | ␉␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
395 | ␉␉␉}␊ |
396 | ␉␉}␊ |
397 | ␉␉DBG("CPU is %s\n", p->CPU.Mobile?"Mobile":"Desktop");␊ |
398 | ␉␉␉␊ |
399 | ␉}␊ |
400 | #if 0␊ |
401 | ␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f))␊ |
402 | ␉{␊ |
403 | ␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */)␊ |
404 | ␉␉{␊ |
405 | ␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
406 | ␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊ |
407 | ␉␉␉currdiv = (msr & 0x01) * 2;␊ |
408 | ␉␉} ␊ |
409 | ␉␉else if(p->CPU.ExtFamily >= 0x01 /* K10+ */)␊ |
410 | ␉␉{␊ |
411 | ␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
412 | ␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊ |
413 | ␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊ |
414 | ␉␉␉else /* K11+ */␊ |
415 | ␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊ |
416 | ␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊ |
417 | ␉␉}␊ |
418 | ␊ |
419 | ␉␉if (currcoef) ␊ |
420 | ␉␉{␊ |
421 | ␉␉␉if (currdiv) ␊ |
422 | ␉␉␉{␊ |
423 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
424 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
425 | ␉␉␉}␊ |
426 | ␉␉␉else␊ |
427 | ␉␉␉{␊ |
428 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
429 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
430 | ␉␉␉}␊ |
431 | ␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
432 | ␉␉␉cpuFrequency = tscFrequency;␊ |
433 | ␉␉}␊ |
434 | ␉}␊ |
435 | #endif␊ |
436 | ␉else if(p->CPU.Vendor == 0x746e6543 && p->CPU.Family == 6)␊ |
437 | ␉{␊ |
438 | ␉␉switch (p->CPU.Model) {␊ |
439 | ␉␉␉case CPU_VIA_NANO:␊ |
440 | ␉␉␉␉// NOTE: TSC is constant, irrelevent of speed steping ␊ |
441 | ␉␉␉␉break;␊ |
442 | ␉␉␉default:␊ |
443 | ␉␉␉␉break;␊ |
444 | ␉␉}␊ |
445 | ␉␉␊ |
446 | ␉␉msr = rdmsr64(MSR_NANO_FCR2);␊ |
447 | ␉␉verbose("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊ |
448 | ␉␉␊ |
449 | ␉␉//msr = msr >> 32;␊ |
450 | ␉␉msr |= VIA_ALTERNATIVE_VENDOR_BIT;␊ |
451 | ␉␉//msr = msr << 32;␊ |
452 | ␉␉␊ |
453 | ␉␉verbose("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊ |
454 | ␉␉wrmsr64(MSR_NANO_FCR2, msr);␊ |
455 | ␉␉msr = rdmsr64(MSR_NANO_FCR2);␊ |
456 | ␉␉verbose("MSR_IA32_EBL_CR_POWERON Returns 0x%X 0x%X\n", msr >> 32, msr & 0xffffffff);␊ |
457 | ␉␉␊ |
458 | ␉␉␊ |
459 | ␉␉/* get cpuid values */␊ |
460 | ␉␉for( ; i <= 3; i++)␊ |
461 | ␉␉{␊ |
462 | ␉␉␉do_cpuid(i, p->CPU.CPUID[i]);␊ |
463 | ␉␉}␊ |
464 | ␉␉//int numcpuid_supported = p->CPU.CPUID[CPUID_0][0];␉// max number cpuid call␊ |
465 | ␉␉//int numextcpuid = p->CPU.CPUID[CPUID_80][0];␊ |
466 | ␉␉␉␉␉␉␉␉␉␉␉␉␉␉␉//p->CPU.Features = 0;␊ |
467 | ␉␉␉␉␉␉␉␉␉␉␉␉␉␉␉//␉␉bitfield(p->CPU.CPUID[CPUID_1][1], 0, 0) FEATURE_C␊ |
468 | ␉␉␊ |
469 | ␉␉// CPUID_0 -> largest cpuid val in EAX␊ |
470 | ␉␉// CPUID_0 -> rem = vendor string␊ |
471 | ␉␉/*␊ |
472 | ␉␉CPUID_1 EDX:␊ |
473 | ␉␉ 0 -> FPU␊ |
474 | ␉␉ 1 -> VME␊ |
475 | ␉␉ 2 -> DE␊ |
476 | ␉␉ 3 -> PSE␊ |
477 | ␉␉ 4 -> TSC␊ |
478 | ␉␉ 5 -> MSR␊ |
479 | ␉␉ 6 -> PAE␊ |
480 | ␉␉ 7 -> MCE␊ |
481 | ␉␉ 8 -> CX8␊ |
482 | ␉␉ 9 -> APIC␊ |
483 | ␉␉ 10 -> Reserved␊ |
484 | ␉␉ 11 -> Fast Call␊ |
485 | ␉␉ 12 -> MTTR␊ |
486 | ␉␉ 13 -> PGE␊ |
487 | ␉␉ 14 -> MCA␊ |
488 | ␉␉ 15 -> CMOV␊ |
489 | ␉␉ 16 -> PAT␊ |
490 | ␉␉ 17 -> PSE36␊ |
491 | ␉␉ 18 -> Serial Number ␊ |
492 | ␉␉ 23 -> MMX␊ |
493 | ␉␉ 24 -> FXSR␊ |
494 | ␉␉ 25 -> SSE␊ |
495 | ␉␉ */␊ |
496 | ␉␉␊ |
497 | ␉␉//CPUID_80 -> largest excpuid value in EAX␊ |
498 | ␉␉//CPUID_81,EAX -> Signature␊ |
499 | ␉␉//CPUID_80,EDX -> Ext Features␊ |
500 | ␉␉//CPUID_82 -> CPU String␊ |
501 | ␉␉//CPUID_83 -> CPU String␊ |
502 | ␉␉//CPUID_84 -> CPU String␊ |
503 | ␉␉p->CPU.NoThreads = p->CPU.NoCores;␊ |
504 | ␉␉␊ |
505 | ␉}␊ |
506 | ␉␊ |
507 | ␉if (!fsbFrequency) {␊ |
508 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
509 | ␉␉cpuFrequency = tscFrequency;␊ |
510 | ␉␉msglog("CPU: fsb=0 ! using the default value 100MHz !\n");␊ |
511 | ␉}␊ |
512 | ␉␊ |
513 | /*␉␊ |
514 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
515 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
516 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
517 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
518 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
519 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
520 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
521 | ␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
522 | */␉␊ |
523 | ␊ |
524 | ␊ |
525 | ␉p->CPU.MaxCoef = turbo;␊ |
526 | ␉p->CPU.MaxDiv = maxdiv;␊ |
527 | ␉p->CPU.MinCoef = mindiv;␊ |
528 | ␉p->CPU.CurrCoef = currcoef;␊ |
529 | ␉p->CPU.CurrDiv = currdiv;␊ |
530 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
531 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
532 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
533 | ␉DBG("CPU: Brand: %s\n", p->CPU.BrandString);␊ |
534 | ␉DBG("CPU: Vendor/Model/ExtModel: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Model, p->CPU.ExtModel);␊ |
535 | ␉DBG("CPU: Family/ExtFamily: 0x%x/0x%x\n", p->CPU.Family, p->CPU.ExtFamily);␊ |
536 | ␉DBG("CPU: MaxCoef/CurrCoef/Turbo: 0x%x/0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef, turbo);␊ |
537 | ␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv?2:1, p->CPU.CurrDiv?2:1);␊ |
538 | ␉DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
539 | ␉DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
540 | ␉DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
541 | ␉DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
542 | ␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
543 | #if DEBUG_CPU␊ |
544 | ␉pause();␊ |
545 | #endif␊ |
546 | }␊ |
547 | |