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Source at commit 1547 created 12 years 10 months ago. By blackosx, Added UseKernelCache boot option to svn | |
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1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #ifndef __LIBSAIO_CPU_H␊ |
7 | #define __LIBSAIO_CPU_H␊ |
8 | ␊ |
9 | //#include "libsaio.h"␊ |
10 | ␊ |
11 | extern void scan_cpu(PlatformInfo_t *);␊ |
12 | ␊ |
13 | #define bit(n)␉␉␉(1ULL << (n))␊ |
14 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
15 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
16 | ␊ |
17 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
18 | ␊ |
19 | #define␉MSR_IA32_PERF_STATUS␉0x00000198␊ |
20 | #define MSR_IA32_PERF_CONTROL␉0x199␊ |
21 | #define MSR_IA32_EXT_CONFIG␉␉0x00EE␊ |
22 | #define MSR_FLEX_RATIO␉␉␉0x194␊ |
23 | #define MSR_TURBO_RATIO_LIMIT␉0x1AD␊ |
24 | #define␉MSR_PLATFORM_INFO␉␉0xCE␊ |
25 | #define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊ |
26 | #define MSR_IA32_PLATFORM_ID␉0x17␊ |
27 | ␊ |
28 | #define K8_FIDVID_STATUS␉␉0xC0010042␊ |
29 | #define K10_COFVID_STATUS␉␉0xC0010071␊ |
30 | ␊ |
31 | #define MSR_AMD_MPERF 0x000000E7␊ |
32 | #define MSR_AMD_APERF 0x000000E8␊ |
33 | ␊ |
34 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
35 | ␊ |
36 | // DFE: This constant comes from older xnu:␊ |
37 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
38 | ␊ |
39 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
40 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
41 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
42 | ␊ |
43 | // CPUID Values␊ |
44 | #define CPUID_MODEL_YONAH␉␉14␉// Intel Mobile Core Solo, Duo␊ |
45 | #define CPUID_MODEL_MEROM␉␉15␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
46 | #define CPUID_MODEL_PENRYN␉␉23␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
47 | #define CPUID_MODEL_NEHALEM␉␉26␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
48 | #define CPUID_MODEL_ATOM␉␉28␉// Intel Atom (45nm)␊ |
49 | #define CPUID_MODEL_FIELDS␉␉30␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
50 | #define CPUID_MODEL_DALES␉␉31␉// Havendale, Auburndale␊ |
51 | #define CPUID_MODEL_DALES_32NM␉37␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
52 | #define CPUID_MODEL_SANDY␉␉42␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
53 | #define CPUID_MODEL_WESTMERE␉44␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
54 | #define CPUID_MODEL_NEHALEM_EX␉46␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
55 | #define CPUID_MODEL_WESTMERE_EX␉47␉// Intel Xeon E7␊ |
56 | ␊ |
57 | ␊ |
58 | static inline uint64_t rdtsc64(void)␊ |
59 | {␊ |
60 | ␉uint64_t ret;␊ |
61 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
62 | ␉return ret;␊ |
63 | }␊ |
64 | ␊ |
65 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
66 | {␊ |
67 | uint64_t ret;␊ |
68 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
69 | return ret;␊ |
70 | }␊ |
71 | ␊ |
72 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
73 | {␊ |
74 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
75 | }␊ |
76 | ␊ |
77 | static inline void intel_waitforsts(void) {␊ |
78 | ␉uint32_t inline_timeout = 100000;␊ |
79 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
80 | }␊ |
81 | ␊ |
82 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
83 | {␊ |
84 | ␉asm volatile ("cpuid"␊ |
85 | ␉␉␉␉ : "=a" (data[0]),␊ |
86 | ␉␉␉␉ "=b" (data[1]),␊ |
87 | ␉␉␉␉ "=c" (data[2]),␊ |
88 | ␉␉␉␉ "=d" (data[3])␊ |
89 | ␉␉␉␉ : "a" (selector));␊ |
90 | }␊ |
91 | ␊ |
92 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
93 | {␊ |
94 | ␉asm volatile ("cpuid"␊ |
95 | ␉␉␉␉ : "=a" (data[0]),␊ |
96 | ␉␉␉␉ "=b" (data[1]),␊ |
97 | ␉␉␉␉ "=c" (data[2]),␊ |
98 | ␉␉␉␉ "=d" (data[3])␊ |
99 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
100 | }␊ |
101 | ␊ |
102 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
103 | ␊ |
104 | /*␊ |
105 | * Enable or disable timer 2.␊ |
106 | * Port 0x61 controls timer 2:␊ |
107 | * bit 0 gates the clock,␊ |
108 | * bit 1 gates output to speaker.␊ |
109 | */␊ |
110 | static inline void enable_PIT2(void)␊ |
111 | {␊ |
112 | /* Enable gate, disable speaker */␊ |
113 | __asm__ volatile(␊ |
114 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
115 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
116 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
117 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
118 | ␉␉␉␉␉ : : : "%al" );␊ |
119 | }␊ |
120 | ␊ |
121 | static inline void disable_PIT2(void)␊ |
122 | {␊ |
123 | /* Disable gate and output to speaker */␊ |
124 | __asm__ volatile(␊ |
125 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
126 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
127 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
128 | ␉␉␉␉␉ : : : "%al" );␊ |
129 | }␊ |
130 | ␊ |
131 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
132 | // roughly based on Linux code␊ |
133 | ␊ |
134 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
135 | In mode 0, the counter will initially set its gate low when the␊ |
136 | timer expires. For this to be useful, you ought to set it high␊ |
137 | before calling this function. The enable_PIT2 function does this.␊ |
138 | */␊ |
139 | static inline void set_PIT2_mode0(uint16_t value)␊ |
140 | {␊ |
141 | __asm__ volatile(␊ |
142 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
143 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
144 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
145 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
146 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
147 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
148 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
149 | }␊ |
150 | ␊ |
151 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
152 | static inline unsigned long poll_PIT2_gate(void)␊ |
153 | {␊ |
154 | unsigned long count = 0;␊ |
155 | unsigned char nmi_sc_val;␊ |
156 | do {␊ |
157 | ++count;␊ |
158 | __asm__ volatile(␊ |
159 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
160 | ␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
161 | } while( (nmi_sc_val & 0x20) == 0);␊ |
162 | return count;␊ |
163 | }␊ |
164 | ␊ |
165 | #endif /* !__LIBSAIO_CPU_H */␊ |
166 |