1 | /*␊ |
2 | * Copyright 2010,2011 valv, cparm <armelcadetpetit@gmail.com>. All rights reserved.␊ |
3 | */␊ |
4 | #include "boot.h"␊ |
5 | #include "bootstruct.h"␊ |
6 | #include "libsaio.h"␊ |
7 | #include "modules.h"␊ |
8 | #include "Platform.h"␊ |
9 | #include "cpu.h"␊ |
10 | ␊ |
11 | #define kFixFSB␉␉ "FixFSB"␊ |
12 | #define MSR_FSB_FREQ␉␉0x000000cd␊ |
13 | #define AMD_10H_11H_CONFIG 0xc0010064␊ |
14 | #define kEnableCPUfreq␉"EnableCPUfreqModule"␊ |
15 | ␊ |
16 | void CPUfreq_hook(void* arg1, void* arg2, void* arg3, void* arg4, void* arg5, void* arg6)␊ |
17 | {␉␊ |
18 | ␉int bus_ratio;␉␉␉␉ ␊ |
19 | ␉uint64_t␉msr , fsbFrequency , cpuFrequency , minfsb , maxfsb ;␊ |
20 | ␉␊ |
21 | ␉if ((Platform->CPU.Vendor == 0x756E6547 /* Intel */) && ((Platform->CPU.Family == 0x06) || (Platform->CPU.Family == 0x0f)))␊ |
22 | ␉{␊ |
23 | ␉␉if ((Platform->CPU.Family == 0x06 && Platform->CPU.Model >= 0x0c) || (Platform->CPU.Family == 0x0f && Platform->CPU.Model >= 0x03))␊ |
24 | ␉␉{␊ |
25 | ␉␉␉␊ |
26 | ␉␉␉if (Platform->CPU.Family == 0x06)␊ |
27 | ␉␉␉{␊ |
28 | ␉␉␉␉␊ |
29 | ␉␉␉␉bus_ratio = 0; ␉␉␉␉␉␉␉␉ ␊ |
30 | ␉␉␉␉msr = rdmsr64(MSR_FSB_FREQ); ␊ |
31 | ␉␉␉␉fsbFrequency = 0;␊ |
32 | ␉␉␉␉cpuFrequency = 0; ␊ |
33 | ␉␉␉␉minfsb = 183000000; ␊ |
34 | ␉␉␉␉maxfsb = 185000000;␊ |
35 | ␉␉␉␉␊ |
36 | ␉␉␉␉bool␉␉fix_fsb = false;␉␉␉␉␊ |
37 | ␉␉␉␉uint16_t idlo;␊ |
38 | ␉␉␉␉uint8_t crlo, crhi = 0;␉␉␉␉␊ |
39 | ␉␉␉␉␊ |
40 | ␉␉␉␉switch (Platform->CPU.Model) {␊ |
41 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Core Duo/Solo, Pentium M DC␊ |
42 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Core Xeon, Core 2 DC, 65nm␊ |
43 | ␉␉␉␉␉case 0x16:␉␉␉␉␉// Celeron, Core 2 SC, 65nm␊ |
44 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉// Core 2 Duo/Extreme, Xeon, 45nm␊ |
45 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Atom :)␊ |
46 | ␉␉␉␉␉case 0x27:␉␉␉␉␉// Atom Lincroft, 45nm ␊ |
47 | ␉␉␉␉␉{␊ |
48 | ␉␉␉␉␉␉getBoolForKey(kFixFSB, &fix_fsb, &bootInfo->bootConfig); ␊ |
49 | ␉␉␉␉␉␉␊ |
50 | ␉␉␉␉␉␉if (fix_fsb)␊ |
51 | ␉␉␉␉␉␉{␊ |
52 | ␉␉␉␉␉␉␉␊ |
53 | ␉␉␉␉␉␉␉int bus = (msr >> 0) & 0x7; ␊ |
54 | ␉␉␉␉␉␉␉switch (bus) {␊ |
55 | ␉␉␉␉␉␉␉␉case 0:␊ |
56 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 266666667;␊ |
57 | ␉␉␉␉␉␉␉␉␉break;␊ |
58 | ␉␉␉␉␉␉␉␉case 1:␊ |
59 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 133333333;␊ |
60 | ␉␉␉␉␉␉␉␉␉break;␊ |
61 | ␉␉␉␉␉␉␉␉case 2:␊ |
62 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
63 | ␉␉␉␉␉␉␉␉␉break;␊ |
64 | ␉␉␉␉␉␉␉␉case 3:␊ |
65 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 166666667;␊ |
66 | ␉␉␉␉␉␉␉␉␉break;␊ |
67 | ␉␉␉␉␉␉␉␉case 4:␊ |
68 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 333333333;␊ |
69 | ␉␉␉␉␉␉␉␉␉break;␊ |
70 | ␉␉␉␉␉␉␉␉case 5:␊ |
71 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 100000000;␊ |
72 | ␉␉␉␉␉␉␉␉␉break;␊ |
73 | ␉␉␉␉␉␉␉␉case 6:␊ |
74 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 400000000;␊ |
75 | ␉␉␉␉␉␉␉␉␉break;␊ |
76 | ␉␉␉␉␉␉␉␉default:␊ |
77 | ␉␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␉␉␉␉␉␉␉␉␉␊ |
78 | ␉␉␉␉␉␉␉␉␉break;␊ |
79 | ␉␉␉␉␉␉␉}␊ |
80 | ␉␉␉␉␉␉␉␊ |
81 | ␉␉␉␉␉␉␉␊ |
82 | ␉␉␉␉␉␉␉if (((fsbFrequency) > (minfsb) && (fsbFrequency) < (maxfsb)) || (!fsbFrequency)) ␊ |
83 | ␉␉␉␉␉␉␉{␊ |
84 | ␉␉␉␉␉␉␉␉fsbFrequency = 200000000;␊ |
85 | ␉␉␉␉␉␉␉}␊ |
86 | ␉␉␉␉␉␉␉Platform->CPU.FSBFrequency = fsbFrequency;␊ |
87 | ␉␉␉␉␉␉}␊ |
88 | ␉␉␉␉␉␉␊ |
89 | ␉␉␉␉␉␉if (getIntForKey("MaxBusRatio", &bus_ratio, &bootInfo->bootConfig)) ␊ |
90 | ␉␉␉␉␉␉{ ␊ |
91 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
92 | ␉␉␉␉␉␉␉idlo = (msr >> 48) & 0xffff;␉␉␉␉␉␉␉␉␊ |
93 | ␉␉␉␉␉␉␉crlo = (idlo >> 8) & 0xff;␊ |
94 | ␉␉␉␉␉␉␉␊ |
95 | ␉␉␉␉␉␉␉//printf("CPUfreq: MinCoef: 0x%x\n",crlo);␊ |
96 | ␉␉␉␉␉␉␉␊ |
97 | ␉␉␉␉␉␉␉if (Platform->CPU.MaxCoef) ␊ |
98 | ␉␉␉␉␉␉␉{␊ |
99 | ␉␉␉␉␉␉␉␉if (Platform->CPU.MaxDiv) ␊ |
100 | ␉␉␉␉␉␉␉␉{␊ |
101 | ␉␉␉␉␉␉␉␉␉crhi = (Platform->CPU.MaxCoef * 10) + 5;␊ |
102 | ␉␉␉␉␉␉␉␉}␊ |
103 | ␉␉␉␉␉␉␉␉else ␊ |
104 | ␉␉␉␉␉␉␉␉{␊ |
105 | ␉␉␉␉␉␉␉␉␉crhi = Platform->CPU.MaxCoef * 10;␊ |
106 | ␉␉␉␉␉␉␉␉}␊ |
107 | ␉␉␉␉␉␉␉}␊ |
108 | ␉␉␉␉␉␉␉if (crlo == 0 || crhi == crlo) goto out;␉␉␉␉␉␉␉␉␊ |
109 | ␉␉␉␉␉␉␉␊ |
110 | ␉␉␉␉␉␉␉if ((bus_ratio >= (crlo *10)) && (crhi >= bus_ratio) ) ␊ |
111 | ␉␉␉␉␉␉␉␉//if (bus_ratio >= 60) ␊ |
112 | ␉␉␉␉␉␉␉{␉␉␉␉␉␉␉␉␊ |
113 | ␉␉␉␉␉␉␉␉uint8_t currdiv = 0, currcoef = 0;␊ |
114 | ␉␉␉␉␉␉␉␉␊ |
115 | ␉␉␉␉␉␉␉␉currcoef = (int)(bus_ratio / 10);␊ |
116 | ␉␉␉␉␉␉␉␉␊ |
117 | ␉␉␉␉␉␉␉␉uint8_t fdiv = bus_ratio - (currcoef * 10);␊ |
118 | ␉␉␉␉␉␉␉␉if (fdiv > 0)␊ |
119 | ␉␉␉␉␉␉␉␉␉currdiv = 1;␊ |
120 | ␉␉␉␉␉␉␉␉␊ |
121 | ␉␉␉␉␉␉␉␉Platform->CPU.CurrCoef = currcoef;␊ |
122 | ␉␉␉␉␉␉␉␉Platform->CPU.CurrDiv = currdiv;␉␉␉␉␉␉␉␉␉␊ |
123 | ␉␉␉␉␉␉␉}␊ |
124 | ␉␉␉␉␉␉␉␊ |
125 | ␉␉␉␉␉␉␉␊ |
126 | ␉␉␉␉␉␉}␉␉␉␉␉␉␉␉␊ |
127 | ␉␉␉␉␉␉␊ |
128 | ␉␉␉␉␉out:␊ |
129 | ␉␉␉␉␉␉if (Platform->CPU.CurrDiv) ␊ |
130 | ␉␉␉␉␉␉{␊ |
131 | ␉␉␉␉␉␉␉cpuFrequency = (Platform->CPU.FSBFrequency * ((Platform->CPU.CurrCoef * 2) + 1) / 2);␊ |
132 | ␉␉␉␉␉␉}␊ |
133 | ␉␉␉␉␉␉else ␊ |
134 | ␉␉␉␉␉␉{␊ |
135 | ␉␉␉␉␉␉␉cpuFrequency = (Platform->CPU.FSBFrequency * Platform->CPU.CurrCoef);␊ |
136 | ␉␉␉␉␉␉}␉␉␉␉␉␉␉␊ |
137 | ␉␉␉␉␉␉␊ |
138 | ␉␉␉␉␉␉Platform->CPU.CPUFrequency = cpuFrequency;␊ |
139 | ␉␉␉␉␉␉verbose("CPU: FSBFreq changed to: %dMHz\n", Platform->CPU.FSBFrequency / 1000000);␊ |
140 | ␉␉␉␉␉␉verbose("CPU: CPUFreq changed to: %dMHz\n", Platform->CPU.CPUFrequency / 1000000);␊ |
141 | ␉␉␉␉␉␉//verbose("CPUfreq: FSB Fix applied !\n");␉␉␉␉␉␉␉␊ |
142 | ␉␉␉␉␉␉␊ |
143 | ␉␉␉␉␉␉break;␊ |
144 | ␉␉␉␉␉}␉␉␉␉␉␉␊ |
145 | ␉␉␉␉␉case 0x1d:␉␉// Xeon MP MP 7400␊ |
146 | ␉␉␉␉␉default:␉␉␉␉␉␉␊ |
147 | ␉␉␉␉␉␉break;␊ |
148 | ␉␉␉␉}␊ |
149 | ␉␉␉}␊ |
150 | ␉␉}␊ |
151 | ␉}␊ |
152 | ␉else if(Platform->CPU.Vendor == 0x68747541 /* AMD */ && Platform->CPU.Family == 0x0f) // valv: work in progress␊ |
153 | ␉{␊ |
154 | ␉␉verbose("CPU: ");␊ |
155 | ␉␉// valv: mobility check␉␉␉ ␊ |
156 | ␉␉if ((strstr(Platform->CPU.BrandString, "obile") == 0) || (strstr(Platform->CPU.BrandString, "Atom") == 0))␊ |
157 | ␉␉{␊ |
158 | ␉␉␉Platform->CPU.isMobile = true;␊ |
159 | ␉␉}␊ |
160 | ␉␉␊ |
161 | ␉␉verbose("%s\n", Platform->CPU.BrandString);␊ |
162 | ␉␉uint8_t bus_ratio_current = 0;␊ |
163 | ␉␉␊ |
164 | ␉␉if(Platform->CPU.ExtFamily == 0x00 /* K8 */)␊ |
165 | ␉␉{␊ |
166 | ␉␉␉␊ |
167 | ␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
168 | ␉␉␉bus_ratio_current = (msr & 0x3f) / 2 + 4; ␊ |
169 | ␉␉␉Platform->CPU.CurrDiv = (msr & 0x01) * 2;␉␉␉␉␉ ␊ |
170 | ␉␉␉if (bus_ratio_current)␊ |
171 | ␉␉␉{␊ |
172 | ␉␉␉␉if (Platform->CPU.CurrDiv)␊ |
173 | ␉␉␉␉{␊ |
174 | ␉␉␉␉␉Platform->CPU.FSBFrequency = ((Platform->CPU.TSCFrequency * Platform->CPU.CurrDiv) / bus_ratio_current); // ?␊ |
175 | ␉␉␉␉}␊ |
176 | ␉␉␉␉else␊ |
177 | ␉␉␉␉{␊ |
178 | ␉␉␉␉␉Platform->CPU.FSBFrequency = (Platform->CPU.TSCFrequency / bus_ratio_current);␊ |
179 | ␉␉␉␉}␊ |
180 | ␉␉␉␉//fsbFrequency = (tscFrequency / bus_ratio_max); // ?␊ |
181 | ␉␉␉}␊ |
182 | ␉␉}␊ |
183 | ␉␉else if(Platform->CPU.ExtFamily >= 0x01 /* K10+ */)␊ |
184 | ␉␉{␊ |
185 | ␉␉␉␊ |
186 | ␉␉␉msr = rdmsr64(AMD_10H_11H_CONFIG);␊ |
187 | ␉␉␉bus_ratio_current = ((msr) & 0x3F);␊ |
188 | ␉␉␉Platform->CPU.CurrDiv = (2 << ((msr >> 6) & 0x07)) / 2;␊ |
189 | ␉␉␉Platform->CPU.FSBFrequency = (Platform->CPU.CPUFrequency / bus_ratio_current);␊ |
190 | ␉␉␉␊ |
191 | ␉␉␉␊ |
192 | ␉␉}␉␊ |
193 | ␉␉␊ |
194 | ␉␉if (!Platform->CPU.FSBFrequency) ␊ |
195 | ␉␉{␊ |
196 | ␉␉␉Platform->CPU.FSBFrequency = (DEFAULT_FSB * 1000);␊ |
197 | ␉␉␉verbose("0 ! using the default value for FSB !\n");␊ |
198 | ␉␉}␊ |
199 | ␉␉Platform->CPU.CurrCoef = bus_ratio_current / 10;␊ |
200 | ␉␉Platform->CPU.CPUFrequency = Platform->CPU.TSCFrequency;␊ |
201 | ␉␉␊ |
202 | ␉␉verbose("CPU (AMD): FSBFreq: %dMHz\n", Platform->CPU.FSBFrequency / 1000000);␊ |
203 | ␉␉verbose("CPU (AMD): CPUFreq: %dMHz\n", Platform->CPU.CPUFrequency / 1000000);␊ |
204 | ␉␉verbose("CPU (AMD): CurrCoef:␉␉␉ 0x%x\n", Platform->CPU.CurrCoef);␊ |
205 | ␉␉verbose("CPU (AMD): CurrDiv: 0x%x\n", Platform->CPU.CurrDiv);␉␊ |
206 | ␉}␉ ␊ |
207 | ␊ |
208 | }␊ |
209 | ␊ |
210 | void CPUfreq_start()␊ |
211 | {␉␊ |
212 | ␉bool enable = true;␊ |
213 | ␉getBoolForKey(kEnableCPUfreq, &enable, &bootInfo->bootConfig) ;␊ |
214 | ␉␊ |
215 | ␉if (enable)␊ |
216 | ␉{␊ |
217 | ␉␉if (Platform->CPU.Features & CPUID_FEATURE_MSR)␊ |
218 | ␉␉{␊ |
219 | ␉␉␉register_hook_callback("PreBoot", &CPUfreq_hook);␉␉␊ |
220 | ␉␉} ␊ |
221 | ␉␉else␊ |
222 | ␉␉{␊ |
223 | ␉␉␉verbose ("Unsupported CPU: CPUfreq disabled !!!\n");␉␉␊ |
224 | ␉␉}␉␊ |
225 | ␉}␊ |
226 | }␊ |
227 | |