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1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation on the rights to use, copy, modify, merge,
11 * publish, distribute, sublicense, and/or sell copies of the Software,
12 * and to permit persons to whom the Software is furnished to do so,
13 * subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 */
28
29/*
30 * Authors:
31 * Kevin E. Martin <martin@xfree86.org>
32 * Rickard E. Faith <faith@valinux.com>
33 * Alan Hourihane <alanh@fairlite.demon.co.uk>
34 *
35 * References:
36 *
37 * !!!! FIXME !!!!
38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical
39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April
40 * 1999.
41 *
42 * !!!! FIXME !!!!
43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N
44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.
45 *
46 */
47
48/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h
49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT
50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */
51
52#ifndef _ATI_REG_H_
53#define _ATI_REG_H_
54
55#define ATI_DATATYPE_VQ0
56#define ATI_DATATYPE_CI41
57#define ATI_DATATYPE_CI82
58#define ATI_DATATYPE_ARGB15553
59#define ATI_DATATYPE_RGB5654
60#define ATI_DATATYPE_RGB8885
61#define ATI_DATATYPE_ARGB88886
62#define ATI_DATATYPE_RGB3327
63#define ATI_DATATYPE_Y88
64#define ATI_DATATYPE_RGB89
65#define ATI_DATATYPE_CI1610
66#define ATI_DATATYPE_VYUY_42211
67#define ATI_DATATYPE_YVYU_42212
68#define ATI_DATATYPE_AYUV_44414
69#define ATI_DATATYPE_ARGB444415
70
71/* Registers for 2D/Video/Overlay */
72#define RADEON_ADAPTER_ID 0x0f2c /* PCI */
73#define RADEON_AGP_BASE 0x0170
74#define RADEON_AGP_CNTL 0x0174
75# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)
76# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)
77# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)
78# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)
79# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)
80# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)
81# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)
82# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)
83#define RADEON_STATUS_PCI_CONFIG 0x06
84# define RADEON_CAP_LIST 0x100000
85#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/
86# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */
87# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */
88# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */
89# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */
90#define RADEON_AGP_COMMAND 0x0f60 /* PCI */
91#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/
92# define RADEON_AGP_ENABLE (1<<8)
93#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */
94#define RADEON_AGP_STATUS 0x0f5c /* PCI */
95# define RADEON_AGP_1X_MODE 0x01
96# define RADEON_AGP_2X_MODE 0x02
97# define RADEON_AGP_4X_MODE 0x04
98# define RADEON_AGP_FW_MODE 0x10
99# define RADEON_AGP_MODE_MASK 0x17
100# define RADEON_AGPv3_MODE 0x08
101# define RADEON_AGPv3_4X_MODE 0x01
102# define RADEON_AGPv3_8X_MODE 0x02
103#define RADEON_ATTRDR 0x03c1 /* VGA */
104#define RADEON_ATTRDW 0x03c0 /* VGA */
105#define RADEON_ATTRX 0x03c0 /* VGA */
106#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8
107#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc
108
109#define RADEON_BASE_CODE 0x0f0b
110#define RADEON_BIOS_0_SCRATCH 0x0010
111# define RADEON_FP_PANEL_SCALABLE (1 << 16)
112# define RADEON_FP_PANEL_SCALE_EN (1 << 17)
113# define RADEON_FP_CHIP_SCALE_EN (1 << 18)
114# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)
115# define RADEON_DISPLAY_ROT_MASK (3 << 28)
116# define RADEON_DISPLAY_ROT_00 (0 << 28)
117# define RADEON_DISPLAY_ROT_90 (1 << 28)
118# define RADEON_DISPLAY_ROT_180 (2 << 28)
119# define RADEON_DISPLAY_ROT_270 (3 << 28)
120#define RADEON_BIOS_1_SCRATCH 0x0014
121#define RADEON_BIOS_2_SCRATCH 0x0018
122#define RADEON_BIOS_3_SCRATCH 0x001c
123#define RADEON_BIOS_4_SCRATCH 0x0020
124# define RADEON_CRT1_ATTACHED_MASK (3 << 0)
125# define RADEON_CRT1_ATTACHED_MONO (1 << 0)
126# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)
127# define RADEON_LCD1_ATTACHED (1 << 2)
128# define RADEON_DFP1_ATTACHED (1 << 3)
129# define RADEON_TV1_ATTACHED_MASK (3 << 4)
130# define RADEON_TV1_ATTACHED_COMP (1 << 4)
131# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)
132# define RADEON_CRT2_ATTACHED_MASK (3 << 8)
133# define RADEON_CRT2_ATTACHED_MONO (1 << 8)
134# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)
135# define RADEON_DFP2_ATTACHED (1 << 11)
136#define RADEON_BIOS_5_SCRATCH 0x0024
137# define RADEON_LCD1_ON (1 << 0)
138# define RADEON_CRT1_ON (1 << 1)
139# define RADEON_TV1_ON (1 << 2)
140# define RADEON_DFP1_ON (1 << 3)
141# define RADEON_CRT2_ON (1 << 5)
142# define RADEON_CV1_ON (1 << 6)
143# define RADEON_DFP2_ON (1 << 7)
144# define RADEON_LCD1_CRTC_MASK (1 << 8)
145# define RADEON_LCD1_CRTC_SHIFT 8
146# define RADEON_CRT1_CRTC_MASK (1 << 9)
147# define RADEON_CRT1_CRTC_SHIFT 9
148# define RADEON_TV1_CRTC_MASK (1 << 10)
149# define RADEON_TV1_CRTC_SHIFT 10
150# define RADEON_DFP1_CRTC_MASK (1 << 11)
151# define RADEON_DFP1_CRTC_SHIFT 11
152# define RADEON_CRT2_CRTC_MASK (1 << 12)
153# define RADEON_CRT2_CRTC_SHIFT 12
154# define RADEON_CV1_CRTC_MASK (1 << 13)
155# define RADEON_CV1_CRTC_SHIFT 13
156# define RADEON_DFP2_CRTC_MASK (1 << 14)
157# define RADEON_DFP2_CRTC_SHIFT 14
158#define RADEON_BIOS_6_SCRATCH 0x0028
159# define RADEON_ACC_MODE_CHANGE (1 << 2)
160# define RADEON_EXT_DESKTOP_MODE (1 << 3)
161# define RADEON_LCD_DPMS_ON (1 << 20)
162# define RADEON_CRT_DPMS_ON (1 << 21)
163# define RADEON_TV_DPMS_ON (1 << 22)
164# define RADEON_DFP_DPMS_ON (1 << 23)
165# define RADEON_DPMS_MASK (3 << 24)
166# define RADEON_DPMS_ON (0 << 24)
167# define RADEON_DPMS_STANDBY (1 << 24)
168# define RADEON_DPMS_SUSPEND (2 << 24)
169# define RADEON_DPMS_OFF (3 << 24)
170# define RADEON_SCREEN_BLANKING (1 << 26)
171# define RADEON_DRIVER_CRITICAL (1 << 27)
172# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)
173#define RADEON_BIOS_7_SCRATCH 0x002c
174# define RADEON_SYS_HOTKEY (1 << 10)
175# define RADEON_DRV_LOADED (1 << 12)
176#define RADEON_BIOS_ROM 0x0f30 /* PCI */
177#define RADEON_BIST 0x0f0f /* PCI */
178#define RADEON_BRUSH_DATA0 0x1480
179#define RADEON_BRUSH_DATA1 0x1484
180#define RADEON_BRUSH_DATA10 0x14a8
181#define RADEON_BRUSH_DATA11 0x14ac
182#define RADEON_BRUSH_DATA12 0x14b0
183#define RADEON_BRUSH_DATA13 0x14b4
184#define RADEON_BRUSH_DATA14 0x14b8
185#define RADEON_BRUSH_DATA15 0x14bc
186#define RADEON_BRUSH_DATA16 0x14c0
187#define RADEON_BRUSH_DATA17 0x14c4
188#define RADEON_BRUSH_DATA18 0x14c8
189#define RADEON_BRUSH_DATA19 0x14cc
190#define RADEON_BRUSH_DATA2 0x1488
191#define RADEON_BRUSH_DATA20 0x14d0
192#define RADEON_BRUSH_DATA21 0x14d4
193#define RADEON_BRUSH_DATA22 0x14d8
194#define RADEON_BRUSH_DATA23 0x14dc
195#define RADEON_BRUSH_DATA24 0x14e0
196#define RADEON_BRUSH_DATA25 0x14e4
197#define RADEON_BRUSH_DATA26 0x14e8
198#define RADEON_BRUSH_DATA27 0x14ec
199#define RADEON_BRUSH_DATA28 0x14f0
200#define RADEON_BRUSH_DATA29 0x14f4
201#define RADEON_BRUSH_DATA3 0x148c
202#define RADEON_BRUSH_DATA30 0x14f8
203#define RADEON_BRUSH_DATA31 0x14fc
204#define RADEON_BRUSH_DATA32 0x1500
205#define RADEON_BRUSH_DATA33 0x1504
206#define RADEON_BRUSH_DATA34 0x1508
207#define RADEON_BRUSH_DATA35 0x150c
208#define RADEON_BRUSH_DATA36 0x1510
209#define RADEON_BRUSH_DATA37 0x1514
210#define RADEON_BRUSH_DATA38 0x1518
211#define RADEON_BRUSH_DATA39 0x151c
212#define RADEON_BRUSH_DATA4 0x1490
213#define RADEON_BRUSH_DATA40 0x1520
214#define RADEON_BRUSH_DATA41 0x1524
215#define RADEON_BRUSH_DATA42 0x1528
216#define RADEON_BRUSH_DATA43 0x152c
217#define RADEON_BRUSH_DATA44 0x1530
218#define RADEON_BRUSH_DATA45 0x1534
219#define RADEON_BRUSH_DATA46 0x1538
220#define RADEON_BRUSH_DATA47 0x153c
221#define RADEON_BRUSH_DATA48 0x1540
222#define RADEON_BRUSH_DATA49 0x1544
223#define RADEON_BRUSH_DATA5 0x1494
224#define RADEON_BRUSH_DATA50 0x1548
225#define RADEON_BRUSH_DATA51 0x154c
226#define RADEON_BRUSH_DATA52 0x1550
227#define RADEON_BRUSH_DATA53 0x1554
228#define RADEON_BRUSH_DATA54 0x1558
229#define RADEON_BRUSH_DATA55 0x155c
230#define RADEON_BRUSH_DATA56 0x1560
231#define RADEON_BRUSH_DATA57 0x1564
232#define RADEON_BRUSH_DATA58 0x1568
233#define RADEON_BRUSH_DATA59 0x156c
234#define RADEON_BRUSH_DATA6 0x1498
235#define RADEON_BRUSH_DATA60 0x1570
236#define RADEON_BRUSH_DATA61 0x1574
237#define RADEON_BRUSH_DATA62 0x1578
238#define RADEON_BRUSH_DATA63 0x157c
239#define RADEON_BRUSH_DATA7 0x149c
240#define RADEON_BRUSH_DATA8 0x14a0
241#define RADEON_BRUSH_DATA9 0x14a4
242#define RADEON_BRUSH_SCALE 0x1470
243#define RADEON_BRUSH_Y_X 0x1474
244#define RADEON_BUS_CNTL 0x0030
245# define RADEON_BUS_MASTER_DIS (1 << 6)
246# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)
247# define RADEON_BUS_RD_DISCARD_EN (1 << 24)
248# define RADEON_BUS_RD_ABORT_EN (1 << 25)
249# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)
250# define RADEON_BUS_WRT_BURST (1 << 29)
251# define RADEON_BUS_READ_BURST (1 << 30)
252#define RADEON_BUS_CNTL1 0x0034
253# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)
254
255#define RADEON_PCIE_INDEX 0x0030
256#define RADEON_PCIE_DATA 0x0034
257#define R600_PCIE_PORT_INDEX 0x0038
258#define R600_PCIE_PORT_DATA 0x003c
259/* PCIE_LC_LINK_WIDTH_CNTL is PCIE on r1xx-r5xx, PCIE_PORT on r6xx-r7xx */
260#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */
261# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0
262# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7
263# define RADEON_PCIE_LC_LINK_WIDTH_X0 0
264# define RADEON_PCIE_LC_LINK_WIDTH_X1 1
265# define RADEON_PCIE_LC_LINK_WIDTH_X2 2
266# define RADEON_PCIE_LC_LINK_WIDTH_X4 3
267# define RADEON_PCIE_LC_LINK_WIDTH_X8 4
268# define RADEON_PCIE_LC_LINK_WIDTH_X12 5
269# define RADEON_PCIE_LC_LINK_WIDTH_X16 6
270# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4
271# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70
272# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
273# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)
274# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)
275# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)
276# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)
277# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)
278#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c
279#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c
280
281#define RADEON_CACHE_CNTL 0x1724
282#define RADEON_CACHE_LINE 0x0f0c /* PCI */
283#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */
284#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */
285#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */
286# define RADEON_DONT_USE_XTALIN (1 << 4)
287# define RADEON_SCLK_DYN_START_CNTL (1 << 15)
288#define RADEON_CLOCK_CNTL_DATA 0x000c
289#define RADEON_CLOCK_CNTL_INDEX 0x0008
290# define RADEON_PLL_WR_EN (1 << 7)
291# define RADEON_PLL_DIV_SEL (3 << 8)
292# define RADEON_PLL2_DIV_SEL_MASK ~(3 << 8)
293#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */
294# define RADEON_M_SPLL_REF_DIV_MASK 0xff
295# define RADEON_M_SPLL_REF_DIV_SHIFT 0
296# define RADEON_MPLL_FB_DIV_MASK 0xff
297# define RADEON_MPLL_FB_DIV_SHIFT 8
298# define RADEON_SPLL_FB_DIV_MASK 0xff
299# define RADEON_SPLL_FB_DIV_SHIFT 16
300#define RADEON_SPLL_CNTL 0x000c /* PLL */
301# define RADEON_SPLL_SLEEP (1 << 0)
302# define RADEON_SPLL_RESET (1 << 1)
303# define RADEON_SPLL_PCP_MASK 0x7
304# define RADEON_SPLL_PCP_SHIFT 8
305# define RADEON_SPLL_PVG_MASK 0x7
306# define RADEON_SPLL_PVG_SHIFT 11
307# define RADEON_SPLL_PDC_MASK 0x3
308# define RADEON_SPLL_PDC_SHIFT 14
309#define RADEON_CLK_PWRMGT_CNTL 0x0014 /* PLL */
310# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)
311# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)
312# define RADEON_ACTIVE_HILO_LAT_SHIFT 13
313# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)
314# define RADEON_MC_BUSY (1 << 16)
315# define RADEON_DLL_READY (1 << 19)
316# define RADEON_CG_NO1_DEBUG_0 (1 << 24)
317# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)
318# define RADEON_DYN_STOP_MODE_MASK (7 << 21)
319# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)
320# define RADEON_TVCLK_TURNOFF (1 << 31)
321#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */
322# define RADEON_TCL_BYPASS_DISABLE (1 << 20)
323#define RADEON_CLR_CMP_CLR_3D 0x1a24
324#define RADEON_CLR_CMP_CLR_DST 0x15c8
325#define RADEON_CLR_CMP_CLR_SRC 0x15c4
326#define RADEON_CLR_CMP_CNTL 0x15c0
327# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)
328# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)
329# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)
330#define RADEON_CLR_CMP_MASK 0x15cc
331# define RADEON_CLR_CMP_MSK 0xffffffff
332#define RADEON_CLR_CMP_MASK_3D 0x1A28
333#define RADEON_COMMAND 0x0f04 /* PCI */
334#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c
335#define RADEON_CONFIG_APER_0_BASE 0x0100
336#define RADEON_CONFIG_APER_1_BASE 0x0104
337#define RADEON_CONFIG_APER_SIZE 0x0108
338#define RADEON_CONFIG_BONDS 0x00e8
339#define RADEON_CONFIG_CNTL 0x00e0
340# define RADEON_CFG_ATI_REV_A11 (0 << 16)
341# define RADEON_CFG_ATI_REV_A12 (1 << 16)
342# define RADEON_CFG_ATI_REV_A13 (2 << 16)
343# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)
344#define RADEON_CONFIG_MEMSIZE 0x00f8
345#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114
346#define RADEON_CONFIG_REG_1_BASE 0x010c
347#define RADEON_CONFIG_REG_APER_SIZE 0x0110
348#define RADEON_CONFIG_XSTRAP 0x00e4
349#define RADEON_CONSTANT_COLOR_C 0x1d34
350# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff
351# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff
352# define RADEON_CONSTANT_COLOR_ZERO 0x00000000
353#define RADEON_CRC_CMDFIFO_ADDR 0x0740
354#define RADEON_CRC_CMDFIFO_DOUT 0x0744
355#define RADEON_GRPH_BUFFER_CNTL 0x02f0
356# define RADEON_GRPH_START_REQ_MASK (0x7f)
357# define RADEON_GRPH_START_REQ_SHIFT 0
358# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)
359# define RADEON_GRPH_STOP_REQ_SHIFT 8
360# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)
361# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16
362# define RADEON_GRPH_CRITICAL_CNTL (1<<28)
363# define RADEON_GRPH_BUFFER_SIZE (1<<29)
364# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)
365# define RADEON_GRPH_STOP_CNTL (1<<31)
366#define RADEON_GRPH2_BUFFER_CNTL 0x03f0
367# define RADEON_GRPH2_START_REQ_MASK (0x7f)
368# define RADEON_GRPH2_START_REQ_SHIFT 0
369# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)
370# define RADEON_GRPH2_STOP_REQ_SHIFT 8
371# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)
372# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16
373# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)
374# define RADEON_GRPH2_BUFFER_SIZE (1<<29)
375# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)
376# define RADEON_GRPH2_STOP_CNTL (1<<31)
377#define RADEON_CRTC_CRNT_FRAME 0x0214
378#define RADEON_CRTC_EXT_CNTL 0x0054
379# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)
380# define RADEON_VGA_ATI_LINEAR (1 << 3)
381# define RADEON_XCRT_CNT_EN (1 << 6)
382# define RADEON_CRTC_HSYNC_DIS (1 << 8)
383# define RADEON_CRTC_VSYNC_DIS (1 << 9)
384# define RADEON_CRTC_DISPLAY_DIS (1 << 10)
385# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)
386# define RADEON_CRTC_CRT_ON (1 << 15)
387#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055
388# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)
389# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)
390# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)
391#define RADEON_CRTC_GEN_CNTL 0x0050
392# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)
393# define RADEON_CRTC_INTERLACE_EN (1 << 1)
394# define RADEON_CRTC_CSYNC_EN (1 << 4)
395# define RADEON_CRTC_ICON_EN (1 << 15)
396# define RADEON_CRTC_CUR_EN (1 << 16)
397# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)
398# define RADEON_CRTC_EXT_DISP_EN (1 << 24)
399# define RADEON_CRTC_EN (1 << 25)
400# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)
401#define RADEON_CRTC2_GEN_CNTL 0x03f8
402# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)
403# define RADEON_CRTC2_INTERLACE_EN (1 << 1)
404# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)
405# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)
406# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)
407# define RADEON_CRTC2_CRT2_ON (1 << 7)
408# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8
409# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)
410# define RADEON_CRTC2_ICON_EN (1 << 15)
411# define RADEON_CRTC2_CUR_EN (1 << 16)
412# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)
413# define RADEON_CRTC2_DISP_DIS (1 << 23)
414# define RADEON_CRTC2_EN (1 << 25)
415# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)
416# define RADEON_CRTC2_CSYNC_EN (1 << 27)
417# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
418# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
419#define RADEON_CRTC_MORE_CNTL 0x27c
420# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)
421# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)
422# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
423# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)
424#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
425# define RADEON_CRTC_GUI_TRIG_VLINE_START_SHIFT 0
426# define RADEON_CRTC_GUI_TRIG_VLINE_INV (1 << 15)
427# define RADEON_CRTC_GUI_TRIG_VLINE_END_SHIFT 16
428# define RADEON_CRTC_GUI_TRIG_VLINE_STALL (1 << 30)
429#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
430# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
431# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)
432# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3
433# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)
434# define RADEON_CRTC_H_SYNC_WID_SHIFT 16
435# define RADEON_CRTC_H_SYNC_POL (1 << 23)
436#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304
437# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)
438# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)
439# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3
440# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)
441# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16
442# define RADEON_CRTC2_H_SYNC_POL (1 << 23)
443#define RADEON_CRTC_H_TOTAL_DISP 0x0200
444# define RADEON_CRTC_H_TOTAL (0x03ff << 0)
445# define RADEON_CRTC_H_TOTAL_SHIFT 0
446# define RADEON_CRTC_H_DISP (0x01ff << 16)
447# define RADEON_CRTC_H_DISP_SHIFT 16
448#define RADEON_CRTC2_H_TOTAL_DISP 0x0300
449# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)
450# define RADEON_CRTC2_H_TOTAL_SHIFT 0
451# define RADEON_CRTC2_H_DISP (0x01ff << 16)
452# define RADEON_CRTC2_H_DISP_SHIFT 16
453
454#define RADEON_CRTC_OFFSET_RIGHT 0x0220
455#define RADEON_CRTC_OFFSET 0x0224
456#define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)
457#define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)
458
459#define RADEON_CRTC2_OFFSET 0x0324
460#define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)
461#define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)
462#define RADEON_CRTC_OFFSET_CNTL 0x0228
463# define RADEON_CRTC_TILE_LINE_SHIFT 0
464# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4
465#define R300_CRTC_X_Y_MODE_EN_RIGHT(1 << 6)
466#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)
467#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)
468#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)
469#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)
470#define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)
471#define R300_CRTC_X_Y_MODE_EN(1 << 9)
472#define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)
473#define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)
474#define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)
475#define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)
476#define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)
477#define R300_CRTC_MICRO_TILE_EN_RIGHT(1 << 12)
478#define R300_CRTC_MICRO_TILE_EN(1 << 13)
479#define R300_CRTC_MACRO_TILE_EN_RIGHT(1 << 14)
480# define R300_CRTC_MACRO_TILE_EN (1 << 15)
481# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)
482# define RADEON_CRTC_TILE_EN (1 << 15)
483# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
484# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)
485
486#define R300_CRTC_TILE_X0_Y0 0x0350
487#define R300_CRTC2_TILE_X0_Y0 0x0358
488
489#define RADEON_CRTC2_OFFSET_CNTL 0x0328
490# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)
491# define RADEON_CRTC2_TILE_EN (1 << 15)
492#define RADEON_CRTC_PITCH 0x022c
493#define RADEON_CRTC_PITCH__SHIFT 0
494#define RADEON_CRTC_PITCH__RIGHT_SHIFT16
495
496#define RADEON_CRTC2_PITCH 0x032c
497#define RADEON_CRTC_STATUS 0x005c
498# define RADEON_CRTC_VBLANK_SAVE (1 << 1)
499# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)
500#define RADEON_CRTC2_STATUS 0x03fc
501# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)
502# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)
503#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c
504# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)
505# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0
506# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)
507# define RADEON_CRTC_V_SYNC_WID_SHIFT 16
508# define RADEON_CRTC_V_SYNC_POL (1 << 23)
509#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c
510# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)
511# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0
512# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)
513# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16
514# define RADEON_CRTC2_V_SYNC_POL (1 << 23)
515#define RADEON_CRTC_V_TOTAL_DISP 0x0208
516# define RADEON_CRTC_V_TOTAL (0x07ff << 0)
517# define RADEON_CRTC_V_TOTAL_SHIFT 0
518# define RADEON_CRTC_V_DISP (0x07ff << 16)
519# define RADEON_CRTC_V_DISP_SHIFT 16
520#define RADEON_CRTC2_V_TOTAL_DISP 0x0308
521# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)
522# define RADEON_CRTC2_V_TOTAL_SHIFT 0
523# define RADEON_CRTC2_V_DISP (0x07ff << 16)
524# define RADEON_CRTC2_V_DISP_SHIFT 16
525#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210
526# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)
527#define RADEON_CRTC2_CRNT_FRAME 0x0314
528#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318
529#define RADEON_CRTC2_STATUS 0x03fc
530#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310
531#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */
532#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */
533#define RADEON_CUR_CLR0 0x026c
534#define RADEON_CUR_CLR1 0x0270
535#define RADEON_CUR_HORZ_VERT_OFF 0x0268
536#define RADEON_CUR_HORZ_VERT_POSN 0x0264
537#define RADEON_CUR_OFFSET 0x0260
538# define RADEON_CUR_LOCK (1 << 31)
539#define RADEON_CUR2_CLR0 0x036c
540#define RADEON_CUR2_CLR1 0x0370
541#define RADEON_CUR2_HORZ_VERT_OFF 0x0368
542#define RADEON_CUR2_HORZ_VERT_POSN 0x0364
543#define RADEON_CUR2_OFFSET 0x0360
544# define RADEON_CUR2_LOCK (1 << 31)
545
546#define RADEON_DAC_CNTL 0x0058
547# define RADEON_DAC_RANGE_CNTL (3 << 0)
548# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)
549# define RADEON_DAC_RANGE_CNTL_MASK 0x03
550# define RADEON_DAC_BLANKING (1 << 2)
551# define RADEON_DAC_CMP_EN (1 << 3)
552# define RADEON_DAC_CMP_OUTPUT (1 << 7)
553# define RADEON_DAC_8BIT_EN (1 << 8)
554# define RADEON_DAC_TVO_EN (1 << 10)
555# define RADEON_DAC_VGA_ADR_EN (1 << 13)
556# define RADEON_DAC_PDWN (1 << 15)
557# define RADEON_DAC_MASK_ALL (0xff << 24)
558#define RADEON_DAC_CNTL2 0x007c
559# define RADEON_DAC2_TV_CLK_SEL (0 << 1)
560# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)
561# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)
562# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)
563# define RADEON_DAC2_CMP_EN (1 << 7)
564# define RADEON_DAC2_CMP_OUT_R (1 << 8)
565# define RADEON_DAC2_CMP_OUT_G (1 << 9)
566# define RADEON_DAC2_CMP_OUT_B (1 << 10)
567# define RADEON_DAC2_CMP_OUTPUT (1 << 11)
568#define RADEON_DAC_EXT_CNTL 0x0280
569# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)
570# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)
571# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)
572# define RADEON_DAC_FORCE_DATA_EN (1 << 5)
573# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)
574# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)
575# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)
576# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)
577# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)
578# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00
579# define RADEON_DAC_FORCE_DATA_SHIFT 8
580#define RADEON_DAC_MACRO_CNTL 0x0d04
581# define RADEON_DAC_PDWN_R (1 << 16)
582# define RADEON_DAC_PDWN_G (1 << 17)
583# define RADEON_DAC_PDWN_B (1 << 18)
584#define RADEON_TV_DAC_CNTL 0x088c
585# define RADEON_TV_DAC_NBLANK (1 << 0)
586# define RADEON_TV_DAC_NHOLD (1 << 1)
587# define RADEON_TV_DAC_PEDESTAL (1 << 2)
588# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)
589# define RADEON_TV_DAC_CMPOUT (1 << 5)
590# define RADEON_TV_DAC_STD_MASK (3 << 8)
591# define RADEON_TV_DAC_STD_PAL (0 << 8)
592# define RADEON_TV_DAC_STD_NTSC (1 << 8)
593# define RADEON_TV_DAC_STD_PS2 (2 << 8)
594# define RADEON_TV_DAC_STD_RS343 (3 << 8)
595# define RADEON_TV_DAC_BGSLEEP (1 << 6)
596# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)
597# define RADEON_TV_DAC_BGADJ_SHIFT 16
598# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)
599# define RADEON_TV_DAC_DACADJ_SHIFT 20
600# define RADEON_TV_DAC_RDACPD (1 << 24)
601# define RADEON_TV_DAC_GDACPD (1 << 25)
602# define RADEON_TV_DAC_BDACPD (1 << 26)
603# define RADEON_TV_DAC_RDACDET (1 << 29)
604# define RADEON_TV_DAC_GDACDET (1 << 30)
605# define RADEON_TV_DAC_BDACDET (1 << 31)
606# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)
607# define R420_TV_DAC_RDACPD (1 << 25)
608# define R420_TV_DAC_GDACPD (1 << 26)
609# define R420_TV_DAC_BDACPD (1 << 27)
610# define R420_TV_DAC_TVENABLE (1 << 28)
611#define RADEON_DISP_HW_DEBUG 0x0d14
612# define RADEON_CRT2_DISP1_SEL (1 << 5)
613#define RADEON_DISP_OUTPUT_CNTL 0x0d64
614# define RADEON_DISP_DAC_SOURCE_MASK 0x03
615# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c
616# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01
617# define RADEON_DISP_DAC_SOURCE_RMX 0x02
618# define RADEON_DISP_DAC_SOURCE_LTU 0x03
619# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04
620# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)
621# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0
622# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)
623# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)
624# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)
625# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)
626# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)
627# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)
628# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)
629# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */
630# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */
631#define RADEON_DISP_TV_OUT_CNTL 0x0d6c
632# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)
633# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)
634#define RADEON_DAC_CRC_SIG 0x02cc
635#define RADEON_DAC_DATA 0x03c9 /* VGA */
636#define RADEON_DAC_MASK 0x03c6 /* VGA */
637#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */
638#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */
639#define RADEON_DDA_CONFIG 0x02e0
640#define RADEON_DDA_ON_OFF 0x02e4
641#define RADEON_DEFAULT_OFFSET 0x16e0
642#define RADEON_DEFAULT_PITCH 0x16e4
643#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8
644# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)
645# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)
646#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820
647#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824
648#define RADEON_DEVICE_ID 0x0f02 /* PCI */
649#define RADEON_DISP_MISC_CNTL 0x0d00
650# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)
651#define RADEON_DISP_MERGE_CNTL 0x0d60
652# define RADEON_DISP_ALPHA_MODE_MASK 0x03
653# define RADEON_DISP_ALPHA_MODE_KEY 0
654# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
655# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
656# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)
657# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
658# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
659#define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
660#define RADEON_DISP2_MERGE_CNTL 0x0d68
661# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)
662#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
663#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
664#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
665#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c
666#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90
667#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98
668#define RADEON_DP_BRUSH_BKGD_CLR 0x1478
669#define RADEON_DP_BRUSH_FRGD_CLR 0x147c
670#define RADEON_DP_CNTL 0x16c0
671# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)
672# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)
673# define RADEON_DP_DST_TILE_LINEAR (0 << 3)
674# define RADEON_DP_DST_TILE_MACRO (1 << 3)
675# define RADEON_DP_DST_TILE_MICRO (2 << 3)
676# define RADEON_DP_DST_TILE_BOTH (3 << 3)
677#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0
678# define RADEON_DST_Y_MAJOR (1 << 2)
679# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)
680# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)
681#define RADEON_DP_DATATYPE 0x16c4
682# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)
683#define RADEON_DP_GUI_MASTER_CNTL 0x146c
684# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
685# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
686# define RADEON_GMC_SRC_CLIPPING (1 << 2)
687# define RADEON_GMC_DST_CLIPPING (1 << 3)
688# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)
689# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)
690# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)
691# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)
692# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)
693# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)
694# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)
695# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)
696# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)
697# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)
698# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)
699# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
700# define RADEON_GMC_BRUSH_NONE (15 << 4)
701# define RADEON_GMC_DST_8BPP_CI (2 << 8)
702# define RADEON_GMC_DST_15BPP (3 << 8)
703# define RADEON_GMC_DST_16BPP (4 << 8)
704# define RADEON_GMC_DST_24BPP (5 << 8)
705# define RADEON_GMC_DST_32BPP (6 << 8)
706# define RADEON_GMC_DST_8BPP_RGB (7 << 8)
707# define RADEON_GMC_DST_Y8 (8 << 8)
708# define RADEON_GMC_DST_RGB8 (9 << 8)
709# define RADEON_GMC_DST_VYUY (11 << 8)
710# define RADEON_GMC_DST_YVYU (12 << 8)
711# define RADEON_GMC_DST_AYUV444 (14 << 8)
712# define RADEON_GMC_DST_ARGB4444 (15 << 8)
713# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)
714# define RADEON_GMC_DST_DATATYPE_SHIFT 8
715# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)
716# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)
717# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)
718# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
719# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)
720# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)
721# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)
722# define RADEON_GMC_CONVERSION_TEMP (1 << 15)
723# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)
724# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)
725# define RADEON_GMC_ROP3_MASK (0xff << 16)
726# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)
727# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
728# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
729# define RADEON_GMC_3D_FCN_EN (1 << 27)
730# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
731# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)
732# define RADEON_GMC_WR_MSK_DIS (1 << 30)
733# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)
734# define RADEON_ROP3_ZERO 0x00000000
735# define RADEON_ROP3_DSa 0x00880000
736# define RADEON_ROP3_SDna 0x00440000
737# define RADEON_ROP3_S 0x00cc0000
738# define RADEON_ROP3_DSna 0x00220000
739# define RADEON_ROP3_D 0x00aa0000
740# define RADEON_ROP3_DSx 0x00660000
741# define RADEON_ROP3_DSo 0x00ee0000
742# define RADEON_ROP3_DSon 0x00110000
743# define RADEON_ROP3_DSxn 0x00990000
744# define RADEON_ROP3_Dn 0x00550000
745# define RADEON_ROP3_SDno 0x00dd0000
746# define RADEON_ROP3_Sn 0x00330000
747# define RADEON_ROP3_DSno 0x00bb0000
748# define RADEON_ROP3_DSan 0x00770000
749# define RADEON_ROP3_ONE 0x00ff0000
750# define RADEON_ROP3_DPa 0x00a00000
751# define RADEON_ROP3_PDna 0x00500000
752# define RADEON_ROP3_P 0x00f00000
753# define RADEON_ROP3_DPna 0x000a0000
754# define RADEON_ROP3_D 0x00aa0000
755# define RADEON_ROP3_DPx 0x005a0000
756# define RADEON_ROP3_DPo 0x00fa0000
757# define RADEON_ROP3_DPon 0x00050000
758# define RADEON_ROP3_PDxn 0x00a50000
759# define RADEON_ROP3_PDno 0x00f50000
760# define RADEON_ROP3_Pn 0x000f0000
761# define RADEON_ROP3_DPno 0x00af0000
762# define RADEON_ROP3_DPan 0x005f0000
763#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84
764#define RADEON_DP_MIX 0x16c8
765#define RADEON_DP_SRC_BKGD_CLR 0x15dc
766#define RADEON_DP_SRC_FRGD_CLR 0x15d8
767#define RADEON_DP_WRITE_MASK 0x16cc
768#define RADEON_DST_BRES_DEC 0x1630
769#define RADEON_DST_BRES_ERR 0x1628
770#define RADEON_DST_BRES_INC 0x162c
771#define RADEON_DST_BRES_LNTH 0x1634
772#define RADEON_DST_BRES_LNTH_SUB 0x1638
773#define RADEON_DST_HEIGHT 0x1410
774#define RADEON_DST_HEIGHT_WIDTH 0x143c
775#define RADEON_DST_HEIGHT_WIDTH_8 0x158c
776#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4
777#define RADEON_DST_HEIGHT_Y 0x15a0
778#define RADEON_DST_LINE_START 0x1600
779#define RADEON_DST_LINE_END 0x1604
780#define RADEON_DST_LINE_PATCOUNT 0x1608
781# define RADEON_BRES_CNTL_SHIFT 8
782#define RADEON_DST_OFFSET 0x1404
783#define RADEON_DST_PITCH 0x1408
784#define RADEON_DST_PITCH_OFFSET 0x142c
785#define RADEON_DST_PITCH_OFFSET_C 0x1c80
786# define RADEON_PITCH_SHIFT 21
787# define RADEON_DST_TILE_LINEAR (0 << 30)
788# define RADEON_DST_TILE_MACRO (1 << 30)
789# define RADEON_DST_TILE_MICRO (2 << 30)
790# define RADEON_DST_TILE_BOTH (3 << 30)
791#define RADEON_DST_WIDTH 0x140c
792#define RADEON_DST_WIDTH_HEIGHT 0x1598
793#define RADEON_DST_WIDTH_X 0x1588
794#define RADEON_DST_WIDTH_X_INCY 0x159c
795#define RADEON_DST_X 0x141c
796#define RADEON_DST_X_SUB 0x15a4
797#define RADEON_DST_X_Y 0x1594
798#define RADEON_DST_Y 0x1420
799#define RADEON_DST_Y_SUB 0x15a8
800#define RADEON_DST_Y_X 0x1438
801
802#define RADEON_FCP_CNTL 0x0910
803# define RADEON_FCP0_SRC_PCICLK 0
804# define RADEON_FCP0_SRC_PCLK 1
805# define RADEON_FCP0_SRC_PCLKb 2
806# define RADEON_FCP0_SRC_HREF 3
807# define RADEON_FCP0_SRC_GND 4
808# define RADEON_FCP0_SRC_HREFb 5
809#define RADEON_FLUSH_1 0x1704
810#define RADEON_FLUSH_2 0x1708
811#define RADEON_FLUSH_3 0x170c
812#define RADEON_FLUSH_4 0x1710
813#define RADEON_FLUSH_5 0x1714
814#define RADEON_FLUSH_6 0x1718
815#define RADEON_FLUSH_7 0x171c
816#define RADEON_FOG_3D_TABLE_START 0x1810
817#define RADEON_FOG_3D_TABLE_END 0x1814
818#define RADEON_FOG_3D_TABLE_DENSITY 0x181c
819#define RADEON_FOG_TABLE_INDEX 0x1a14
820#define RADEON_FOG_TABLE_DATA 0x1a18
821#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250
822#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254
823# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff
824# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000
825# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff
826# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000
827# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8
828# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000
829# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff
830# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000
831# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000
832# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010
833# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000
834# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010
835# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003
836# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010
837# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000
838# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010
839#define RADEON_FP_GEN_CNTL 0x0284
840# define RADEON_FP_FPON (1 << 0)
841# define RADEON_FP_BLANK_EN (1 << 1)
842# define RADEON_FP_TMDS_EN (1 << 2)
843# define RADEON_FP_PANEL_FORMAT (1 << 3)
844# define RADEON_FP_EN_TMDS (1 << 7)
845# define RADEON_FP_DETECT_SENSE (1 << 8)
846# define R200_FP_SOURCE_SEL_MASK (3 << 10)
847# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)
848# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)
849# define R200_FP_SOURCE_SEL_RMX (2 << 10)
850# define R200_FP_SOURCE_SEL_TRANS (3 << 10)
851# define RADEON_FP_SEL_CRTC1 (0 << 13)
852# define RADEON_FP_SEL_CRTC2 (1 << 13)
853# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)
854# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)
855# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)
856# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)
857# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)
858# define RADEON_FP_DFP_SYNC_SEL (1 << 21)
859# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)
860# define RADEON_FP_CRT_SYNC_SEL (1 << 23)
861# define RADEON_FP_USE_SHADOW_EN (1 << 24)
862# define RADEON_FP_CRT_SYNC_ALT (1 << 26)
863#define RADEON_FP2_GEN_CNTL 0x0288
864# define RADEON_FP2_BLANK_EN (1 << 1)
865# define RADEON_FP2_ON (1 << 2)
866# define RADEON_FP2_PANEL_FORMAT (1 << 3)
867# define RADEON_FP2_DETECT_SENSE (1 << 8)
868# define R200_FP2_SOURCE_SEL_MASK (3 << 10)
869# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)
870# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)
871# define R200_FP2_SOURCE_SEL_RMX (2 << 10)
872# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)
873# define RADEON_FP2_SRC_SEL_MASK (3 << 13)
874# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)
875# define RADEON_FP2_FP_POL (1 << 16)
876# define RADEON_FP2_LP_POL (1 << 17)
877# define RADEON_FP2_SCK_POL (1 << 18)
878# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)
879# define RADEON_FP2_PAD_FLOP_EN (1 << 22)
880# define RADEON_FP2_CRC_EN (1 << 23)
881# define RADEON_FP2_CRC_READ_EN (1 << 24)
882# define RADEON_FP2_DVO_EN (1 << 25)
883# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)
884# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)
885# define R200_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)
886# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)
887#define RADEON_FP_H_SYNC_STRT_WID 0x02c4
888#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4
889#define RADEON_FP_HORZ_STRETCH 0x028c
890#define RADEON_FP_HORZ2_STRETCH 0x038c
891# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff
892# define RADEON_HORZ_STRETCH_RATIO_MAX 4096
893# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)
894# define RADEON_HORZ_PANEL_SHIFT 16
895# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)
896# define RADEON_HORZ_STRETCH_BLEND (1 << 26)
897# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)
898# define RADEON_HORZ_AUTO_RATIO (1 << 27)
899# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)
900# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)
901#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278
902#define RADEON_FP_V_SYNC_STRT_WID 0x02c8
903#define RADEON_FP_VERT_STRETCH 0x0290
904#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8
905#define RADEON_FP_VERT2_STRETCH 0x0390
906# define RADEON_VERT_PANEL_SIZE (0xfff << 12)
907# define RADEON_VERT_PANEL_SHIFT 12
908# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff
909# define RADEON_VERT_STRETCH_RATIO_SHIFT 0
910# define RADEON_VERT_STRETCH_RATIO_MAX 4096
911# define RADEON_VERT_STRETCH_ENABLE (1 << 25)
912# define RADEON_VERT_STRETCH_LINEREP (0 << 26)
913# define RADEON_VERT_STRETCH_BLEND (1 << 26)
914# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)
915#define RADEON_VERT_AUTO_RATIO_INC (1 << 31)
916# define RADEON_VERT_STRETCH_RESERVED 0x71000000
917#define RS400_FP_2ND_GEN_CNTL 0x0384
918# define RS400_FP_2ND_ON (1 << 0)
919# define RS400_FP_2ND_BLANK_EN (1 << 1)
920# define RS400_TMDS_2ND_EN (1 << 2)
921# define RS400_PANEL_FORMAT_2ND (1 << 3)
922# define RS400_FP_2ND_EN_TMDS (1 << 7)
923# define RS400_FP_2ND_DETECT_SENSE (1 << 8)
924# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)
925# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)
926# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)
927# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)
928# define RS400_FP_2ND_DETECT_EN (1 << 12)
929# define RS400_HPD_2ND_SEL (1 << 13)
930#define RS400_FP2_2_GEN_CNTL 0x0388
931# define RS400_FP2_2_BLANK_EN (1 << 1)
932# define RS400_FP2_2_ON (1 << 2)
933# define RS400_FP2_2_PANEL_FORMAT (1 << 3)
934# define RS400_FP2_2_DETECT_SENSE (1 << 8)
935# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)
936# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)
937# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)
938# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)
939# define RS400_FP2_2_DVO2_EN (1 << 25)
940#define RS400_TMDS2_CNTL 0x0394
941#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a4
942# define RS400_TMDS2_PLLEN (1 << 0)
943# define RS400_TMDS2_PLLRST (1 << 1)
944
945#define RADEON_GEN_INT_CNTL 0x0040
946#define RADEON_GEN_INT_STATUS 0x0044
947# define RADEON_VSYNC_INT_AK (1 << 2)
948# define RADEON_VSYNC_INT (1 << 2)
949# define RADEON_VSYNC2_INT_AK (1 << 6)
950# define RADEON_VSYNC2_INT (1 << 6)
951#define RADEON_GENENB 0x03c3 /* VGA */
952#define RADEON_GENFC_RD 0x03ca /* VGA */
953#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */
954#define RADEON_GENMO_RD 0x03cc /* VGA */
955#define RADEON_GENMO_WT 0x03c2 /* VGA */
956#define RADEON_GENS0 0x03c2 /* VGA */
957#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
958#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */
959#define RADEON_GPIO_MONIDB 0x006c
960#define RADEON_GPIO_CRT2_DDC 0x006c
961#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */
962#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */
963# define RADEON_GPIO_A_0 (1 << 0)
964# define RADEON_GPIO_A_1 (1 << 1)
965# define RADEON_GPIO_Y_0 (1 << 8)
966# define RADEON_GPIO_Y_1 (1 << 9)
967# define RADEON_GPIO_Y_SHIFT_0 8
968# define RADEON_GPIO_Y_SHIFT_1 9
969# define RADEON_GPIO_EN_0 (1 << 16)
970# define RADEON_GPIO_EN_1 (1 << 17)
971# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/
972# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/
973#define RADEON_GRPH8_DATA 0x03cf /* VGA */
974#define RADEON_GRPH8_IDX 0x03ce /* VGA */
975#define RADEON_GUI_SCRATCH_REG0 0x15e0
976#define RADEON_GUI_SCRATCH_REG1 0x15e4
977#define RADEON_GUI_SCRATCH_REG2 0x15e8
978#define RADEON_GUI_SCRATCH_REG3 0x15ec
979#define RADEON_GUI_SCRATCH_REG4 0x15f0
980#define RADEON_GUI_SCRATCH_REG5 0x15f4
981
982#define RADEON_HEADER 0x0f0e /* PCI */
983#define RADEON_HOST_DATA0 0x17c0
984#define RADEON_HOST_DATA1 0x17c4
985#define RADEON_HOST_DATA2 0x17c8
986#define RADEON_HOST_DATA3 0x17cc
987#define RADEON_HOST_DATA4 0x17d0
988#define RADEON_HOST_DATA5 0x17d4
989#define RADEON_HOST_DATA6 0x17d8
990#define RADEON_HOST_DATA7 0x17dc
991#define RADEON_HOST_DATA_LAST 0x17e0
992#define RADEON_HOST_PATH_CNTL 0x0130
993# define RADEON_HDP_SOFT_RESET (1 << 26)
994# define RADEON_HDP_APER_CNTL (1 << 23)
995#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */
996# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)
997#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */
998
999 /* Multimedia I2C bus */
1000#define RADEON_I2C_CNTL_0 0x0090
1001#define RADEON_I2C_DONE (1 << 0)
1002#define RADEON_I2C_NACK (1 << 1)
1003#define RADEON_I2C_HALT (1 << 2)
1004#define RADEON_I2C_SOFT_RST (1 << 5)
1005#define RADEON_I2C_DRIVE_EN (1 << 6)
1006#define RADEON_I2C_DRIVE_SEL (1 << 7)
1007#define RADEON_I2C_START (1 << 8)
1008#define RADEON_I2C_STOP (1 << 9)
1009#define RADEON_I2C_RECEIVE (1 << 10)
1010#define RADEON_I2C_ABORT (1 << 11)
1011#define RADEON_I2C_GO (1 << 12)
1012#define RADEON_I2C_CNTL_1 0x0094
1013#define RADEON_I2C_SEL (1 << 16)
1014#define RADEON_I2C_EN (1 << 17)
1015#define RADEON_I2C_DATA 0x0098
1016
1017#define RADEON_DVI_I2C_CNTL_0 0x02e0
1018# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
1019# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */
1020# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */
1021# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */
1022#define RADEON_DVI_I2C_CNTL_1 0x02e4
1023#define RADEON_DVI_I2C_DATA 0x02e8
1024
1025#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */
1026#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */
1027#define RADEON_IO_BASE 0x0f14 /* PCI */
1028
1029#define RADEON_LATENCY 0x0f0d /* PCI */
1030#define RADEON_LEAD_BRES_DEC 0x1608
1031#define RADEON_LEAD_BRES_LNTH 0x161c
1032#define RADEON_LEAD_BRES_LNTH_SUB 0x1624
1033#define RADEON_LVDS_GEN_CNTL 0x02d0
1034# define RADEON_LVDS_ON (1 << 0)
1035# define RADEON_LVDS_DISPLAY_DIS (1 << 1)
1036# define RADEON_LVDS_PANEL_TYPE (1 << 2)
1037# define RADEON_LVDS_PANEL_FORMAT (1 << 3)
1038# define RADEON_LVDS_RST_FM (1 << 6)
1039# define RADEON_LVDS_EN (1 << 7)
1040# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 8
1041# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)
1042# define RADEON_LVDS_BL_MOD_EN (1 << 16)
1043# define RADEON_LVDS_DIGON (1 << 18)
1044# define RADEON_LVDS_BLON (1 << 19)
1045# define RADEON_LVDS_SEL_CRTC2 (1 << 23)
1046#define RADEON_LVDS_PLL_CNTL 0x02d4
1047# define RADEON_HSYNC_DELAY_SHIFT 28
1048# define RADEON_HSYNC_DELAY_MASK (0xf << 28)
1049# define RADEON_LVDS_PLL_EN (1 << 16)
1050# define RADEON_LVDS_PLL_RESET (1 << 17)
1051# define R300_LVDS_SRC_SEL_MASK (3 << 18)
1052# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)
1053# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)
1054# define R300_LVDS_SRC_SEL_RMX (2 << 18)
1055
1056#define RADEON_MAX_LATENCY 0x0f3f /* PCI */
1057#define RADEON_MC_AGP_LOCATION 0x014c
1058#define RADEON_MC_FB_LOCATION 0x0148
1059#define RADEON_DISPLAY_BASE_ADDR 0x23c
1060#define RADEON_DISPLAY2_BASE_ADDR 0x33c
1061#define RADEON_OV0_BASE_ADDR 0x43c
1062#define RADEON_NB_TOM 0x15c
1063#define R300_MC_INIT_MISC_LAT_TIMER 0x180
1064# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
1065# define R300_MC_DISP0R_INIT_LAT_MASK 0xf
1066# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
1067# define R300_MC_DISP1R_INIT_LAT_MASK 0xf
1068#define RADEON_MCLK_CNTL 0x0012 /* PLL */
1069# define RADEON_FORCEON_MCLKA (1 << 16)
1070# define RADEON_FORCEON_MCLKB (1 << 17)
1071# define RADEON_FORCEON_YCLKA (1 << 18)
1072# define RADEON_FORCEON_YCLKB (1 << 19)
1073# define RADEON_FORCEON_MC (1 << 20)
1074# define RADEON_FORCEON_AIC (1 << 21)
1075# define R300_DISABLE_MC_MCLKA (1 << 21)
1076# define R300_DISABLE_MC_MCLKB (1 << 21)
1077#define RADEON_MCLK_MISC 0x001f /* PLL */
1078# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)
1079# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)
1080# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)
1081# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)
1082#define RADEON_LCD_GPIO_MASK 0x01a0
1083#define RADEON_GPIOPAD_EN 0x01a0
1084#define RADEON_LCD_GPIO_Y_REG 0x01a4
1085#define RADEON_MDGPIO_A_REG 0x01ac
1086#define RADEON_MDGPIO_EN_REG 0x01b0
1087#define RADEON_MDGPIO_MASK 0x0198
1088#define RADEON_GPIOPAD_MASK 0x0198
1089#define RADEON_GPIOPAD_A 0x019c
1090#define RADEON_MDGPIO_Y_REG 0x01b4
1091#define RADEON_MEM_ADDR_CONFIG 0x0148
1092#define RADEON_MEM_BASE 0x0f10 /* PCI */
1093#define RADEON_MEM_CNTL 0x0140
1094# define RADEON_MEM_NUM_CHANNELS_MASK 0x01
1095# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)
1096# define RV100_HALF_MODE (1 << 3)
1097# define R300_MEM_NUM_CHANNELS_MASK 0x03
1098# define R300_MEM_USE_CD_CH_ONLY (1 << 2)
1099#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */
1100#define RADEON_MEM_INIT_LAT_TIMER 0x0154
1101#define RADEON_MEM_INTF_CNTL 0x014c
1102#define RADEON_MEM_SDRAM_MODE_REG 0x0158
1103# define RADEON_SDRAM_MODE_MASK 0xffff0000
1104# define RADEON_B3MEM_RESET_MASK 0x6fffffff
1105# define RADEON_MEM_CFG_TYPE_DDR (1 << 30)
1106#define RADEON_MEM_STR_CNTL 0x0150
1107# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)
1108# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)
1109# define R300_MEM_PWRUP_COMPL_C (1 << 2)
1110# define R300_MEM_PWRUP_COMPL_D (1 << 3)
1111# define RADEON_MEM_PWRUP_COMPLETE 0x03
1112# define R300_MEM_PWRUP_COMPLETE 0x0f
1113#define RADEON_MC_STATUS 0x0150
1114# define RADEON_MC_IDLE (1 << 2)
1115# define R300_MC_IDLE (1 << 4)
1116#define RADEON_MEM_VGA_RP_SEL 0x003c
1117#define RADEON_MEM_VGA_WP_SEL 0x0038
1118#define RADEON_MIN_GRANT 0x0f3e /* PCI */
1119#define RADEON_MM_DATA 0x0004
1120#define RADEON_MM_INDEX 0x0000
1121#define RADEON_MPLL_CNTL 0x000e /* PLL */
1122#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */
1123#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */
1124#define RADEON_SEPROM_CNTL1 0x01c0
1125# define RADEON_SCK_PRESCALE_SHIFT 24
1126# define RADEON_SCK_PRESCALE_MASK (0xff << 24)
1127#define R300_MC_IND_INDEX 0x01f8
1128# define R300_MC_IND_ADDR_MASK 0x3f
1129# define R300_MC_IND_WR_EN (1 << 8)
1130#define R300_MC_IND_DATA 0x01fc
1131#define R300_MC_READ_CNTL_AB 0x017c
1132# define R300_MEM_RBS_POSITION_A_MASK 0x03
1133#define R300_MC_READ_CNTL_CD_mcind 0x24
1134# define R300_MEM_RBS_POSITION_C_MASK 0x03
1135
1136#define RADEON_N_VIF_COUNT 0x0248
1137
1138#define RADEON_OV0_AUTO_FLIP_CNTL 0x0470
1139# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007
1140# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008
1141# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010
1142# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020
1143# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040
1144# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300
1145# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000
1146# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000
1147# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000
1148# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000
1149
1150#define RADEON_OV0_COLOUR_CNTL 0x04E0
1151#define RADEON_OV0_DEINTERLACE_PATTERN 0x0474
1152#define RADEON_OV0_EXCLUSIVE_HORZ 0x0408
1153# define RADEON_EXCL_HORZ_START_MASK 0x000000ff
1154# define RADEON_EXCL_HORZ_END_MASK 0x0000ff00
1155# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000
1156# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x80000000
1157#define RADEON_OV0_EXCLUSIVE_VERT 0x040C
1158# define RADEON_EXCL_VERT_START_MASK 0x000003ff
1159# define RADEON_EXCL_VERT_END_MASK 0x03ff0000
1160#define RADEON_OV0_FILTER_CNTL 0x04A0
1161# define RADEON_FILTER_PROGRAMMABLE_COEF 0x0
1162# define RADEON_FILTER_HC_COEF_HORZ_Y 0x1
1163# define RADEON_FILTER_HC_COEF_HORZ_UV 0x2
1164# define RADEON_FILTER_HC_COEF_VERT_Y 0x4
1165# define RADEON_FILTER_HC_COEF_VERT_UV 0x8
1166# define RADEON_FILTER_HARDCODED_COEF 0xf
1167# define RADEON_FILTER_COEF_MASK 0xf
1168
1169#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B0
1170#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B4
1171#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B8
1172#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC
1173#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C0
1174#define RADEON_OV0_FLAG_CNTL 0x04DC
1175#define RADEON_OV0_GAMMA_000_00F 0x0d40
1176#define RADEON_OV0_GAMMA_010_01F 0x0d44
1177#define RADEON_OV0_GAMMA_020_03F 0x0d48
1178#define RADEON_OV0_GAMMA_040_07F 0x0d4c
1179#define RADEON_OV0_GAMMA_080_0BF 0x0e00
1180#define RADEON_OV0_GAMMA_0C0_0FF 0x0e04
1181#define RADEON_OV0_GAMMA_100_13F 0x0e08
1182#define RADEON_OV0_GAMMA_140_17F 0x0e0c
1183#define RADEON_OV0_GAMMA_180_1BF 0x0e10
1184#define RADEON_OV0_GAMMA_1C0_1FF 0x0e14
1185#define RADEON_OV0_GAMMA_200_23F 0x0e18
1186#define RADEON_OV0_GAMMA_240_27F 0x0e1c
1187#define RADEON_OV0_GAMMA_280_2BF 0x0e20
1188#define RADEON_OV0_GAMMA_2C0_2FF 0x0e24
1189#define RADEON_OV0_GAMMA_300_33F 0x0e28
1190#define RADEON_OV0_GAMMA_340_37F 0x0e2c
1191#define RADEON_OV0_GAMMA_380_3BF 0x0d50
1192#define RADEON_OV0_GAMMA_3C0_3FF 0x0d54
1193#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC
1194#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F0
1195#define RADEON_OV0_H_INC 0x0480
1196#define RADEON_OV0_KEY_CNTL 0x04F4
1197# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L
1198# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L
1199# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L
1200# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L
1201# define RADEON_VIDEO_KEY_FN_NE 0x00000003L
1202# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L
1203# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L
1204# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L
1205# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L
1206# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L
1207# define RADEON_CMP_MIX_MASK 0x00000100L
1208# define RADEON_CMP_MIX_OR 0x00000000L
1209# define RADEON_CMP_MIX_AND 0x00000100L
1210#define RADEON_OV0_LIN_TRANS_A 0x0d20
1211#define RADEON_OV0_LIN_TRANS_B 0x0d24
1212#define RADEON_OV0_LIN_TRANS_C 0x0d28
1213#define RADEON_OV0_LIN_TRANS_D 0x0d2c
1214#define RADEON_OV0_LIN_TRANS_E 0x0d30
1215#define RADEON_OV0_LIN_TRANS_F 0x0d34
1216#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x0430
1217# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL
1218# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L
1219#define RADEON_OV0_P1_H_ACCUM_INIT 0x0488
1220#define RADEON_OV0_P1_V_ACCUM_INIT 0x0428
1221# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L
1222# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L
1223#define RADEON_OV0_P1_X_START_END 0x0494
1224#define RADEON_OV0_P2_X_START_END 0x0498
1225#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x0434
1226# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL
1227# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L
1228#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C
1229#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C
1230#define RADEON_OV0_P3_X_START_END 0x049C
1231#define RADEON_OV0_REG_LOAD_CNTL 0x0410
1232# define RADEON_REG_LD_CTL_LOCK 0x00000001L
1233# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L
1234# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L
1235# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L
1236# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L
1237#define RADEON_OV0_SCALE_CNTL 0x0420
1238# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L
1239# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L
1240# define RADEON_SCALER_SIGNED_UV 0x00000010L
1241# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L
1242# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L
1243# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L
1244# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L
1245# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L
1246# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L
1247# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L
1248# define RADEON_SCALER_SOURCE_15BPP 0x00000300L
1249# define RADEON_SCALER_SOURCE_16BPP 0x00000400L
1250# define RADEON_SCALER_SOURCE_32BPP 0x00000600L
1251# define RADEON_SCALER_SOURCE_YUV9 0x00000900L
1252# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L
1253# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L
1254# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L
1255# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L
1256# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L
1257# define RADEON_SCALER_CRTC_SEL 0x00004000L
1258# define RADEON_SCALER_SMART_SWITCH 0x00008000L
1259# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L
1260# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L
1261# define RADEON_SCALER_DIS_LIMIT 0x08000000L
1262# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L
1263# define RADEON_SCALER_INT_EMU 0x20000000L
1264# define RADEON_SCALER_ENABLE 0x40000000L
1265# define RADEON_SCALER_SOFT_RESET 0x80000000L
1266#define RADEON_OV0_STEP_BY 0x0484
1267#define RADEON_OV0_TEST 0x04F8
1268#define RADEON_OV0_V_INC 0x0424
1269#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x0460
1270#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x0464
1271#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x0440
1272# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L
1273# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L
1274# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L
1275# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L
1276#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x0444
1277# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L
1278# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L
1279# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L
1280# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L
1281#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x0448
1282# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L
1283# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L
1284# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L
1285# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L
1286#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C
1287#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x0450
1288#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x0454
1289#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E8
1290#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E4
1291#define RADEON_OV0_Y_X_START 0x0400
1292#define RADEON_OV0_Y_X_END 0x0404
1293#define RADEON_OV1_Y_X_START 0x0600
1294#define RADEON_OV1_Y_X_END 0x0604
1295#define RADEON_OVR_CLR 0x0230
1296#define RADEON_OVR_WID_LEFT_RIGHT 0x0234
1297#define RADEON_OVR_WID_TOP_BOTTOM 0x0238
1298
1299/* first capture unit */
1300
1301#define RADEON_CAP0_BUF0_OFFSET 0x0920
1302#define RADEON_CAP0_BUF1_OFFSET 0x0924
1303#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x0928
1304#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C
1305
1306#define RADEON_CAP0_BUF_PITCH 0x0930
1307#define RADEON_CAP0_V_WINDOW 0x0934
1308#define RADEON_CAP0_H_WINDOW 0x0938
1309#define RADEON_CAP0_VBI0_OFFSET 0x093C
1310#define RADEON_CAP0_VBI1_OFFSET 0x0940
1311#define RADEON_CAP0_VBI_V_WINDOW 0x0944
1312#define RADEON_CAP0_VBI_H_WINDOW 0x0948
1313#define RADEON_CAP0_PORT_MODE_CNTL 0x094C
1314#define RADEON_CAP0_TRIG_CNTL 0x0950
1315#define RADEON_CAP0_DEBUG 0x0954
1316#define RADEON_CAP0_CONFIG 0x0958
1317# define RADEON_CAP0_CONFIG_CONTINUOS 0x00000001
1318# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x00000002
1319# define RADEON_CAP0_CONFIG_START_BUF_GET 0x00000004
1320# define RADEON_CAP0_CONFIG_START_BUF_SET 0x00000008
1321# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x00000010
1322# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020
1323# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040
1324# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080
1325# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100
1326# define RADEON_CAP0_CONFIG_MIRROR_EN 0x00000200
1327# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400
1328# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800
1329# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x00001000
1330# define RADEON_CAP0_CONFIG_VBI_EN 0x00002000
1331# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000
1332# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000
1333# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x00010000
1334# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000
1335# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000
1336# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000
1337# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000
1338# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x00200000
1339# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x00400000
1340# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000
1341# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x00800000
1342# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x01000000
1343# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x01800000
1344# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000
1345# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x04000000
1346# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000
1347# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000
1348# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x40000000
1349# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x80000000
1350#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C
1351#define RADEON_CAP0_ANC_EVEN_OFFSET 0x0960
1352#define RADEON_CAP0_ANC_H_WINDOW 0x0964
1353#define RADEON_CAP0_VIDEO_SYNC_TEST 0x0968
1354#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C
1355#define RADEON_CAP0_BUF_STATUS 0x0970
1356/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */
1357/* #define RADEON_CAP0_XSHARPNESS 0x097C */
1358#define RADEON_CAP0_VBI2_OFFSET 0x0980
1359#define RADEON_CAP0_VBI3_OFFSET 0x0984
1360#define RADEON_CAP0_ANC2_OFFSET 0x0988
1361#define RADEON_CAP0_ANC3_OFFSET 0x098C
1362#define RADEON_VID_BUFFER_CONTROL 0x0900
1363
1364/* second capture unit */
1365
1366#define RADEON_CAP1_BUF0_OFFSET 0x0990
1367#define RADEON_CAP1_BUF1_OFFSET 0x0994
1368#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x0998
1369#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C
1370
1371#define RADEON_CAP1_BUF_PITCH 0x09A0
1372#define RADEON_CAP1_V_WINDOW 0x09A4
1373#define RADEON_CAP1_H_WINDOW 0x09A8
1374#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC
1375#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B0
1376#define RADEON_CAP1_VBI_V_WINDOW 0x09B4
1377#define RADEON_CAP1_VBI_H_WINDOW 0x09B8
1378#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC
1379#define RADEON_CAP1_TRIG_CNTL 0x09C0
1380#define RADEON_CAP1_DEBUG 0x09C4
1381#define RADEON_CAP1_CONFIG 0x09C8
1382#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC
1383#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D0
1384#define RADEON_CAP1_ANC_H_WINDOW 0x09D4
1385#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D8
1386#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC
1387#define RADEON_CAP1_BUF_STATUS 0x09E0
1388#define RADEON_CAP1_DWNSC_XRATIO 0x09E8
1389#define RADEON_CAP1_XSHARPNESS 0x09EC
1390
1391/* misc multimedia registers */
1392
1393#define RADEON_IDCT_RUNS 0x1F80
1394#define RADEON_IDCT_LEVELS 0x1F84
1395#define RADEON_IDCT_CONTROL 0x1FBC
1396#define RADEON_IDCT_AUTH_CONTROL 0x1F88
1397#define RADEON_IDCT_AUTH 0x1F8C
1398
1399#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */
1400# define RADEON_P2PLL_RESET (1 << 0)
1401# define RADEON_P2PLL_SLEEP (1 << 1)
1402# define RADEON_P2PLL_PVG_MASK (7 << 11)
1403# define RADEON_P2PLL_PVG_SHIFT 11
1404# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)
1405# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1406# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1407#define RADEON_P2PLL_DIV_0 0x002c
1408# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff
1409# define RADEON_P2PLL_POST0_DIV_MASK 0x00070000
1410#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */
1411# define RADEON_P2PLL_REF_DIV_MASK 0x03ff
1412# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1413# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1414# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)
1415# define R300_PPLL_REF_DIV_ACC_SHIFT 18
1416#define RADEON_PALETTE_DATA 0x00b4
1417#define RADEON_PALETTE_30_DATA 0x00b8
1418#define RADEON_PALETTE_INDEX 0x00b0
1419#define RADEON_PCI_GART_PAGE 0x017c
1420#define RADEON_PIXCLKS_CNTL 0x002d
1421# define RADEON_PIX2CLK_SRC_SEL_MASK 0x03
1422# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x00
1423# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x01
1424# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x02
1425# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x03
1426# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)
1427# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)
1428# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)
1429# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)
1430# define R300_DVOCLK_ALWAYS_ONb (1 << 10)
1431# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)
1432# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)
1433# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)
1434# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)
1435# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)
1436# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)
1437# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)
1438# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)
1439# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)
1440# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)
1441# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)
1442#define RADEON_PLANE_3D_MASK_C 0x1d44
1443#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */
1444# define RADEON_PLL_MASK_READ_B (1 << 9)
1445#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */
1446#define RADEON_PMI_DATA 0x0f63 /* PCI */
1447#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */
1448#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */
1449#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */
1450#define RADEON_PMI_REGISTER 0x0f5c /* PCI */
1451#define RADEON_PPLL_CNTL 0x0002 /* PLL */
1452# define RADEON_PPLL_RESET (1 << 0)
1453# define RADEON_PPLL_SLEEP (1 << 1)
1454# define RADEON_PPLL_PVG_MASK (7 << 11)
1455# define RADEON_PPLL_PVG_SHIFT 11
1456# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)
1457# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)
1458# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)
1459#define RADEON_PPLL_DIV_0 0x0004 /* PLL */
1460#define RADEON_PPLL_DIV_1 0x0005 /* PLL */
1461#define RADEON_PPLL_DIV_2 0x0006 /* PLL */
1462#define RADEON_PPLL_DIV_3 0x0007 /* PLL */
1463# define RADEON_PPLL_FB3_DIV_MASK 0x07ff
1464# define RADEON_PPLL_POST3_DIV_MASK 0x00070000
1465#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */
1466# define RADEON_PPLL_REF_DIV_MASK 0x03ff
1467# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
1468# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
1469#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */
1470
1471#define RADEON_RBBM_GUICNTL 0x172c
1472# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
1473# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
1474# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
1475# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
1476#define RADEON_RBBM_SOFT_RESET 0x00f0
1477# define RADEON_SOFT_RESET_CP (1 << 0)
1478# define RADEON_SOFT_RESET_HI (1 << 1)
1479# define RADEON_SOFT_RESET_SE (1 << 2)
1480# define RADEON_SOFT_RESET_RE (1 << 3)
1481# define RADEON_SOFT_RESET_PP (1 << 4)
1482# define RADEON_SOFT_RESET_E2 (1 << 5)
1483# define RADEON_SOFT_RESET_RB (1 << 6)
1484# define RADEON_SOFT_RESET_HDP (1 << 7)
1485#define RADEON_RBBM_STATUS 0x0e40
1486# define RADEON_RBBM_FIFOCNT_MASK 0x007f
1487# define RADEON_RBBM_ACTIVE (1 << 31)
1488#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
1489# define RADEON_RB2D_DC_FLUSH (3 << 0)
1490# define RADEON_RB2D_DC_FREE (3 << 2)
1491# define RADEON_RB2D_DC_FLUSH_ALL 0xf
1492# define RADEON_RB2D_DC_BUSY (1 << 31)
1493#define RADEON_RB2D_DSTCACHE_MODE 0x3428
1494#define RADEON_DSTCACHE_CTLSTAT 0x1714
1495
1496#define RADEON_RB3D_ZCACHE_MODE 0x3250
1497#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
1498# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
1499#define RADEON_RB3D_DSTCACHE_MODE 0x3258
1500# define RADEON_RB3D_DC_CACHE_ENABLE (0)
1501# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)
1502# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)
1503# define RADEON_RB3D_DC_CACHE_DISABLE (3)
1504# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)
1505# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)
1506# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)
1507# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)
1508# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)
1509# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)
1510# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)
1511# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)
1512# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)
1513
1514#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C
1515# define RADEON_RB3D_DC_FLUSH (3 << 0)
1516# define RADEON_RB3D_DC_FREE (3 << 2)
1517# define RADEON_RB3D_DC_FLUSH_ALL 0xf
1518# define RADEON_RB3D_DC_BUSY (1 << 31)
1519
1520#define RADEON_REG_BASE 0x0f18 /* PCI */
1521#define RADEON_REGPROG_INF 0x0f09 /* PCI */
1522#define RADEON_REVISION_ID 0x0f08 /* PCI */
1523
1524#define RADEON_SC_BOTTOM 0x164c
1525#define RADEON_SC_BOTTOM_RIGHT 0x16f0
1526#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c
1527#define RADEON_SC_LEFT 0x1640
1528#define RADEON_SC_RIGHT 0x1644
1529#define RADEON_SC_TOP 0x1648
1530#define RADEON_SC_TOP_LEFT 0x16ec
1531#define RADEON_SC_TOP_LEFT_C 0x1c88
1532# define RADEON_SC_SIGN_MASK_LO 0x8000
1533# define RADEON_SC_SIGN_MASK_HI 0x80000000
1534#define RADEON_SCLK_CNTL 0x000d /* PLL */
1535# define RADEON_SCLK_SRC_SEL_MASK 0x0007
1536# define RADEON_DYN_STOP_LAT_MASK 0x00007ff8
1537# define RADEON_CP_MAX_DYN_STOP_LAT 0x0008
1538# define RADEON_SCLK_FORCEON_MASK 0xffff8000
1539# define RADEON_SCLK_FORCE_DISP2 (1<<15)
1540# define RADEON_SCLK_FORCE_CP (1<<16)
1541# define RADEON_SCLK_FORCE_HDP (1<<17)
1542# define RADEON_SCLK_FORCE_DISP1 (1<<18)
1543# define RADEON_SCLK_FORCE_TOP (1<<19)
1544# define RADEON_SCLK_FORCE_E2 (1<<20)
1545# define RADEON_SCLK_FORCE_SE (1<<21)
1546# define RADEON_SCLK_FORCE_IDCT (1<<22)
1547# define RADEON_SCLK_FORCE_VIP (1<<23)
1548# define RADEON_SCLK_FORCE_RE (1<<24)
1549# define RADEON_SCLK_FORCE_PB (1<<25)
1550# define RADEON_SCLK_FORCE_TAM (1<<26)
1551# define RADEON_SCLK_FORCE_TDM (1<<27)
1552# define RADEON_SCLK_FORCE_RB (1<<28)
1553# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)
1554# define RADEON_SCLK_FORCE_SUBPIC (1<<30)
1555# define RADEON_SCLK_FORCE_OV0 (1<<31)
1556# define R300_SCLK_FORCE_VAP (1<<21)
1557# define R300_SCLK_FORCE_SR (1<<25)
1558# define R300_SCLK_FORCE_PX (1<<26)
1559# define R300_SCLK_FORCE_TX (1<<27)
1560# define R300_SCLK_FORCE_US (1<<28)
1561# define R300_SCLK_FORCE_SU (1<<30)
1562#define R300_SCLK_CNTL2 0x1e /* PLL */
1563# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)
1564# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)
1565# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)
1566# define R300_SCLK_FORCE_TCL (1<<13)
1567# define R300_SCLK_FORCE_CBA (1<<14)
1568# define R300_SCLK_FORCE_GA (1<<15)
1569#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */
1570# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x0007
1571# define RADEON_SCLK_MORE_FORCEON 0x0700
1572#define RADEON_SDRAM_MODE_REG 0x0158
1573#define RADEON_SEQ8_DATA 0x03c5 /* VGA */
1574#define RADEON_SEQ8_IDX 0x03c4 /* VGA */
1575#define RADEON_SNAPSHOT_F_COUNT 0x0244
1576#define RADEON_SNAPSHOT_VH_COUNTS 0x0240
1577#define RADEON_SNAPSHOT_VIF_COUNT 0x024c
1578#define RADEON_SRC_OFFSET 0x15ac
1579#define RADEON_SRC_PITCH 0x15b0
1580#define RADEON_SRC_PITCH_OFFSET 0x1428
1581#define RADEON_SRC_SC_BOTTOM 0x165c
1582#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f4
1583#define RADEON_SRC_SC_RIGHT 0x1654
1584#define RADEON_SRC_X 0x1414
1585#define RADEON_SRC_X_Y 0x1590
1586#define RADEON_SRC_Y 0x1418
1587#define RADEON_SRC_Y_X 0x1434
1588#define RADEON_STATUS 0x0f06 /* PCI */
1589#define RADEON_SUBPIC_CNTL 0x0540 /* ? */
1590#define RADEON_SUB_CLASS 0x0f0a /* PCI */
1591#define RADEON_SURFACE_CNTL 0x0b00
1592# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
1593# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
1594# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
1595# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
1596# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
1597#define RADEON_SURFACE0_INFO 0x0b0c
1598# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)
1599# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)
1600# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)
1601# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)
1602# define R200_SURF_TILE_NONE (0 << 16)
1603# define R200_SURF_TILE_COLOR_MACRO (1 << 16)
1604# define R200_SURF_TILE_COLOR_MICRO (2 << 16)
1605# define R200_SURF_TILE_COLOR_BOTH (3 << 16)
1606# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)
1607# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)
1608# define R300_SURF_TILE_NONE (0 << 16)
1609# define R300_SURF_TILE_COLOR_MACRO (1 << 16)
1610# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)
1611# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)
1612# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)
1613# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)
1614# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)
1615#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
1616#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
1617#define RADEON_SURFACE1_INFO 0x0b1c
1618#define RADEON_SURFACE1_LOWER_BOUND 0x0b14
1619#define RADEON_SURFACE1_UPPER_BOUND 0x0b18
1620#define RADEON_SURFACE2_INFO 0x0b2c
1621#define RADEON_SURFACE2_LOWER_BOUND 0x0b24
1622#define RADEON_SURFACE2_UPPER_BOUND 0x0b28
1623#define RADEON_SURFACE3_INFO 0x0b3c
1624#define RADEON_SURFACE3_LOWER_BOUND 0x0b34
1625#define RADEON_SURFACE3_UPPER_BOUND 0x0b38
1626#define RADEON_SURFACE4_INFO 0x0b4c
1627#define RADEON_SURFACE4_LOWER_BOUND 0x0b44
1628#define RADEON_SURFACE4_UPPER_BOUND 0x0b48
1629#define RADEON_SURFACE5_INFO 0x0b5c
1630#define RADEON_SURFACE5_LOWER_BOUND 0x0b54
1631#define RADEON_SURFACE5_UPPER_BOUND 0x0b58
1632#define RADEON_SURFACE6_INFO 0x0b6c
1633#define RADEON_SURFACE6_LOWER_BOUND 0x0b64
1634#define RADEON_SURFACE6_UPPER_BOUND 0x0b68
1635#define RADEON_SURFACE7_INFO 0x0b7c
1636#define RADEON_SURFACE7_LOWER_BOUND 0x0b74
1637#define RADEON_SURFACE7_UPPER_BOUND 0x0b78
1638#define RADEON_SW_SEMAPHORE 0x013c
1639
1640#define RADEON_TEST_DEBUG_CNTL 0x0120
1641#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001
1642
1643#define RADEON_TEST_DEBUG_MUX 0x0124
1644#define RADEON_TEST_DEBUG_OUT 0x012c
1645#define RADEON_TMDS_PLL_CNTL 0x02a8
1646#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a4
1647# define RADEON_TMDS_TRANSMITTER_PLLEN 1
1648# define RADEON_TMDS_TRANSMITTER_PLLRST 2
1649#define RADEON_TRAIL_BRES_DEC 0x1614
1650#define RADEON_TRAIL_BRES_ERR 0x160c
1651#define RADEON_TRAIL_BRES_INC 0x1610
1652#define RADEON_TRAIL_X 0x1618
1653#define RADEON_TRAIL_X_SUB 0x1620
1654
1655#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */
1656# define RADEON_VCLK_SRC_SEL_MASK 0x03
1657# define RADEON_VCLK_SRC_SEL_CPUCLK 0x00
1658# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x01
1659# define RADEON_VCLK_SRC_SEL_BYTECLK 0x02
1660# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x03
1661# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)
1662# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)
1663# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)
1664
1665#define RADEON_VENDOR_ID 0x0f00 /* PCI */
1666#define RADEON_VGA_DDA_CONFIG 0x02e8
1667#define RADEON_VGA_DDA_ON_OFF 0x02ec
1668#define RADEON_VID_BUFFER_CONTROL 0x0900
1669#define RADEON_VIDEOMUX_CNTL 0x0190
1670
1671 /* VIP bus */
1672#define RADEON_VIPH_CH0_DATA 0x0c00
1673#define RADEON_VIPH_CH1_DATA 0x0c04
1674#define RADEON_VIPH_CH2_DATA 0x0c08
1675#define RADEON_VIPH_CH3_DATA 0x0c0c
1676#define RADEON_VIPH_CH0_ADDR 0x0c10
1677#define RADEON_VIPH_CH1_ADDR 0x0c14
1678#define RADEON_VIPH_CH2_ADDR 0x0c18
1679#define RADEON_VIPH_CH3_ADDR 0x0c1c
1680#define RADEON_VIPH_CH0_SBCNT 0x0c20
1681#define RADEON_VIPH_CH1_SBCNT 0x0c24
1682#define RADEON_VIPH_CH2_SBCNT 0x0c28
1683#define RADEON_VIPH_CH3_SBCNT 0x0c2c
1684#define RADEON_VIPH_CH0_ABCNT 0x0c30
1685#define RADEON_VIPH_CH1_ABCNT 0x0c34
1686#define RADEON_VIPH_CH2_ABCNT 0x0c38
1687#define RADEON_VIPH_CH3_ABCNT 0x0c3c
1688#define RADEON_VIPH_CONTROL 0x0c40
1689# define RADEON_VIP_BUSY 0
1690# define RADEON_VIP_IDLE 1
1691# define RADEON_VIP_RESET 2
1692# define RADEON_VIPH_EN (1 << 21)
1693#define RADEON_VIPH_DV_LAT 0x0c44
1694#define RADEON_VIPH_BM_CHUNK 0x0c48
1695#define RADEON_VIPH_DV_INT 0x0c4c
1696#define RADEON_VIPH_TIMEOUT_STAT 0x0c50
1697#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010
1698#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010
1699#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000
1700
1701#define RADEON_VIPH_REG_DATA 0x0084
1702#define RADEON_VIPH_REG_ADDR 0x0080
1703
1704
1705#define RADEON_WAIT_UNTIL 0x1720
1706# define RADEON_WAIT_CRTC_PFLIP (1 << 0)
1707# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)
1708# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)
1709# define RADEON_WAIT_CRTC_VLINE (1 << 3)
1710# define RADEON_WAIT_DMA_VID_IDLE (1 << 8)
1711# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)
1712# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */
1713# define RADEON_WAIT_OV0_FLIP (1 << 11)
1714# define RADEON_WAIT_AGP_FLUSH (1 << 13)
1715# define RADEON_WAIT_2D_IDLE (1 << 14)
1716# define RADEON_WAIT_3D_IDLE (1 << 15)
1717# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
1718# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
1719# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
1720# define RADEON_CMDFIFO_ENTRIES_SHIFT 10
1721# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f
1722# define RADEON_WAIT_VAP_IDLE (1 << 28)
1723# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)
1724# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)
1725# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)
1726
1727#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */
1728#define RADEON_XCLK_CNTL 0x000d /* PLL */
1729#define RADEON_XDLL_CNTL 0x000c /* PLL */
1730#define RADEON_XPLL_CNTL 0x000b /* PLL */
1731
1732
1733
1734/* Registers for 3D/TCL */
1735#define RADEON_PP_BORDER_COLOR_0 0x1d40
1736#define RADEON_PP_BORDER_COLOR_1 0x1d44
1737#define RADEON_PP_BORDER_COLOR_2 0x1d48
1738#define RADEON_PP_CNTL 0x1c38
1739# define RADEON_STIPPLE_ENABLE (1 << 0)
1740# define RADEON_SCISSOR_ENABLE (1 << 1)
1741# define RADEON_PATTERN_ENABLE (1 << 2)
1742# define RADEON_SHADOW_ENABLE (1 << 3)
1743# define RADEON_TEX_ENABLE_MASK (0xf << 4)
1744# define RADEON_TEX_0_ENABLE (1 << 4)
1745# define RADEON_TEX_1_ENABLE (1 << 5)
1746# define RADEON_TEX_2_ENABLE (1 << 6)
1747# define RADEON_TEX_3_ENABLE (1 << 7)
1748# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)
1749# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)
1750# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)
1751# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)
1752# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)
1753# define RADEON_PLANAR_YUV_ENABLE (1 << 20)
1754# define RADEON_SPECULAR_ENABLE (1 << 21)
1755# define RADEON_FOG_ENABLE (1 << 22)
1756# define RADEON_ALPHA_TEST_ENABLE (1 << 23)
1757# define RADEON_ANTI_ALIAS_NONE (0 << 24)
1758# define RADEON_ANTI_ALIAS_LINE (1 << 24)
1759# define RADEON_ANTI_ALIAS_POLY (2 << 24)
1760# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)
1761# define RADEON_BUMP_MAP_ENABLE (1 << 26)
1762# define RADEON_BUMPED_MAP_T0 (0 << 27)
1763# define RADEON_BUMPED_MAP_T1 (1 << 27)
1764# define RADEON_BUMPED_MAP_T2 (2 << 27)
1765# define RADEON_TEX_3D_ENABLE_0 (1 << 29)
1766# define RADEON_TEX_3D_ENABLE_1 (1 << 30)
1767# define RADEON_MC_ENABLE (1 << 31)
1768#define RADEON_PP_FOG_COLOR 0x1c18
1769# define RADEON_FOG_COLOR_MASK 0x00ffffff
1770# define RADEON_FOG_VERTEX (0 << 24)
1771# define RADEON_FOG_TABLE (1 << 24)
1772# define RADEON_FOG_USE_DEPTH (0 << 25)
1773# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)
1774# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)
1775#define RADEON_PP_LUM_MATRIX 0x1d00
1776#define RADEON_PP_MISC 0x1c14
1777# define RADEON_REF_ALPHA_MASK 0x000000ff
1778# define RADEON_ALPHA_TEST_FAIL (0 << 8)
1779# define RADEON_ALPHA_TEST_LESS (1 << 8)
1780# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)
1781# define RADEON_ALPHA_TEST_EQUAL (3 << 8)
1782# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)
1783# define RADEON_ALPHA_TEST_GREATER (5 << 8)
1784# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)
1785# define RADEON_ALPHA_TEST_PASS (7 << 8)
1786# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)
1787# define RADEON_CHROMA_FUNC_FAIL (0 << 16)
1788# define RADEON_CHROMA_FUNC_PASS (1 << 16)
1789# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)
1790# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)
1791# define RADEON_CHROMA_KEY_NEAREST (0 << 18)
1792# define RADEON_CHROMA_KEY_ZERO (1 << 18)
1793# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)
1794# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)
1795# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)
1796# define RADEON_SHADOW_PASS_1 (0 << 22)
1797# define RADEON_SHADOW_PASS_2 (1 << 22)
1798# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)
1799# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)
1800#define RADEON_PP_ROT_MATRIX_0 0x1d58
1801#define RADEON_PP_ROT_MATRIX_1 0x1d5c
1802#define RADEON_PP_TXFILTER_0 0x1c54
1803#define RADEON_PP_TXFILTER_1 0x1c6c
1804#define RADEON_PP_TXFILTER_2 0x1c84
1805# define RADEON_MAG_FILTER_NEAREST (0 << 0)
1806# define RADEON_MAG_FILTER_LINEAR (1 << 0)
1807# define RADEON_MAG_FILTER_MASK (1 << 0)
1808# define RADEON_MIN_FILTER_NEAREST (0 << 1)
1809# define RADEON_MIN_FILTER_LINEAR (1 << 1)
1810# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
1811# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
1812# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
1813# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
1814# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)
1815# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)
1816# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
1817# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
1818# define RADEON_MIN_FILTER_MASK (15 << 1)
1819# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)
1820# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)
1821# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)
1822# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)
1823# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)
1824# define RADEON_MAX_ANISO_MASK (7 << 5)
1825# define RADEON_LOD_BIAS_MASK (0xff << 8)
1826# define RADEON_LOD_BIAS_SHIFT 8
1827# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)
1828# define RADEON_MAX_MIP_LEVEL_SHIFT 16
1829# define RADEON_YUV_TO_RGB (1 << 20)
1830# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)
1831# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)
1832# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)
1833# define RADEON_WRAPEN_S (1 << 22)
1834# define RADEON_CLAMP_S_WRAP (0 << 23)
1835# define RADEON_CLAMP_S_MIRROR (1 << 23)
1836# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)
1837# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)
1838# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)
1839# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)
1840# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)
1841# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)
1842# define RADEON_CLAMP_S_MASK (7 << 23)
1843# define RADEON_WRAPEN_T (1 << 26)
1844# define RADEON_CLAMP_T_WRAP (0 << 27)
1845# define RADEON_CLAMP_T_MIRROR (1 << 27)
1846# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)
1847# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)
1848# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)
1849# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)
1850# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)
1851# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)
1852# define RADEON_CLAMP_T_MASK (7 << 27)
1853# define RADEON_BORDER_MODE_OGL (0 << 31)
1854# define RADEON_BORDER_MODE_D3D (1 << 31)
1855#define RADEON_PP_TXFORMAT_0 0x1c58
1856#define RADEON_PP_TXFORMAT_1 0x1c70
1857#define RADEON_PP_TXFORMAT_2 0x1c88
1858# define RADEON_TXFORMAT_I8 (0 << 0)
1859# define RADEON_TXFORMAT_AI88 (1 << 0)
1860# define RADEON_TXFORMAT_RGB332 (2 << 0)
1861# define RADEON_TXFORMAT_ARGB1555 (3 << 0)
1862# define RADEON_TXFORMAT_RGB565 (4 << 0)
1863# define RADEON_TXFORMAT_ARGB4444 (5 << 0)
1864# define RADEON_TXFORMAT_ARGB8888 (6 << 0)
1865# define RADEON_TXFORMAT_RGBA8888 (7 << 0)
1866# define RADEON_TXFORMAT_Y8 (8 << 0)
1867# define RADEON_TXFORMAT_VYUY422 (10 << 0)
1868# define RADEON_TXFORMAT_YVYU422 (11 << 0)
1869# define RADEON_TXFORMAT_DXT1 (12 << 0)
1870# define RADEON_TXFORMAT_DXT23 (14 << 0)
1871# define RADEON_TXFORMAT_DXT45 (15 << 0)
1872# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)
1873# define RADEON_TXFORMAT_FORMAT_SHIFT 0
1874# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)
1875# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)
1876# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)
1877# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)
1878# define RADEON_TXFORMAT_WIDTH_SHIFT 8
1879# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)
1880# define RADEON_TXFORMAT_HEIGHT_SHIFT 12
1881# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)
1882# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 16
1883# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)
1884# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 20
1885# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)
1886# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)
1887# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)
1888# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)
1889# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)
1890# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)
1891# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)
1892# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)
1893# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)
1894# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)
1895# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)
1896# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)
1897#define RADEON_PP_CUBIC_FACES_0 0x1d24
1898#define RADEON_PP_CUBIC_FACES_1 0x1d28
1899#define RADEON_PP_CUBIC_FACES_2 0x1d2c
1900# define RADEON_FACE_WIDTH_1_SHIFT 0
1901# define RADEON_FACE_HEIGHT_1_SHIFT 4
1902# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)
1903# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)
1904# define RADEON_FACE_WIDTH_2_SHIFT 8
1905# define RADEON_FACE_HEIGHT_2_SHIFT 12
1906# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)
1907# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)
1908# define RADEON_FACE_WIDTH_3_SHIFT 16
1909# define RADEON_FACE_HEIGHT_3_SHIFT 20
1910# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)
1911# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)
1912# define RADEON_FACE_WIDTH_4_SHIFT 24
1913# define RADEON_FACE_HEIGHT_4_SHIFT 28
1914# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)
1915# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)
1916
1917#define RADEON_PP_TXOFFSET_0 0x1c5c
1918#define RADEON_PP_TXOFFSET_1 0x1c74
1919#define RADEON_PP_TXOFFSET_2 0x1c8c
1920# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)
1921# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)
1922# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)
1923# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)
1924# define RADEON_TXO_MACRO_LINEAR (0 << 2)
1925# define RADEON_TXO_MACRO_TILE (1 << 2)
1926# define RADEON_TXO_MICRO_LINEAR (0 << 3)
1927# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)
1928# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)
1929# define RADEON_TXO_OFFSET_MASK 0xffffffe0
1930# define RADEON_TXO_OFFSET_SHIFT 5
1931
1932#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
1933#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd4
1934#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd8
1935#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc
1936#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de0
1937#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
1938#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e04
1939#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e08
1940#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c
1941#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e10
1942#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
1943#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e18
1944#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c
1945#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e20
1946#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e24
1947
1948#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
1949#define RADEON_PP_TEX_SIZE_1 0x1d0c
1950#define RADEON_PP_TEX_SIZE_2 0x1d14
1951# define RADEON_TEX_USIZE_MASK (0x7ff << 0)
1952# define RADEON_TEX_USIZE_SHIFT 0
1953# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)
1954# define RADEON_TEX_VSIZE_SHIFT 16
1955# define RADEON_SIGNED_RGB_MASK (1 << 30)
1956# define RADEON_SIGNED_RGB_SHIFT 30
1957# define RADEON_SIGNED_ALPHA_MASK (1 << 31)
1958# define RADEON_SIGNED_ALPHA_SHIFT 31
1959#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */
1960#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */
1961#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */
1962/* note: bits 13-5: 32 byte aligned stride of texture map */
1963
1964#define RADEON_PP_TXCBLEND_0 0x1c60
1965#define RADEON_PP_TXCBLEND_1 0x1c78
1966#define RADEON_PP_TXCBLEND_2 0x1c90
1967# define RADEON_COLOR_ARG_A_SHIFT 0
1968# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)
1969# define RADEON_COLOR_ARG_A_ZERO (0 << 0)
1970# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)
1971# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)
1972# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)
1973# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)
1974# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)
1975# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)
1976# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)
1977# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)
1978# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)
1979# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)
1980# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)
1981# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)
1982# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)
1983# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)
1984# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)
1985# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)
1986# define RADEON_COLOR_ARG_B_SHIFT 5
1987# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)
1988# define RADEON_COLOR_ARG_B_ZERO (0 << 5)
1989# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)
1990# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)
1991# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)
1992# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)
1993# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)
1994# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)
1995# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)
1996# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)
1997# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)
1998# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)
1999# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)
2000# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)
2001# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)
2002# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)
2003# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)
2004# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)
2005# define RADEON_COLOR_ARG_C_SHIFT 10
2006# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)
2007# define RADEON_COLOR_ARG_C_ZERO (0 << 10)
2008# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)
2009# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)
2010# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)
2011# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)
2012# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)
2013# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)
2014# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)
2015# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)
2016# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)
2017# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)
2018# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)
2019# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)
2020# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)
2021# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)
2022# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)
2023# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)
2024# define RADEON_COMP_ARG_A (1 << 15)
2025# define RADEON_COMP_ARG_A_SHIFT 15
2026# define RADEON_COMP_ARG_B (1 << 16)
2027# define RADEON_COMP_ARG_B_SHIFT 16
2028# define RADEON_COMP_ARG_C (1 << 17)
2029# define RADEON_COMP_ARG_C_SHIFT 17
2030# define RADEON_BLEND_CTL_MASK (7 << 18)
2031# define RADEON_BLEND_CTL_ADD (0 << 18)
2032# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)
2033# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)
2034# define RADEON_BLEND_CTL_BLEND (3 << 18)
2035# define RADEON_BLEND_CTL_DOT3 (4 << 18)
2036# define RADEON_SCALE_SHIFT 21
2037# define RADEON_SCALE_MASK (3 << 21)
2038# define RADEON_SCALE_1X (0 << 21)
2039# define RADEON_SCALE_2X (1 << 21)
2040# define RADEON_SCALE_4X (2 << 21)
2041# define RADEON_CLAMP_TX (1 << 23)
2042# define RADEON_T0_EQ_TCUR (1 << 24)
2043# define RADEON_T1_EQ_TCUR (1 << 25)
2044# define RADEON_T2_EQ_TCUR (1 << 26)
2045# define RADEON_T3_EQ_TCUR (1 << 27)
2046# define RADEON_COLOR_ARG_MASK 0x1f
2047# define RADEON_COMP_ARG_SHIFT 15
2048#define RADEON_PP_TXABLEND_0 0x1c64
2049#define RADEON_PP_TXABLEND_1 0x1c7c
2050#define RADEON_PP_TXABLEND_2 0x1c94
2051# define RADEON_ALPHA_ARG_A_SHIFT 0
2052# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)
2053# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)
2054# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)
2055# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)
2056# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)
2057# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)
2058# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)
2059# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)
2060# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)
2061# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)
2062# define RADEON_ALPHA_ARG_B_SHIFT 4
2063# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)
2064# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)
2065# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)
2066# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)
2067# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)
2068# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)
2069# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)
2070# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)
2071# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)
2072# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)
2073# define RADEON_ALPHA_ARG_C_SHIFT 8
2074# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)
2075# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)
2076# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)
2077# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)
2078# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)
2079# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)
2080# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)
2081# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)
2082# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)
2083# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)
2084# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)
2085# define RADEON_ALPHA_ARG_MASK 0xf
2086
2087#define RADEON_PP_TFACTOR_0 0x1c68
2088#define RADEON_PP_TFACTOR_1 0x1c80
2089#define RADEON_PP_TFACTOR_2 0x1c98
2090
2091#define RADEON_RB3D_BLENDCNTL 0x1c20
2092# define RADEON_COMB_FCN_MASK (3 << 12)
2093# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)
2094# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)
2095# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)
2096# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)
2097# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)
2098# define RADEON_SRC_BLEND_GL_ONE (33 << 16)
2099# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)
2100# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)
2101# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)
2102# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)
2103# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)
2104# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)
2105# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)
2106# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)
2107# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)
2108# define RADEON_SRC_BLEND_MASK (63 << 16)
2109# define RADEON_DST_BLEND_GL_ZERO (32 << 24)
2110# define RADEON_DST_BLEND_GL_ONE (33 << 24)
2111# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)
2112# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)
2113# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)
2114# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)
2115# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)
2116# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)
2117# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)
2118# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)
2119# define RADEON_DST_BLEND_MASK (63 << 24)
2120#define RADEON_RB3D_CNTL 0x1c3c
2121# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
2122# define RADEON_PLANE_MASK_ENABLE (1 << 1)
2123# define RADEON_DITHER_ENABLE (1 << 2)
2124# define RADEON_ROUND_ENABLE (1 << 3)
2125# define RADEON_SCALE_DITHER_ENABLE (1 << 4)
2126# define RADEON_DITHER_INIT (1 << 5)
2127# define RADEON_ROP_ENABLE (1 << 6)
2128# define RADEON_STENCIL_ENABLE (1 << 7)
2129# define RADEON_Z_ENABLE (1 << 8)
2130# define RADEON_DEPTH_XZ_OFFEST_ENABLE (1 << 9)
2131# define RADEON_COLOR_FORMAT_ARGB1555 (3 << 10)
2132# define RADEON_COLOR_FORMAT_RGB565 (4 << 10)
2133# define RADEON_COLOR_FORMAT_ARGB8888 (6 << 10)
2134# define RADEON_COLOR_FORMAT_RGB332 (7 << 10)
2135# define RADEON_COLOR_FORMAT_Y8 (8 << 10)
2136# define RADEON_COLOR_FORMAT_RGB8 (9 << 10)
2137# define RADEON_COLOR_FORMAT_YUV422_VYUY (11 << 10)
2138# define RADEON_COLOR_FORMAT_YUV422_YVYU (12 << 10)
2139# define RADEON_COLOR_FORMAT_aYUV444 (14 << 10)
2140# define RADEON_COLOR_FORMAT_ARGB4444 (15 << 10)
2141# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)
2142#define RADEON_RB3D_COLOROFFSET 0x1c40
2143# define RADEON_COLOROFFSET_MASK 0xfffffff0
2144#define RADEON_RB3D_COLORPITCH 0x1c48
2145# define RADEON_COLORPITCH_MASK 0x000001ff8
2146# define RADEON_COLOR_TILE_ENABLE (1 << 16)
2147# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)
2148# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)
2149# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)
2150# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)
2151#define RADEON_RB3D_DEPTHOFFSET 0x1c24
2152#define RADEON_RB3D_DEPTHPITCH 0x1c28
2153# define RADEON_DEPTHPITCH_MASK 0x00001ff8
2154# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)
2155# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)
2156# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)
2157#define RADEON_RB3D_PLANEMASK 0x1d84
2158#define RADEON_RB3D_ROPCNTL 0x1d80
2159# define RADEON_ROP_MASK (15 << 8)
2160# define RADEON_ROP_CLEAR (0 << 8)
2161# define RADEON_ROP_NOR (1 << 8)
2162# define RADEON_ROP_AND_INVERTED (2 << 8)
2163# define RADEON_ROP_COPY_INVERTED (3 << 8)
2164# define RADEON_ROP_AND_REVERSE (4 << 8)
2165# define RADEON_ROP_INVERT (5 << 8)
2166# define RADEON_ROP_XOR (6 << 8)
2167# define RADEON_ROP_NAND (7 << 8)
2168# define RADEON_ROP_AND (8 << 8)
2169# define RADEON_ROP_EQUIV (9 << 8)
2170# define RADEON_ROP_NOOP (10 << 8)
2171# define RADEON_ROP_OR_INVERTED (11 << 8)
2172# define RADEON_ROP_COPY (12 << 8)
2173# define RADEON_ROP_OR_REVERSE (13 << 8)
2174# define RADEON_ROP_OR (14 << 8)
2175# define RADEON_ROP_SET (15 << 8)
2176#define RADEON_RB3D_STENCILREFMASK 0x1d7c
2177# define RADEON_STENCIL_REF_SHIFT 0
2178# define RADEON_STENCIL_REF_MASK (0xff << 0)
2179# define RADEON_STENCIL_MASK_SHIFT 16
2180# define RADEON_STENCIL_VALUE_MASK (0xff << 16)
2181# define RADEON_STENCIL_WRITEMASK_SHIFT 24
2182# define RADEON_STENCIL_WRITE_MASK (0xff << 24)
2183#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
2184# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)
2185# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
2186# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
2187# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)
2188# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)
2189# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)
2190# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)
2191# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)
2192# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)
2193# define RADEON_Z_TEST_NEVER (0 << 4)
2194# define RADEON_Z_TEST_LESS (1 << 4)
2195# define RADEON_Z_TEST_LEQUAL (2 << 4)
2196# define RADEON_Z_TEST_EQUAL (3 << 4)
2197# define RADEON_Z_TEST_GEQUAL (4 << 4)
2198# define RADEON_Z_TEST_GREATER (5 << 4)
2199# define RADEON_Z_TEST_NEQUAL (6 << 4)
2200# define RADEON_Z_TEST_ALWAYS (7 << 4)
2201# define RADEON_Z_TEST_MASK (7 << 4)
2202# define RADEON_STENCIL_TEST_NEVER (0 << 12)
2203# define RADEON_STENCIL_TEST_LESS (1 << 12)
2204# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)
2205# define RADEON_STENCIL_TEST_EQUAL (3 << 12)
2206# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)
2207# define RADEON_STENCIL_TEST_GREATER (5 << 12)
2208# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)
2209# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
2210# define RADEON_STENCIL_TEST_MASK (0x7 << 12)
2211# define RADEON_STENCIL_FAIL_KEEP (0 << 16)
2212# define RADEON_STENCIL_FAIL_ZERO (1 << 16)
2213# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)
2214# define RADEON_STENCIL_FAIL_INC (3 << 16)
2215# define RADEON_STENCIL_FAIL_DEC (4 << 16)
2216# define RADEON_STENCIL_FAIL_INVERT (5 << 16)
2217# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)
2218# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)
2219# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)
2220# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
2221# define RADEON_STENCIL_ZPASS_INC (3 << 20)
2222# define RADEON_STENCIL_ZPASS_DEC (4 << 20)
2223# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)
2224# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)
2225# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)
2226# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)
2227# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
2228# define RADEON_STENCIL_ZFAIL_INC (3 << 24)
2229# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)
2230# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)
2231# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)
2232# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
2233# define RADEON_FORCE_Z_DIRTY (1 << 29)
2234# define RADEON_Z_WRITE_ENABLE (1 << 30)
2235#define RADEON_RE_LINE_PATTERN 0x1cd0
2236# define RADEON_LINE_PATTERN_MASK 0x0000ffff
2237# define RADEON_LINE_REPEAT_COUNT_SHIFT 16
2238# define RADEON_LINE_PATTERN_START_SHIFT 24
2239# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)
2240# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)
2241# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)
2242#define RADEON_RE_LINE_STATE 0x1cd4
2243# define RADEON_LINE_CURRENT_PTR_SHIFT 0
2244# define RADEON_LINE_CURRENT_COUNT_SHIFT 8
2245#define RADEON_RE_MISC 0x26c4
2246# define RADEON_STIPPLE_COORD_MASK 0x1f
2247# define RADEON_STIPPLE_X_OFFSET_SHIFT 0
2248# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)
2249# define RADEON_STIPPLE_Y_OFFSET_SHIFT 8
2250# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)
2251# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)
2252# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)
2253#define RADEON_RE_SOLID_COLOR 0x1c1c
2254#define RADEON_RE_TOP_LEFT 0x26c0
2255# define RADEON_RE_LEFT_SHIFT 0
2256# define RADEON_RE_TOP_SHIFT 16
2257#define RADEON_RE_WIDTH_HEIGHT 0x1c44
2258# define RADEON_RE_WIDTH_SHIFT 0
2259# define RADEON_RE_HEIGHT_SHIFT 16
2260
2261#define RADEON_SE_CNTL 0x1c4c
2262# define RADEON_FFACE_CULL_CW (0 << 0)
2263# define RADEON_FFACE_CULL_CCW (1 << 0)
2264# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)
2265# define RADEON_BFACE_CULL (0 << 1)
2266# define RADEON_BFACE_SOLID (3 << 1)
2267# define RADEON_FFACE_CULL (0 << 3)
2268# define RADEON_FFACE_SOLID (3 << 3)
2269# define RADEON_FFACE_CULL_MASK (3 << 3)
2270# define RADEON_BADVTX_CULL_DISABLE (1 << 5)
2271# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)
2272# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)
2273# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)
2274# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
2275# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)
2276# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
2277# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
2278# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)
2279# define RADEON_ALPHA_SHADE_SOLID (0 << 10)
2280# define RADEON_ALPHA_SHADE_FLAT (1 << 10)
2281# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
2282# define RADEON_ALPHA_SHADE_MASK (3 << 10)
2283# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)
2284# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
2285# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
2286# define RADEON_SPECULAR_SHADE_MASK (3 << 12)
2287# define RADEON_FOG_SHADE_SOLID (0 << 14)
2288# define RADEON_FOG_SHADE_FLAT (1 << 14)
2289# define RADEON_FOG_SHADE_GOURAUD (2 << 14)
2290# define RADEON_FOG_SHADE_MASK (3 << 14)
2291# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)
2292# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)
2293# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)
2294# define RADEON_WIDELINE_ENABLE (1 << 20)
2295# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
2296# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
2297# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)
2298# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
2299# define RADEON_ROUND_MODE_TRUNC (0 << 28)
2300# define RADEON_ROUND_MODE_ROUND (1 << 28)
2301# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)
2302# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)
2303# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)
2304# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
2305# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)
2306# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)
2307#define R200_RE_CNTL0x1c50
2308# define R200_STIPPLE_ENABLE0x1
2309# define R200_SCISSOR_ENABLE0x2
2310# define R200_PATTERN_ENABLE0x4
2311# define R200_PERSPECTIVE_ENABLE0x8
2312# define R200_POINT_SMOOTH0x20
2313# define R200_VTX_STQ0_D3D0x00010000
2314# define R200_VTX_STQ1_D3D0x00040000
2315# define R200_VTX_STQ2_D3D0x00100000
2316# define R200_VTX_STQ3_D3D0x00400000
2317# define R200_VTX_STQ4_D3D0x01000000
2318# define R200_VTX_STQ5_D3D0x04000000
2319#define R200_RE_SCISSOR_TL_00x1cd8
2320#define R200_RE_SCISSOR_BR_00x1cdc
2321#define R200_RE_SCISSOR_TL_10x1ce0
2322#define R200_RE_SCISSOR_BR_10x1ce4
2323#define R200_RE_SCISSOR_TL_20x1ce8
2324#define R200_RE_SCISSOR_BR_20x1cec
2325# define R200_SCISSOR_X_SHIFT0
2326# define R200_SCISSOR_Y_SHIFT16
2327#define RADEON_SE_CNTL_STATUS 0x2140
2328# define RADEON_VC_NO_SWAP (0 << 0)
2329# define RADEON_VC_16BIT_SWAP (1 << 0)
2330# define RADEON_VC_32BIT_SWAP (2 << 0)
2331# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)
2332# define RADEON_TCL_BYPASS (1 << 8)
2333#define RADEON_SE_COORD_FMT 0x1c50
2334# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)
2335# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)
2336# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)
2337# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)
2338# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)
2339# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)
2340# define RADEON_VTX_W0_NORMALIZE (1 << 12)
2341# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)
2342# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)
2343# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)
2344# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)
2345# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)
2346# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)
2347# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)
2348#define RADEON_SE_LINE_WIDTH 0x1db8
2349#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c
2350# define RADEON_LIGHTING_ENABLE (1 << 0)
2351# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)
2352# define RADEON_LOCAL_VIEWER (1 << 2)
2353# define RADEON_NORMALIZE_NORMALS (1 << 3)
2354# define RADEON_RESCALE_NORMALS (1 << 4)
2355# define RADEON_SPECULAR_LIGHTS (1 << 5)
2356# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)
2357# define RADEON_LIGHT_ALPHA (1 << 7)
2358# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)
2359# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)
2360# define RADEON_LM_SOURCE_STATE_PREMULT 0
2361# define RADEON_LM_SOURCE_STATE_MULT 1
2362# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 2
2363# define RADEON_LM_SOURCE_VERTEX_SPECULAR 3
2364# define RADEON_EMISSIVE_SOURCE_SHIFT 16
2365# define RADEON_AMBIENT_SOURCE_SHIFT 18
2366# define RADEON_DIFFUSE_SOURCE_SHIFT 20
2367# define RADEON_SPECULAR_SOURCE_SHIFT 22
2368#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x2220
2369#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224
2370#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228
2371#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c
2372#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x2230
2373#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234
2374#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238
2375#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c
2376#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
2377#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214
2378#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218
2379#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c
2380#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x2240
2381#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244
2382#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248
2383#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c
2384#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c
2385# define RADEON_MODELVIEW_0_SHIFT 0
2386# define RADEON_MODELVIEW_1_SHIFT 4
2387# define RADEON_MODELVIEW_2_SHIFT 8
2388# define RADEON_MODELVIEW_3_SHIFT 12
2389# define RADEON_IT_MODELVIEW_0_SHIFT 16
2390# define RADEON_IT_MODELVIEW_1_SHIFT 20
2391# define RADEON_IT_MODELVIEW_2_SHIFT 24
2392# define RADEON_IT_MODELVIEW_3_SHIFT 28
2393#define RADEON_SE_TCL_MATRIX_SELECT_1 0x2260
2394# define RADEON_MODELPROJECT_0_SHIFT 0
2395# define RADEON_MODELPROJECT_1_SHIFT 4
2396# define RADEON_MODELPROJECT_2_SHIFT 8
2397# define RADEON_MODELPROJECT_3_SHIFT 12
2398# define RADEON_TEXMAT_0_SHIFT 16
2399# define RADEON_TEXMAT_1_SHIFT 20
2400# define RADEON_TEXMAT_2_SHIFT 24
2401# define RADEON_TEXMAT_3_SHIFT 28
2402
2403
2404#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
2405# define RADEON_TCL_VTX_W0 (1 << 0)
2406# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)
2407# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)
2408# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)
2409# define RADEON_TCL_VTX_FP_SPEC (1 << 4)
2410# define RADEON_TCL_VTX_FP_FOG (1 << 5)
2411# define RADEON_TCL_VTX_PK_SPEC (1 << 6)
2412# define RADEON_TCL_VTX_ST0 (1 << 7)
2413# define RADEON_TCL_VTX_ST1 (1 << 8)
2414# define RADEON_TCL_VTX_Q1 (1 << 9)
2415# define RADEON_TCL_VTX_ST2 (1 << 10)
2416# define RADEON_TCL_VTX_Q2 (1 << 11)
2417# define RADEON_TCL_VTX_ST3 (1 << 12)
2418# define RADEON_TCL_VTX_Q3 (1 << 13)
2419# define RADEON_TCL_VTX_Q0 (1 << 14)
2420# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 15
2421# define RADEON_TCL_VTX_NORM0 (1 << 18)
2422# define RADEON_TCL_VTX_XY1 (1 << 27)
2423# define RADEON_TCL_VTX_Z1 (1 << 28)
2424# define RADEON_TCL_VTX_W1 (1 << 29)
2425# define RADEON_TCL_VTX_NORM1 (1 << 30)
2426# define RADEON_TCL_VTX_Z0 (1 << 31)
2427
2428#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x2258
2429# define RADEON_TCL_COMPUTE_XYZW (1 << 0)
2430# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)
2431# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)
2432# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)
2433# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)
2434# define RADEON_TCL_TEX_INPUT_TEX_0 0
2435# define RADEON_TCL_TEX_INPUT_TEX_1 1
2436# define RADEON_TCL_TEX_INPUT_TEX_2 2
2437# define RADEON_TCL_TEX_INPUT_TEX_3 3
2438# define RADEON_TCL_TEX_COMPUTED_TEX_0 8
2439# define RADEON_TCL_TEX_COMPUTED_TEX_1 9
2440# define RADEON_TCL_TEX_COMPUTED_TEX_2 10
2441# define RADEON_TCL_TEX_COMPUTED_TEX_3 11
2442# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 16
2443# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 20
2444# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 24
2445# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 28
2446
2447#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x2270
2448# define RADEON_LIGHT_0_ENABLE (1 << 0)
2449# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)
2450# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)
2451# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)
2452# define RADEON_LIGHT_0_IS_SPOT (1 << 4)
2453# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)
2454# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)
2455# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)
2456# define RADEON_LIGHT_0_SHIFT 0
2457# define RADEON_LIGHT_1_ENABLE (1 << 16)
2458# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)
2459# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)
2460# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)
2461# define RADEON_LIGHT_1_IS_SPOT (1 << 20)
2462# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)
2463# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)
2464# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)
2465# define RADEON_LIGHT_1_SHIFT 16
2466#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x2274
2467# define RADEON_LIGHT_2_SHIFT 0
2468# define RADEON_LIGHT_3_SHIFT 16
2469#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x2278
2470# define RADEON_LIGHT_4_SHIFT 0
2471# define RADEON_LIGHT_5_SHIFT 16
2472#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c
2473# define RADEON_LIGHT_6_SHIFT 0
2474# define RADEON_LIGHT_7_SHIFT 16
2475
2476#define RADEON_SE_TCL_SHININESS 0x2250
2477
2478#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x2268
2479# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)
2480# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)
2481# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)
2482# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)
2483# define RADEON_TEXMAT_0_ENABLE (1 << 4)
2484# define RADEON_TEXMAT_1_ENABLE (1 << 5)
2485# define RADEON_TEXMAT_2_ENABLE (1 << 6)
2486# define RADEON_TEXMAT_3_ENABLE (1 << 7)
2487# define RADEON_TEXGEN_INPUT_MASK 0xf
2488# define RADEON_TEXGEN_INPUT_TEXCOORD_0 0
2489# define RADEON_TEXGEN_INPUT_TEXCOORD_1 1
2490# define RADEON_TEXGEN_INPUT_TEXCOORD_2 2
2491# define RADEON_TEXGEN_INPUT_TEXCOORD_3 3
2492# define RADEON_TEXGEN_INPUT_OBJ 4
2493# define RADEON_TEXGEN_INPUT_EYE 5
2494# define RADEON_TEXGEN_INPUT_EYE_NORMAL 6
2495# define RADEON_TEXGEN_INPUT_EYE_REFLECT 7
2496# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 8
2497# define RADEON_TEXGEN_0_INPUT_SHIFT 16
2498# define RADEON_TEXGEN_1_INPUT_SHIFT 20
2499# define RADEON_TEXGEN_2_INPUT_SHIFT 24
2500# define RADEON_TEXGEN_3_INPUT_SHIFT 28
2501
2502#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x2264
2503# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)
2504# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)
2505# define RADEON_UCP_ENABLE_0 (1 << 2)
2506# define RADEON_UCP_ENABLE_1 (1 << 3)
2507# define RADEON_UCP_ENABLE_2 (1 << 4)
2508# define RADEON_UCP_ENABLE_3 (1 << 5)
2509# define RADEON_UCP_ENABLE_4 (1 << 6)
2510# define RADEON_UCP_ENABLE_5 (1 << 7)
2511# define RADEON_TCL_FOG_MASK (3 << 8)
2512# define RADEON_TCL_FOG_DISABLE (0 << 8)
2513# define RADEON_TCL_FOG_EXP (1 << 8)
2514# define RADEON_TCL_FOG_EXP2 (2 << 8)
2515# define RADEON_TCL_FOG_LINEAR (3 << 8)
2516# define RADEON_RNG_BASED_FOG (1 << 10)
2517# define RADEON_LIGHT_TWOSIDE (1 << 11)
2518# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)
2519# define RADEON_BLEND_OP_COUNT_SHIFT 12
2520# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)
2521# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)
2522# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)
2523# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)
2524# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)
2525# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)
2526# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)
2527# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)
2528# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)
2529# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)
2530# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)
2531# define RADEON_CULL_FRONT_IS_CW (0 << 28)
2532# define RADEON_CULL_FRONT_IS_CCW (1 << 28)
2533# define RADEON_CULL_FRONT (1 << 29)
2534# define RADEON_CULL_BACK (1 << 30)
2535# define RADEON_FORCE_W_TO_ONE (1 << 31)
2536
2537#define RADEON_SE_VPORT_XSCALE 0x1d98
2538#define RADEON_SE_VPORT_XOFFSET 0x1d9c
2539#define RADEON_SE_VPORT_YSCALE 0x1da0
2540#define RADEON_SE_VPORT_YOFFSET 0x1da4
2541#define RADEON_SE_VPORT_ZSCALE 0x1da8
2542#define RADEON_SE_VPORT_ZOFFSET 0x1dac
2543#define RADEON_SE_ZBIAS_FACTOR 0x1db0
2544#define RADEON_SE_ZBIAS_CONSTANT 0x1db4
2545
2546#define RADEON_SE_VTX_FMT 0x2080
2547# define RADEON_SE_VTX_FMT_XY 0x00000000
2548# define RADEON_SE_VTX_FMT_W0 0x00000001
2549# define RADEON_SE_VTX_FMT_FPCOLOR 0x00000002
2550# define RADEON_SE_VTX_FMT_FPALPHA 0x00000004
2551# define RADEON_SE_VTX_FMT_PKCOLOR 0x00000008
2552# define RADEON_SE_VTX_FMT_FPSPEC 0x00000010
2553# define RADEON_SE_VTX_FMT_FPFOG 0x00000020
2554# define RADEON_SE_VTX_FMT_PKSPEC 0x00000040
2555# define RADEON_SE_VTX_FMT_ST0 0x00000080
2556# define RADEON_SE_VTX_FMT_ST1 0x00000100
2557# define RADEON_SE_VTX_FMT_Q1 0x00000200
2558# define RADEON_SE_VTX_FMT_ST2 0x00000400
2559# define RADEON_SE_VTX_FMT_Q2 0x00000800
2560# define RADEON_SE_VTX_FMT_ST3 0x00001000
2561# define RADEON_SE_VTX_FMT_Q3 0x00002000
2562# define RADEON_SE_VTX_FMT_Q0 0x00004000
2563# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000
2564# define RADEON_SE_VTX_FMT_N0 0x00040000
2565# define RADEON_SE_VTX_FMT_XY1 0x08000000
2566# define RADEON_SE_VTX_FMT_Z1 0x10000000
2567# define RADEON_SE_VTX_FMT_W1 0x20000000
2568# define RADEON_SE_VTX_FMT_N1 0x40000000
2569# define RADEON_SE_VTX_FMT_Z 0x80000000
2570
2571#define RADEON_SE_VF_CNTL 0x2084
2572# define RADEON_VF_PRIM_TYPE_POINT_LIST 1
2573# define RADEON_VF_PRIM_TYPE_LINE_LIST 2
2574# define RADEON_VF_PRIM_TYPE_LINE_STRIP 3
2575# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 4
2576# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 5
2577# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 6
2578# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 7
2579# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 8
2580# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 9
2581# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 10
2582# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 11
2583# define RADEON_VF_PRIM_TYPE_LINE_LOOP 12
2584# define RADEON_VF_PRIM_TYPE_QUAD_LIST 13
2585# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 14
2586# define RADEON_VF_PRIM_TYPE_POLYGON 15
2587# define RADEON_VF_PRIM_WALK_STATE (0<<4)
2588# define RADEON_VF_PRIM_WALK_INDEX (1<<4)
2589# define RADEON_VF_PRIM_WALK_LIST (2<<4)
2590# define RADEON_VF_PRIM_WALK_DATA (3<<4)
2591# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)
2592# define RADEON_VF_RADEON_MODE (1<<8)
2593# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)
2594# define RADEON_VF_PROG_STREAM_ENA (1<<10)
2595# define RADEON_VF_INDEX_SIZE_SHIFT 11
2596# define RADEON_VF_NUM_VERTICES_SHIFT 16
2597
2598#define RADEON_SE_PORT_DATA00x2000
2599
2600#define R200_SE_VAP_CNTL0x2080
2601# define R200_VAP_TCL_ENABLE0x00000001
2602# define R200_VAP_SINGLE_BUF_STATE_ENABLE0x00000010
2603# define R200_VAP_FORCE_W_TO_ONE0x00010000
2604# define R200_VAP_D3D_TEX_DEFAULT0x00020000
2605# define R200_VAP_VF_MAX_VTX_NUM__SHIFT18
2606# define R200_VAP_VF_MAX_VTX_NUM(9 << 18)
2607# define R200_VAP_DX_CLIP_SPACE_DEF0x00400000
2608#define R200_VF_MAX_VTX_INDX0x210c
2609#define R200_VF_MIN_VTX_INDX0x2110
2610#define R200_SE_VTE_CNTL0x20b0
2611# define R200_VPORT_X_SCALE_ENA0x00000001
2612# define R200_VPORT_X_OFFSET_ENA0x00000002
2613# define R200_VPORT_Y_SCALE_ENA0x00000004
2614# define R200_VPORT_Y_OFFSET_ENA0x00000008
2615# define R200_VPORT_Z_SCALE_ENA0x00000010
2616# define R200_VPORT_Z_OFFSET_ENA0x00000020
2617# define R200_VTX_XY_FMT0x00000100
2618# define R200_VTX_Z_FMT0x00000200
2619# define R200_VTX_W0_FMT0x00000400
2620# define R200_VTX_W0_NORMALIZE0x00000800
2621# define R200_VTX_ST_DENORMALIZED0x00001000
2622#define R200_SE_VAP_CNTL_STATUS0x2140
2623# define R200_VC_NO_SWAP(0 << 0)
2624# define R200_VC_16BIT_SWAP(1 << 0)
2625# define R200_VC_32BIT_SWAP(2 << 0)
2626#define R200_RE_AUX_SCISSOR_CNTL0x26f0
2627# define R200_EXCLUSIVE_SCISSOR_00x01000000
2628# define R200_EXCLUSIVE_SCISSOR_10x02000000
2629# define R200_EXCLUSIVE_SCISSOR_20x04000000
2630# define R200_SCISSOR_ENABLE_00x10000000
2631# define R200_SCISSOR_ENABLE_10x20000000
2632# define R200_SCISSOR_ENABLE_20x40000000
2633#define R200_PP_TXFILTER_00x2c00
2634#define R200_PP_TXFILTER_10x2c20
2635#define R200_PP_TXFILTER_20x2c40
2636#define R200_PP_TXFILTER_30x2c60
2637#define R200_PP_TXFILTER_40x2c80
2638#define R200_PP_TXFILTER_50x2ca0
2639# define R200_MAG_FILTER_NEAREST(0 << 0)
2640# define R200_MAG_FILTER_LINEAR(1 << 0)
2641# define R200_MAG_FILTER_MASK(1 << 0)
2642# define R200_MIN_FILTER_NEAREST(0 << 1)
2643# define R200_MIN_FILTER_LINEAR(1 << 1)
2644# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)
2645# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)
2646# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)
2647# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)
2648# define R200_MIN_FILTER_ANISO_NEAREST(8 << 1)
2649# define R200_MIN_FILTER_ANISO_LINEAR(9 << 1)
2650# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)
2651# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)
2652# define R200_MIN_FILTER_MASK(15 << 1)
2653# define R200_MAX_ANISO_1_TO_1(0 << 5)
2654# define R200_MAX_ANISO_2_TO_1(1 << 5)
2655# define R200_MAX_ANISO_4_TO_1(2 << 5)
2656# define R200_MAX_ANISO_8_TO_1(3 << 5)
2657# define R200_MAX_ANISO_16_TO_1(4 << 5)
2658# define R200_MAX_ANISO_MASK(7 << 5)
2659# define R200_MAX_MIP_LEVEL_MASK(0x0f << 16)
2660# define R200_MAX_MIP_LEVEL_SHIFT16
2661# define R200_YUV_TO_RGB(1 << 20)
2662# define R200_YUV_TEMPERATURE_COOL(0 << 21)
2663# define R200_YUV_TEMPERATURE_HOT(1 << 21)
2664# define R200_YUV_TEMPERATURE_MASK(1 << 21)
2665# define R200_WRAPEN_S(1 << 22)
2666# define R200_CLAMP_S_WRAP(0 << 23)
2667# define R200_CLAMP_S_MIRROR(1 << 23)
2668# define R200_CLAMP_S_CLAMP_LAST(2 << 23)
2669# define R200_CLAMP_S_MIRROR_CLAMP_LAST(3 << 23)
2670# define R200_CLAMP_S_CLAMP_BORDER(4 << 23)
2671# define R200_CLAMP_S_MIRROR_CLAMP_BORDER(5 << 23)
2672# define R200_CLAMP_S_CLAMP_GL(6 << 23)
2673# define R200_CLAMP_S_MIRROR_CLAMP_GL(7 << 23)
2674# define R200_CLAMP_S_MASK(7 << 23)
2675# define R200_WRAPEN_T(1 << 26)
2676# define R200_CLAMP_T_WRAP(0 << 27)
2677# define R200_CLAMP_T_MIRROR(1 << 27)
2678# define R200_CLAMP_T_CLAMP_LAST(2 << 27)
2679# define R200_CLAMP_T_MIRROR_CLAMP_LAST(3 << 27)
2680# define R200_CLAMP_T_CLAMP_BORDER(4 << 27)
2681# define R200_CLAMP_T_MIRROR_CLAMP_BORDER(5 << 27)
2682# define R200_CLAMP_T_CLAMP_GL(6 << 27)
2683# define R200_CLAMP_T_MIRROR_CLAMP_GL(7 << 27)
2684# define R200_CLAMP_T_MASK(7 << 27)
2685# define R200_KILL_LT_ZERO(1 << 30)
2686# define R200_BORDER_MODE_OGL(0 << 31)
2687# define R200_BORDER_MODE_D3D(1 << 31)
2688#define R200_PP_TXFORMAT_00x2c04
2689#define R200_PP_TXFORMAT_10x2c24
2690#define R200_PP_TXFORMAT_20x2c44
2691#define R200_PP_TXFORMAT_30x2c64
2692#define R200_PP_TXFORMAT_40x2c84
2693#define R200_PP_TXFORMAT_50x2ca4
2694# define R200_TXFORMAT_I8(0 << 0)
2695# define R200_TXFORMAT_AI88(1 << 0)
2696# define R200_TXFORMAT_RGB332(2 << 0)
2697# define R200_TXFORMAT_ARGB1555(3 << 0)
2698# define R200_TXFORMAT_RGB565(4 << 0)
2699# define R200_TXFORMAT_ARGB4444(5 << 0)
2700# define R200_TXFORMAT_ARGB8888(6 << 0)
2701# define R200_TXFORMAT_RGBA8888(7 << 0)
2702# define R200_TXFORMAT_Y8(8 << 0)
2703# define R200_TXFORMAT_AVYU4444(9 << 0)
2704# define R200_TXFORMAT_VYUY422(10 << 0)
2705# define R200_TXFORMAT_YVYU422(11 << 0)
2706# define R200_TXFORMAT_DXT1(12 << 0)
2707# define R200_TXFORMAT_DXT23(14 << 0)
2708# define R200_TXFORMAT_DXT45(15 << 0)
2709# define R200_TXFORMAT_ABGR8888(22 << 0)
2710# define R200_TXFORMAT_FORMAT_MASK(31 <<0)
2711# define R200_TXFORMAT_FORMAT_SHIFT0
2712# define R200_TXFORMAT_ALPHA_IN_MAP(1 << 6)
2713# define R200_TXFORMAT_NON_POWER2(1 << 7)
2714# define R200_TXFORMAT_WIDTH_MASK(15 <<8)
2715# define R200_TXFORMAT_WIDTH_SHIFT8
2716# define R200_TXFORMAT_HEIGHT_MASK(15 << 12)
2717# define R200_TXFORMAT_HEIGHT_SHIFT12
2718# define R200_TXFORMAT_F5_WIDTH_MASK(15 << 16)/* cube face 5 */
2719# define R200_TXFORMAT_F5_WIDTH_SHIFT16
2720# define R200_TXFORMAT_F5_HEIGHT_MASK(15 << 20)
2721# define R200_TXFORMAT_F5_HEIGHT_SHIFT20
2722# define R200_TXFORMAT_ST_ROUTE_STQ0(0 << 24)
2723# define R200_TXFORMAT_ST_ROUTE_STQ1(1 << 24)
2724# define R200_TXFORMAT_ST_ROUTE_STQ2(2 << 24)
2725# define R200_TXFORMAT_ST_ROUTE_STQ3(3 << 24)
2726# define R200_TXFORMAT_ST_ROUTE_STQ4(4 << 24)
2727# define R200_TXFORMAT_ST_ROUTE_STQ5(5 << 24)
2728# define R200_TXFORMAT_ST_ROUTE_MASK(7 << 24)
2729# define R200_TXFORMAT_ST_ROUTE_SHIFT24
2730# define R200_TXFORMAT_ALPHA_MASK_ENABLE(1 << 28)
2731# define R200_TXFORMAT_CHROMA_KEY_ENABLE(1 << 29)
2732# define R200_TXFORMAT_CUBIC_MAP_ENABLE(1 << 30)
2733#define R200_PP_TXFORMAT_X_0 0x2c08
2734#define R200_PP_TXFORMAT_X_1 0x2c28
2735#define R200_PP_TXFORMAT_X_2 0x2c48
2736#define R200_PP_TXFORMAT_X_3 0x2c68
2737#define R200_PP_TXFORMAT_X_4 0x2c88
2738#define R200_PP_TXFORMAT_X_5 0x2ca8
2739
2740#define R200_PP_TXSIZE_00x2c0c /* NPOT only */
2741#define R200_PP_TXSIZE_10x2c2c /* NPOT only */
2742#define R200_PP_TXSIZE_20x2c4c /* NPOT only */
2743#define R200_PP_TXSIZE_30x2c6c /* NPOT only */
2744#define R200_PP_TXSIZE_40x2c8c /* NPOT only */
2745#define R200_PP_TXSIZE_50x2cac /* NPOT only */
2746
2747#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */
2748#define R200_PP_TXPITCH_10x2c30 /* NPOT only */
2749#define R200_PP_TXPITCH_20x2c50 /* NPOT only */
2750#define R200_PP_TXPITCH_30x2c70 /* NPOT only */
2751#define R200_PP_TXPITCH_40x2c90 /* NPOT only */
2752#define R200_PP_TXPITCH_50x2cb0 /* NPOT only */
2753
2754#define R200_PP_TXOFFSET_00x2d00
2755# define R200_TXO_ENDIAN_NO_SWAP(0 << 0)
2756# define R200_TXO_ENDIAN_BYTE_SWAP(1 << 0)
2757# define R200_TXO_ENDIAN_WORD_SWAP(2 << 0)
2758# define R200_TXO_ENDIAN_HALFDW_SWAP(3 << 0)
2759# define R200_TXO_MACRO_LINEAR(0 << 2)
2760# define R200_TXO_MACRO_TILE(1 << 2)
2761# define R200_TXO_MICRO_LINEAR(0 << 3)
2762# define R200_TXO_MICRO_TILE(1 << 3)
2763# define R200_TXO_OFFSET_MASK0xffffffe0
2764# define R200_TXO_OFFSET_SHIFT5
2765#define R200_PP_TXOFFSET_10x2d18
2766#define R200_PP_TXOFFSET_20x2d30
2767#define R200_PP_TXOFFSET_30x2d48
2768#define R200_PP_TXOFFSET_40x2d60
2769#define R200_PP_TXOFFSET_50x2d78
2770
2771#define R200_PP_TFACTOR_00x2ee0
2772#define R200_PP_TFACTOR_10x2ee4
2773#define R200_PP_TFACTOR_20x2ee8
2774#define R200_PP_TFACTOR_30x2eec
2775#define R200_PP_TFACTOR_40x2ef0
2776#define R200_PP_TFACTOR_50x2ef4
2777
2778#define R200_PP_TXCBLEND_00x2f00
2779# define R200_TXC_ARG_A_ZERO(0)
2780# define R200_TXC_ARG_A_CURRENT_COLOR(2)
2781# define R200_TXC_ARG_A_CURRENT_ALPHA(3)
2782# define R200_TXC_ARG_A_DIFFUSE_COLOR(4)
2783# define R200_TXC_ARG_A_DIFFUSE_ALPHA(5)
2784# define R200_TXC_ARG_A_SPECULAR_COLOR(6)
2785# define R200_TXC_ARG_A_SPECULAR_ALPHA(7)
2786# define R200_TXC_ARG_A_TFACTOR_COLOR(8)
2787# define R200_TXC_ARG_A_TFACTOR_ALPHA(9)
2788# define R200_TXC_ARG_A_R0_COLOR(10)
2789# define R200_TXC_ARG_A_R0_ALPHA(11)
2790# define R200_TXC_ARG_A_R1_COLOR(12)
2791# define R200_TXC_ARG_A_R1_ALPHA(13)
2792# define R200_TXC_ARG_A_R2_COLOR(14)
2793# define R200_TXC_ARG_A_R2_ALPHA(15)
2794# define R200_TXC_ARG_A_R3_COLOR(16)
2795# define R200_TXC_ARG_A_R3_ALPHA(17)
2796# define R200_TXC_ARG_A_R4_COLOR(18)
2797# define R200_TXC_ARG_A_R4_ALPHA(19)
2798# define R200_TXC_ARG_A_R5_COLOR(20)
2799# define R200_TXC_ARG_A_R5_ALPHA(21)
2800# define R200_TXC_ARG_A_TFACTOR1_COLOR(26)
2801# define R200_TXC_ARG_A_TFACTOR1_ALPHA(27)
2802# define R200_TXC_ARG_A_MASK(31 << 0)
2803# define R200_TXC_ARG_A_SHIFT0
2804# define R200_TXC_ARG_B_ZERO(0 << 5)
2805# define R200_TXC_ARG_B_CURRENT_COLOR(2 << 5)
2806# define R200_TXC_ARG_B_CURRENT_ALPHA(3 << 5)
2807# define R200_TXC_ARG_B_DIFFUSE_COLOR(4 << 5)
2808# define R200_TXC_ARG_B_DIFFUSE_ALPHA(5 << 5)
2809# define R200_TXC_ARG_B_SPECULAR_COLOR(6 << 5)
2810# define R200_TXC_ARG_B_SPECULAR_ALPHA(7 << 5)
2811# define R200_TXC_ARG_B_TFACTOR_COLOR(8 << 5)
2812# define R200_TXC_ARG_B_TFACTOR_ALPHA(9 << 5)
2813# define R200_TXC_ARG_B_R0_COLOR(10 << 5)
2814# define R200_TXC_ARG_B_R0_ALPHA(11 << 5)
2815# define R200_TXC_ARG_B_R1_COLOR(12 << 5)
2816# define R200_TXC_ARG_B_R1_ALPHA(13 << 5)
2817# define R200_TXC_ARG_B_R2_COLOR(14 << 5)
2818# define R200_TXC_ARG_B_R2_ALPHA(15 << 5)
2819# define R200_TXC_ARG_B_R3_COLOR(16 << 5)
2820# define R200_TXC_ARG_B_R3_ALPHA(17 << 5)
2821# define R200_TXC_ARG_B_R4_COLOR(18 << 5)
2822# define R200_TXC_ARG_B_R4_ALPHA(19 << 5)
2823# define R200_TXC_ARG_B_R5_COLOR(20 << 5)
2824# define R200_TXC_ARG_B_R5_ALPHA(21 << 5)
2825# define R200_TXC_ARG_B_TFACTOR1_COLOR(26 << 5)
2826# define R200_TXC_ARG_B_TFACTOR1_ALPHA(27 << 5)
2827# define R200_TXC_ARG_B_MASK(31 << 5)
2828# define R200_TXC_ARG_B_SHIFT5
2829# define R200_TXC_ARG_C_ZERO(0 << 10)
2830# define R200_TXC_ARG_C_CURRENT_COLOR(2 << 10)
2831# define R200_TXC_ARG_C_CURRENT_ALPHA(3 << 10)
2832# define R200_TXC_ARG_C_DIFFUSE_COLOR(4 << 10)
2833# define R200_TXC_ARG_C_DIFFUSE_ALPHA(5 << 10)
2834# define R200_TXC_ARG_C_SPECULAR_COLOR(6 << 10)
2835# define R200_TXC_ARG_C_SPECULAR_ALPHA(7 << 10)
2836# define R200_TXC_ARG_C_TFACTOR_COLOR(8 << 10)
2837# define R200_TXC_ARG_C_TFACTOR_ALPHA(9 << 10)
2838# define R200_TXC_ARG_C_R0_COLOR(10 << 10)
2839# define R200_TXC_ARG_C_R0_ALPHA(11 << 10)
2840# define R200_TXC_ARG_C_R1_COLOR(12 << 10)
2841# define R200_TXC_ARG_C_R1_ALPHA(13 << 10)
2842# define R200_TXC_ARG_C_R2_COLOR(14 << 10)
2843# define R200_TXC_ARG_C_R2_ALPHA(15 << 10)
2844# define R200_TXC_ARG_C_R3_COLOR(16 << 10)
2845# define R200_TXC_ARG_C_R3_ALPHA(17 << 10)
2846# define R200_TXC_ARG_C_R4_COLOR(18 << 10)
2847# define R200_TXC_ARG_C_R4_ALPHA(19 << 10)
2848# define R200_TXC_ARG_C_R5_COLOR(20 << 10)
2849# define R200_TXC_ARG_C_R5_ALPHA(21 << 10)
2850# define R200_TXC_ARG_C_TFACTOR1_COLOR(26 << 10)
2851# define R200_TXC_ARG_C_TFACTOR1_ALPHA(27 << 10)
2852# define R200_TXC_ARG_C_MASK(31 << 10)
2853# define R200_TXC_ARG_C_SHIFT10
2854# define R200_TXC_COMP_ARG_A(1 << 16)
2855# define R200_TXC_COMP_ARG_A_SHIFT(16)
2856# define R200_TXC_BIAS_ARG_A(1 << 17)
2857# define R200_TXC_SCALE_ARG_A(1 << 18)
2858# define R200_TXC_NEG_ARG_A(1 << 19)
2859# define R200_TXC_COMP_ARG_B(1 << 20)
2860# define R200_TXC_COMP_ARG_B_SHIFT(20)
2861# define R200_TXC_BIAS_ARG_B(1 << 21)
2862# define R200_TXC_SCALE_ARG_B(1 << 22)
2863# define R200_TXC_NEG_ARG_B(1 << 23)
2864# define R200_TXC_COMP_ARG_C(1 << 24)
2865# define R200_TXC_COMP_ARG_C_SHIFT(24)
2866# define R200_TXC_BIAS_ARG_C(1 << 25)
2867# define R200_TXC_SCALE_ARG_C(1 << 26)
2868# define R200_TXC_NEG_ARG_C(1 << 27)
2869# define R200_TXC_OP_MADD(0 << 28)
2870# define R200_TXC_OP_CND0(2 << 28)
2871# define R200_TXC_OP_LERP(3 << 28)
2872# define R200_TXC_OP_DOT3(4 << 28)
2873# define R200_TXC_OP_DOT4(5 << 28)
2874# define R200_TXC_OP_CONDITIONAL(6 << 28)
2875# define R200_TXC_OP_DOT2_ADD(7 << 28)
2876# define R200_TXC_OP_MASK(7 << 28)
2877#define R200_PP_TXCBLEND2_00x2f04
2878# define R200_TXC_TFACTOR_SEL_SHIFT0
2879# define R200_TXC_TFACTOR_SEL_MASK0x7
2880# define R200_TXC_TFACTOR1_SEL_SHIFT4
2881# define R200_TXC_TFACTOR1_SEL_MASK(0x7 << 4)
2882# define R200_TXC_SCALE_SHIFT8
2883# define R200_TXC_SCALE_MASK(7 << 8)
2884# define R200_TXC_SCALE_1X(0 << 8)
2885# define R200_TXC_SCALE_2X(1 << 8)
2886# define R200_TXC_SCALE_4X(2 << 8)
2887# define R200_TXC_SCALE_8X(3 << 8)
2888# define R200_TXC_SCALE_INV2(5 << 8)
2889# define R200_TXC_SCALE_INV4(6 << 8)
2890# define R200_TXC_SCALE_INV8(7 << 8)
2891# define R200_TXC_CLAMP_SHIFT12
2892# define R200_TXC_CLAMP_MASK(3 << 12)
2893# define R200_TXC_CLAMP_WRAP(0 << 12)
2894# define R200_TXC_CLAMP_0_1(1 << 12)
2895# define R200_TXC_CLAMP_8_8(2 << 12)
2896# define R200_TXC_OUTPUT_REG_MASK(7 << 16)
2897# define R200_TXC_OUTPUT_REG_NONE(0 << 16)
2898# define R200_TXC_OUTPUT_REG_R0(1 << 16)
2899# define R200_TXC_OUTPUT_REG_R1(2 << 16)
2900# define R200_TXC_OUTPUT_REG_R2(3 << 16)
2901# define R200_TXC_OUTPUT_REG_R3(4 << 16)
2902# define R200_TXC_OUTPUT_REG_R4(5 << 16)
2903# define R200_TXC_OUTPUT_REG_R5(6 << 16)
2904# define R200_TXC_OUTPUT_MASK_MASK(7 << 20)
2905# define R200_TXC_OUTPUT_MASK_RGB(0 << 20)
2906# define R200_TXC_OUTPUT_MASK_RG(1 << 20)
2907# define R200_TXC_OUTPUT_MASK_RB(2 << 20)
2908# define R200_TXC_OUTPUT_MASK_R(3 << 20)
2909# define R200_TXC_OUTPUT_MASK_GB(4 << 20)
2910# define R200_TXC_OUTPUT_MASK_G(5 << 20)
2911# define R200_TXC_OUTPUT_MASK_B(6 << 20)
2912# define R200_TXC_OUTPUT_MASK_NONE(7 << 20)
2913# define R200_TXC_REPL_NORMAL0
2914# define R200_TXC_REPL_RED1
2915# define R200_TXC_REPL_GREEN2
2916# define R200_TXC_REPL_BLUE3
2917# define R200_TXC_REPL_ARG_A_SHIFT26
2918# define R200_TXC_REPL_ARG_A_MASK(3 << 26)
2919# define R200_TXC_REPL_ARG_B_SHIFT28
2920# define R200_TXC_REPL_ARG_B_MASK(3 << 28)
2921# define R200_TXC_REPL_ARG_C_SHIFT30
2922# define R200_TXC_REPL_ARG_C_MASK(3 << 30)
2923#define R200_PP_TXABLEND_00x2f08
2924# define R200_TXA_ARG_A_ZERO(0)
2925# define R200_TXA_ARG_A_CURRENT_ALPHA(2) /* guess */
2926# define R200_TXA_ARG_A_CURRENT_BLUE(3) /* guess */
2927# define R200_TXA_ARG_A_DIFFUSE_ALPHA(4)
2928# define R200_TXA_ARG_A_DIFFUSE_BLUE(5)
2929# define R200_TXA_ARG_A_SPECULAR_ALPHA(6)
2930# define R200_TXA_ARG_A_SPECULAR_BLUE(7)
2931# define R200_TXA_ARG_A_TFACTOR_ALPHA(8)
2932# define R200_TXA_ARG_A_TFACTOR_BLUE(9)
2933# define R200_TXA_ARG_A_R0_ALPHA(10)
2934# define R200_TXA_ARG_A_R0_BLUE(11)
2935# define R200_TXA_ARG_A_R1_ALPHA(12)
2936# define R200_TXA_ARG_A_R1_BLUE(13)
2937# define R200_TXA_ARG_A_R2_ALPHA(14)
2938# define R200_TXA_ARG_A_R2_BLUE(15)
2939# define R200_TXA_ARG_A_R3_ALPHA(16)
2940# define R200_TXA_ARG_A_R3_BLUE(17)
2941# define R200_TXA_ARG_A_R4_ALPHA(18)
2942# define R200_TXA_ARG_A_R4_BLUE(19)
2943# define R200_TXA_ARG_A_R5_ALPHA(20)
2944# define R200_TXA_ARG_A_R5_BLUE(21)
2945# define R200_TXA_ARG_A_TFACTOR1_ALPHA(26)
2946# define R200_TXA_ARG_A_TFACTOR1_BLUE(27)
2947# define R200_TXA_ARG_A_MASK(31 << 0)
2948# define R200_TXA_ARG_A_SHIFT0
2949# define R200_TXA_ARG_B_ZERO(0 << 5)
2950# define R200_TXA_ARG_B_CURRENT_ALPHA(2 << 5) /* guess */
2951# define R200_TXA_ARG_B_CURRENT_BLUE(3 << 5) /* guess */
2952# define R200_TXA_ARG_B_DIFFUSE_ALPHA(4 << 5)
2953# define R200_TXA_ARG_B_DIFFUSE_BLUE(5 << 5)
2954# define R200_TXA_ARG_B_SPECULAR_ALPHA(6 << 5)
2955# define R200_TXA_ARG_B_SPECULAR_BLUE(7 << 5)
2956# define R200_TXA_ARG_B_TFACTOR_ALPHA(8 << 5)
2957# define R200_TXA_ARG_B_TFACTOR_BLUE(9 << 5)
2958# define R200_TXA_ARG_B_R0_ALPHA(10 << 5)
2959# define R200_TXA_ARG_B_R0_BLUE(11 << 5)
2960# define R200_TXA_ARG_B_R1_ALPHA(12 << 5)
2961# define R200_TXA_ARG_B_R1_BLUE(13 << 5)
2962# define R200_TXA_ARG_B_R2_ALPHA(14 << 5)
2963# define R200_TXA_ARG_B_R2_BLUE(15 << 5)
2964# define R200_TXA_ARG_B_R3_ALPHA(16 << 5)
2965# define R200_TXA_ARG_B_R3_BLUE(17 << 5)
2966# define R200_TXA_ARG_B_R4_ALPHA(18 << 5)
2967# define R200_TXA_ARG_B_R4_BLUE(19 << 5)
2968# define R200_TXA_ARG_B_R5_ALPHA(20 << 5)
2969# define R200_TXA_ARG_B_R5_BLUE(21 << 5)
2970# define R200_TXA_ARG_B_TFACTOR1_ALPHA(26 << 5)
2971# define R200_TXA_ARG_B_TFACTOR1_BLUE(27 << 5)
2972# define R200_TXA_ARG_B_MASK(31 << 5)
2973# define R200_TXA_ARG_B_SHIFT5
2974# define R200_TXA_ARG_C_ZERO(0 << 10)
2975# define R200_TXA_ARG_C_CURRENT_ALPHA(2 << 10) /* guess */
2976# define R200_TXA_ARG_C_CURRENT_BLUE(3 << 10) /* guess */
2977# define R200_TXA_ARG_C_DIFFUSE_ALPHA(4 << 10)
2978# define R200_TXA_ARG_C_DIFFUSE_BLUE(5 << 10)
2979# define R200_TXA_ARG_C_SPECULAR_ALPHA(6 << 10)
2980# define R200_TXA_ARG_C_SPECULAR_BLUE(7 << 10)
2981# define R200_TXA_ARG_C_TFACTOR_ALPHA(8 << 10)
2982# define R200_TXA_ARG_C_TFACTOR_BLUE(9 << 10)
2983# define R200_TXA_ARG_C_R0_ALPHA(10 << 10)
2984# define R200_TXA_ARG_C_R0_BLUE(11 << 10)
2985# define R200_TXA_ARG_C_R1_ALPHA(12 << 10)
2986# define R200_TXA_ARG_C_R1_BLUE(13 << 10)
2987# define R200_TXA_ARG_C_R2_ALPHA(14 << 10)
2988# define R200_TXA_ARG_C_R2_BLUE(15 << 10)
2989# define R200_TXA_ARG_C_R3_ALPHA(16 << 10)
2990# define R200_TXA_ARG_C_R3_BLUE(17 << 10)
2991# define R200_TXA_ARG_C_R4_ALPHA(18 << 10)
2992# define R200_TXA_ARG_C_R4_BLUE(19 << 10)
2993# define R200_TXA_ARG_C_R5_ALPHA(20 << 10)
2994# define R200_TXA_ARG_C_R5_BLUE(21 << 10)
2995# define R200_TXA_ARG_C_TFACTOR1_ALPHA(26 << 10)
2996# define R200_TXA_ARG_C_TFACTOR1_BLUE(27 << 10)
2997# define R200_TXA_ARG_C_MASK(31 << 10)
2998# define R200_TXA_ARG_C_SHIFT10
2999# define R200_TXA_COMP_ARG_A(1 << 16)
3000# define R200_TXA_COMP_ARG_A_SHIFT(16)
3001# define R200_TXA_BIAS_ARG_A(1 << 17)
3002# define R200_TXA_SCALE_ARG_A(1 << 18)
3003# define R200_TXA_NEG_ARG_A(1 << 19)
3004# define R200_TXA_COMP_ARG_B(1 << 20)
3005# define R200_TXA_COMP_ARG_B_SHIFT(20)
3006# define R200_TXA_BIAS_ARG_B(1 << 21)
3007# define R200_TXA_SCALE_ARG_B(1 << 22)
3008# define R200_TXA_NEG_ARG_B(1 << 23)
3009# define R200_TXA_COMP_ARG_C(1 << 24)
3010# define R200_TXA_COMP_ARG_C_SHIFT(24)
3011# define R200_TXA_BIAS_ARG_C(1 << 25)
3012# define R200_TXA_SCALE_ARG_C(1 << 26)
3013# define R200_TXA_NEG_ARG_C(1 << 27)
3014# define R200_TXA_OP_MADD(0 << 28)
3015# define R200_TXA_OP_CND0(2 << 28)
3016# define R200_TXA_OP_LERP(3 << 28)
3017# define R200_TXA_OP_CONDITIONAL(6 << 28)
3018# define R200_TXA_OP_MASK(7 << 28)
3019#define R200_PP_TXABLEND2_00x2f0c
3020# define R200_TXA_TFACTOR_SEL_SHIFT0
3021# define R200_TXA_TFACTOR_SEL_MASK0x7
3022# define R200_TXA_TFACTOR1_SEL_SHIFT4
3023# define R200_TXA_TFACTOR1_SEL_MASK(0x7 << 4)
3024# define R200_TXA_SCALE_SHIFT8
3025# define R200_TXA_SCALE_MASK(7 << 8)
3026# define R200_TXA_SCALE_1X(0 << 8)
3027# define R200_TXA_SCALE_2X(1 << 8)
3028# define R200_TXA_SCALE_4X(2 << 8)
3029# define R200_TXA_SCALE_8X(3 << 8)
3030# define R200_TXA_SCALE_INV2(5 << 8)
3031# define R200_TXA_SCALE_INV4(6 << 8)
3032# define R200_TXA_SCALE_INV8(7 << 8)
3033# define R200_TXA_CLAMP_SHIFT12
3034# define R200_TXA_CLAMP_MASK(3 << 12)
3035# define R200_TXA_CLAMP_WRAP(0 << 12)
3036# define R200_TXA_CLAMP_0_1(1 << 12)
3037# define R200_TXA_CLAMP_8_8(2 << 12)
3038# define R200_TXA_OUTPUT_REG_MASK(7 << 16)
3039# define R200_TXA_OUTPUT_REG_NONE(0 << 16)
3040# define R200_TXA_OUTPUT_REG_R0(1 << 16)
3041# define R200_TXA_OUTPUT_REG_R1(2 << 16)
3042# define R200_TXA_OUTPUT_REG_R2(3 << 16)
3043# define R200_TXA_OUTPUT_REG_R3(4 << 16)
3044# define R200_TXA_OUTPUT_REG_R4(5 << 16)
3045# define R200_TXA_OUTPUT_REG_R5(6 << 16)
3046# define R200_TXA_DOT_ALPHA(1 << 20)
3047# define R200_TXA_REPL_NORMAL0
3048# define R200_TXA_REPL_RED1
3049# define R200_TXA_REPL_GREEN2
3050# define R200_TXA_REPL_ARG_A_SHIFT26
3051# define R200_TXA_REPL_ARG_A_MASK(3 << 26)
3052# define R200_TXA_REPL_ARG_B_SHIFT28
3053# define R200_TXA_REPL_ARG_B_MASK(3 << 28)
3054# define R200_TXA_REPL_ARG_C_SHIFT30
3055# define R200_TXA_REPL_ARG_C_MASK(3 << 30)
3056#define R200_PP_TXCBLEND_10x2f10
3057#define R200_PP_TXCBLEND2_10x2f14
3058#define R200_PP_TXABLEND_10x2f18
3059#define R200_PP_TXABLEND2_10x2f1c
3060#define R200_PP_TXCBLEND_20x2f20
3061#define R200_PP_TXCBLEND2_20x2f24
3062#define R200_PP_TXABLEND_20x2f28
3063#define R200_PP_TXABLEND2_20x2f2c
3064#define R200_PP_TXCBLEND_30x2f30
3065#define R200_PP_TXCBLEND2_30x2f34
3066#define R200_PP_TXABLEND_30x2f38
3067#define R200_PP_TXABLEND2_30x2f3c
3068
3069#define R200_SE_VTX_FMT_00x2088
3070# define R200_VTX_XY0 /* always have xy */
3071# define R200_VTX_Z0(1<<0)
3072# define R200_VTX_W0(1<<1)
3073# define R200_VTX_WEIGHT_COUNT_SHIFT(2)
3074# define R200_VTX_PV_MATRIX_SEL(1<<5)
3075# define R200_VTX_N0(1<<6)
3076# define R200_VTX_POINT_SIZE(1<<7)
3077# define R200_VTX_DISCRETE_FOG(1<<8)
3078# define R200_VTX_SHININESS_0(1<<9)
3079# define R200_VTX_SHININESS_1(1<<10)
3080# define R200_VTX_COLOR_NOT_PRESENT0
3081# define R200_VTX_PK_RGBA1
3082# define R200_VTX_FP_RGB2
3083# define R200_VTX_FP_RGBA3
3084# define R200_VTX_COLOR_MASK3
3085# define R200_VTX_COLOR_0_SHIFT11
3086# define R200_VTX_COLOR_1_SHIFT13
3087# define R200_VTX_COLOR_2_SHIFT15
3088# define R200_VTX_COLOR_3_SHIFT17
3089# define R200_VTX_COLOR_4_SHIFT19
3090# define R200_VTX_COLOR_5_SHIFT21
3091# define R200_VTX_COLOR_6_SHIFT23
3092# define R200_VTX_COLOR_7_SHIFT25
3093# define R200_VTX_XY1(1<<28)
3094# define R200_VTX_Z1(1<<29)
3095# define R200_VTX_W1(1<<30)
3096# define R200_VTX_N1(1<<31)
3097#define R200_SE_VTX_FMT_10x208c
3098# define R200_VTX_TEX0_COMP_CNT_SHIFT0
3099# define R200_VTX_TEX1_COMP_CNT_SHIFT3
3100# define R200_VTX_TEX2_COMP_CNT_SHIFT6
3101# define R200_VTX_TEX3_COMP_CNT_SHIFT9
3102# define R200_VTX_TEX4_COMP_CNT_SHIFT12
3103# define R200_VTX_TEX5_COMP_CNT_SHIFT15
3104
3105#define R200_SE_TCL_OUTPUT_VTX_FMT_00x2090
3106#define R200_SE_TCL_OUTPUT_VTX_FMT_10x2094
3107#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL0x2250
3108# define R200_OUTPUT_XYZW(1<<0)
3109# define R200_OUTPUT_COLOR_0(1<<8)
3110# define R200_OUTPUT_COLOR_1(1<<9)
3111# define R200_OUTPUT_TEX_0(1<<16)
3112# define R200_OUTPUT_TEX_1(1<<17)
3113# define R200_OUTPUT_TEX_2(1<<18)
3114# define R200_OUTPUT_TEX_3(1<<19)
3115# define R200_OUTPUT_TEX_4(1<<20)
3116# define R200_OUTPUT_TEX_5(1<<21)
3117# define R200_OUTPUT_TEX_MASK(0x3f<<16)
3118# define R200_OUTPUT_DISCRETE_FOG(1<<24)
3119# define R200_OUTPUT_PT_SIZE(1<<25)
3120# define R200_FORCE_INORDER_PROC(1<<31)
3121#define R200_PP_CNTL_X0x2cc4
3122#define R200_PP_TXMULTI_CTL_00x2c1c
3123#define R200_SE_VTX_STATE_CNTL0x2180
3124# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)
3125
3126/* Registers for CP and Microcode Engine */
3127#define RADEON_CP_ME_RAM_ADDR 0x07d4
3128#define RADEON_CP_ME_RAM_RADDR 0x07d8
3129#define RADEON_CP_ME_RAM_DATAH 0x07dc
3130#define RADEON_CP_ME_RAM_DATAL 0x07e0
3131
3132#define RADEON_CP_RB_BASE 0x0700
3133#define RADEON_CP_RB_CNTL 0x0704
3134#define RADEON_CP_RB_RPTR_ADDR 0x070c
3135#define RADEON_CP_RB_RPTR 0x0710
3136#define RADEON_CP_RB_WPTR 0x0714
3137
3138#define RADEON_CP_IB_BASE 0x0738
3139#define RADEON_CP_IB_BUFSZ 0x073c
3140
3141#define RADEON_CP_CSQ_CNTL 0x0740
3142# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
3143# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
3144# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
3145# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
3146# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
3147# define RADEON_CSQ_PRIBM_INDBM (4 << 28)
3148# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
3149#define RADEON_CP_CSQ_STAT 0x07f8
3150# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)
3151# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)
3152# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)
3153# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)
3154#define RADEON_CP_CSQ_ADDR 0x07f0
3155#define RADEON_CP_CSQ_DATA 0x07f4
3156#define RADEON_CP_CSQ_APER_PRIMARY 0x1000
3157#define RADEON_CP_CSQ_APER_INDIRECT 0x1300
3158
3159#define RADEON_CP_RB_WPTR_DELAY 0x0718
3160# define RADEON_PRE_WRITE_TIMER_SHIFT 0
3161# define RADEON_PRE_WRITE_LIMIT_SHIFT 23
3162
3163#define RADEON_AIC_CNTL 0x01d0
3164# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
3165#define RADEON_AIC_LO_ADDR 0x01dc
3166
3167
3168
3169/* Constants */
3170#define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0
3171#define RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2
3172
3173
3174
3175/* CP packet types */
3176#define RADEON_CP_PACKET0 0x00000000
3177#define RADEON_CP_PACKET1 0x40000000
3178#define RADEON_CP_PACKET2 0x80000000
3179#define RADEON_CP_PACKET3 0xC0000000
3180# define RADEON_CP_PACKET_MASK 0xC0000000
3181# define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
3182# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)
3183# define RADEON_CP_PACKET0_REG_MASK 0x000007ff
3184# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
3185# define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
3186
3187#define RADEON_CP_PACKET0_ONE_REG_WR 0x00008000
3188
3189#define RADEON_CP_PACKET3_NOP 0xC0001000
3190#define RADEON_CP_PACKET3_NEXT_CHAR 0xC0001900
3191#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D00
3192#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E00
3193#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300
3194#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC0002400
3195#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC0002600
3196#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC0002800
3197#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC0002900
3198#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A00
3199#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C00
3200#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500
3201#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00
3202#define RADEON_CP_PACKET3_CNTL_PAINT 0xC0009100
3203#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC0009200
3204#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC0009300
3205#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400
3206#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC0009500
3207#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800
3208#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00
3209#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00
3210#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00
3211
3212
3213#define RADEON_CP_VC_FRMT_XY 0x00000000
3214#define RADEON_CP_VC_FRMT_W0 0x00000001
3215#define RADEON_CP_VC_FRMT_FPCOLOR 0x00000002
3216#define RADEON_CP_VC_FRMT_FPALPHA 0x00000004
3217#define RADEON_CP_VC_FRMT_PKCOLOR 0x00000008
3218#define RADEON_CP_VC_FRMT_FPSPEC 0x00000010
3219#define RADEON_CP_VC_FRMT_FPFOG 0x00000020
3220#define RADEON_CP_VC_FRMT_PKSPEC 0x00000040
3221#define RADEON_CP_VC_FRMT_ST0 0x00000080
3222#define RADEON_CP_VC_FRMT_ST1 0x00000100
3223#define RADEON_CP_VC_FRMT_Q1 0x00000200
3224#define RADEON_CP_VC_FRMT_ST2 0x00000400
3225#define RADEON_CP_VC_FRMT_Q2 0x00000800
3226#define RADEON_CP_VC_FRMT_ST3 0x00001000
3227#define RADEON_CP_VC_FRMT_Q3 0x00002000
3228#define RADEON_CP_VC_FRMT_Q0 0x00004000
3229#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000
3230#define RADEON_CP_VC_FRMT_N0 0x00040000
3231#define RADEON_CP_VC_FRMT_XY1 0x08000000
3232#define RADEON_CP_VC_FRMT_Z1 0x10000000
3233#define RADEON_CP_VC_FRMT_W1 0x20000000
3234#define RADEON_CP_VC_FRMT_N1 0x40000000
3235#define RADEON_CP_VC_FRMT_Z 0x80000000
3236
3237#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000
3238#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001
3239#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002
3240#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003
3241#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
3242#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
3243#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
3244#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007
3245#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008
3246#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009
3247#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a
3248#define RADEON_CP_VC_CNTL_PRIM_TYPE_QUAD_LIST 0x0000000d
3249#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x00000010
3250#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x00000020
3251#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x00000030
3252#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000
3253#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040
3254#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x00000080
3255#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x00000000
3256#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x00000100
3257#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x00000000
3258#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x00000200
3259#define RADEON_CP_VC_CNTL_NUM_SHIFT 16
3260
3261#define RADEON_VS_MATRIX_0_ADDR 0
3262#define RADEON_VS_MATRIX_1_ADDR 4
3263#define RADEON_VS_MATRIX_2_ADDR 8
3264#define RADEON_VS_MATRIX_3_ADDR 12
3265#define RADEON_VS_MATRIX_4_ADDR 16
3266#define RADEON_VS_MATRIX_5_ADDR 20
3267#define RADEON_VS_MATRIX_6_ADDR 24
3268#define RADEON_VS_MATRIX_7_ADDR 28
3269#define RADEON_VS_MATRIX_8_ADDR 32
3270#define RADEON_VS_MATRIX_9_ADDR 36
3271#define RADEON_VS_MATRIX_10_ADDR 40
3272#define RADEON_VS_MATRIX_11_ADDR 44
3273#define RADEON_VS_MATRIX_12_ADDR 48
3274#define RADEON_VS_MATRIX_13_ADDR 52
3275#define RADEON_VS_MATRIX_14_ADDR 56
3276#define RADEON_VS_MATRIX_15_ADDR 60
3277#define RADEON_VS_LIGHT_AMBIENT_ADDR 64
3278#define RADEON_VS_LIGHT_DIFFUSE_ADDR 72
3279#define RADEON_VS_LIGHT_SPECULAR_ADDR 80
3280#define RADEON_VS_LIGHT_DIRPOS_ADDR 88
3281#define RADEON_VS_LIGHT_HWVSPOT_ADDR 96
3282#define RADEON_VS_LIGHT_ATTENUATION_ADDR 104
3283#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 112
3284#define RADEON_VS_UCP_ADDR 116
3285#define RADEON_VS_GLOBAL_AMBIENT_ADDR 122
3286#define RADEON_VS_FOG_PARAM_ADDR 123
3287#define RADEON_VS_EYE_VECTOR_ADDR 124
3288
3289#define RADEON_SS_LIGHT_DCD_ADDR 0
3290#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 8
3291#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 16
3292#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 24
3293#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 32
3294#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 48
3295#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 49
3296#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 50
3297#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51
3298#define RADEON_SS_SHININESS 60
3299
3300#define RADEON_TV_MASTER_CNTL 0x0800
3301# define RADEON_TV_ASYNC_RST (1 << 0)
3302# define RADEON_CRT_ASYNC_RST (1 << 1)
3303# define RADEON_RESTART_PHASE_FIX (1 << 3)
3304#define RADEON_TV_FIFO_ASYNC_RST (1 << 4)
3305#define RADEON_VIN_ASYNC_RST (1 << 5)
3306#define RADEON_AUD_ASYNC_RST (1 << 6)
3307#define RADEON_DVS_ASYNC_RST (1 << 7)
3308# define RADEON_CRT_FIFO_CE_EN (1 << 9)
3309# define RADEON_TV_FIFO_CE_EN (1 << 10)
3310# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)
3311# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)
3312#define RADEON_TV_ON (1 << 31)
3313#define RADEON_TV_PRE_DAC_MUX_CNTL 0x0888
3314# define RADEON_Y_RED_EN (1 << 0)
3315# define RADEON_C_GRN_EN (1 << 1)
3316# define RADEON_CMP_BLU_EN (1 << 2)
3317# define RADEON_DAC_DITHER_EN (1 << 3)
3318# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)
3319# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)
3320# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)
3321# define RADEON_TV_FORCE_DAC_DATA_SHIFT 16
3322#define RADEON_TV_RGB_CNTL 0x0804
3323# define RADEON_SWITCH_TO_BLUE (1 << 4)
3324# define RADEON_RGB_DITHER_EN (1 << 5)
3325# define RADEON_RGB_SRC_SEL_MASK (3 << 8)
3326# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)
3327# define RADEON_RGB_SRC_SEL_RMX (1 << 8)
3328# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)
3329# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)
3330# define RADEON_UVRAM_READ_MARGIN_SHIFT 16
3331# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 20
3332#define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)
3333#define RADEON_TVOUT_SCALE_EN (1 << 26)
3334#define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)
3335#define RADEON_TV_SYNC_CNTL 0x0808
3336# define RADEON_SYNC_OE (1 << 0)
3337# define RADEON_SYNC_OUT (1 << 1)
3338# define RADEON_SYNC_IN (1 << 2)
3339# define RADEON_SYNC_PUB (1 << 3)
3340# define RADEON_SYNC_PD (1 << 4)
3341# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)
3342#define RADEON_TV_HTOTAL 0x080c
3343#define RADEON_TV_HDISP 0x0810
3344#define RADEON_TV_HSTART 0x0818
3345#define RADEON_TV_HCOUNT 0x081C
3346#define RADEON_TV_VTOTAL 0x0820
3347#define RADEON_TV_VDISP 0x0824
3348#define RADEON_TV_VCOUNT 0x0828
3349#define RADEON_TV_FTOTAL 0x082c
3350#define RADEON_TV_FCOUNT 0x0830
3351#define RADEON_TV_FRESTART 0x0834
3352#define RADEON_TV_HRESTART 0x0838
3353#define RADEON_TV_VRESTART 0x083c
3354#define RADEON_TV_HOST_READ_DATA 0x0840
3355#define RADEON_TV_HOST_WRITE_DATA 0x0844
3356#define RADEON_TV_HOST_RD_WT_CNTL 0x0848
3357#define RADEON_HOST_FIFO_RD (1 << 12)
3358#define RADEON_HOST_FIFO_RD_ACK (1 << 13)
3359#define RADEON_HOST_FIFO_WT (1 << 14)
3360#define RADEON_HOST_FIFO_WT_ACK (1 << 15)
3361#define RADEON_TV_VSCALER_CNTL1 0x084c
3362# define RADEON_UV_INC_MASK 0xffff
3363# define RADEON_UV_INC_SHIFT 0
3364# define RADEON_Y_W_EN (1 << 24)
3365# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */
3366# define RADEON_Y_DEL_W_SIG_SHIFT 26
3367#define RADEON_TV_TIMING_CNTL 0x0850
3368# define RADEON_H_INC_MASK 0xfff
3369# define RADEON_H_INC_SHIFT 0
3370# define RADEON_REQ_Y_FIRST (1 << 19)
3371# define RADEON_FORCE_BURST_ALWAYS (1 << 21)
3372# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)
3373# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 24
3374#define RADEON_TV_VSCALER_CNTL2 0x0854
3375# define RADEON_DITHER_MODE (1 << 0)
3376# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)
3377# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)
3378# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)
3379#define RADEON_TV_Y_FALL_CNTL 0x0858
3380# define RADEON_Y_FALL_PING_PONG (1 << 16)
3381# define RADEON_Y_COEF_EN (1 << 17)
3382#define RADEON_TV_Y_RISE_CNTL 0x085c
3383# define RADEON_Y_RISE_PING_PONG (1 << 16)
3384#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x0860
3385#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x0864
3386#define RADEON_YUPSAMP_EN (1 << 0)
3387#define RADEON_UVUPSAMP_EN (1 << 2)
3388#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x0868
3389# define RADEON_Y_GAIN_LIMIT_SHIFT 0
3390# define RADEON_UV_GAIN_LIMIT_SHIFT 16
3391#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c
3392# define RADEON_Y_GAIN_SHIFT 0
3393# define RADEON_UV_GAIN_SHIFT 16
3394#define RADEON_TV_MODULATOR_CNTL1 0x0870
3395#define RADEON_YFLT_EN (1 << 2)
3396#define RADEON_UVFLT_EN (1 << 3)
3397# define RADEON_ALT_PHASE_EN (1 << 6)
3398# define RADEON_SYNC_TIP_LEVEL (1 << 7)
3399# define RADEON_BLANK_LEVEL_SHIFT 8
3400# define RADEON_SET_UP_LEVEL_SHIFT 16
3401#define RADEON_SLEW_RATE_LIMIT (1 << 23)
3402# define RADEON_CY_FILT_BLEND_SHIFT 28
3403#define RADEON_TV_MODULATOR_CNTL2 0x0874
3404# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff
3405# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff
3406# define RADEON_TV_V_BURST_LEVEL_SHIFT 16
3407#define RADEON_TV_CRC_CNTL 0x0890
3408#define RADEON_TV_UV_ADR 0x08ac
3409#define RADEON_MAX_UV_ADR_MASK 0x000000ff
3410#define RADEON_MAX_UV_ADR_SHIFT 0
3411#define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff00
3412#define RADEON_TABLE1_BOT_ADR_SHIFT 8
3413#define RADEON_TABLE3_TOP_ADR_MASK 0x00ff0000
3414#define RADEON_TABLE3_TOP_ADR_SHIFT 16
3415#define RADEON_HCODE_TABLE_SEL_MASK 0x06000000
3416#define RADEON_HCODE_TABLE_SEL_SHIFT 25
3417#define RADEON_VCODE_TABLE_SEL_MASK 0x18000000
3418#define RADEON_VCODE_TABLE_SEL_SHIFT 27
3419#define RADEON_TV_MAX_FIFO_ADDR 0x1a7
3420#define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff
3421#define RADEON_TV_PLL_FINE_CNTL 0x0020/* PLL */
3422#define RADEON_TV_PLL_CNTL 0x0021/* PLL */
3423# define RADEON_TV_M0LO_MASK 0xff
3424# define RADEON_TV_M0HI_MASK 0x7
3425# define RADEON_TV_M0HI_SHIFT 18
3426# define RADEON_TV_N0LO_MASK 0x1ff
3427# define RADEON_TV_N0LO_SHIFT 8
3428# define RADEON_TV_N0HI_MASK 0x3
3429# define RADEON_TV_N0HI_SHIFT 21
3430# define RADEON_TV_P_MASK 0xf
3431# define RADEON_TV_P_SHIFT 24
3432# define RADEON_TV_SLIP_EN (1 << 23)
3433# define RADEON_TV_DTO_EN (1 << 28)
3434#define RADEON_TV_PLL_CNTL1 0x0022/* PLL */
3435# define RADEON_TVPLL_RESET (1 << 1)
3436# define RADEON_TVPLL_SLEEP (1 << 3)
3437# define RADEON_TVPLL_REFCLK_SEL (1 << 4)
3438# define RADEON_TVPCP_SHIFT 8
3439# define RADEON_TVPCP_MASK (7 << 8)
3440# define RADEON_TVPVG_SHIFT 11
3441# define RADEON_TVPVG_MASK (7 << 11)
3442# define RADEON_TVPDC_SHIFT 14
3443# define RADEON_TVPDC_MASK (3 << 14)
3444# define RADEON_TVPLL_TEST_DIS (1 << 31)
3445# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)
3446
3447#define RS400_DISP2_REQ_CNTL10xe30
3448# define RS400_DISP2_START_REQ_LEVEL_SHIFT 0
3449# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff
3450# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 12
3451# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff
3452# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 22
3453# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff
3454#define RS400_DISP2_REQ_CNTL20xe34
3455# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 12
3456# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff
3457# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 22
3458# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff
3459#define RS400_DMIF_MEM_CNTL10xe38
3460# define RS400_DISP2_START_ADR_SHIFT 0
3461# define RS400_DISP2_START_ADR_MASK 0x3ff
3462# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 12
3463# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff
3464# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 22
3465# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff
3466#define RS400_DISP1_REQ_CNTL10xe3c
3467# define RS400_DISP1_START_REQ_LEVEL_SHIFT 0
3468# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff
3469# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 12
3470# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff
3471# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 22
3472# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff
3473
3474#define RS690_MC_INDEX0x78
3475#define RS690_MC_INDEX_MASK0x1ff
3476#define RS690_MC_INDEX_WR_EN(1 << 9)
3477#define RS690_MC_INDEX_WR_ACK0x7f
3478#define RS690_MC_DATA0x7c
3479
3480#define RS690_MC_FB_LOCATION0x100
3481#define RS690_MC_AGP_LOCATION0x101
3482#define RS690_MC_AGP_BASE0x102
3483#define RS690_MC_AGP_BASE_2 0x103
3484#define RS690_MC_INIT_MISC_LAT_TIMER 0x104
3485#define RS690_MC_STATUS 0x90
3486#define RS690_MC_STATUS_IDLE (1 << 0)
3487
3488#define RS600_MC_INDEX 0x70
3489#define RS600_MC_ADDR_MASK0xffff
3490# define RS600_MC_IND_SEQ_RBS_0 (1 << 16)
3491# define RS600_MC_IND_SEQ_RBS_1 (1 << 17)
3492# define RS600_MC_IND_SEQ_RBS_2 (1 << 18)
3493# define RS600_MC_IND_SEQ_RBS_3 (1 << 19)
3494# define RS600_MC_IND_AIC_RBS (1 << 20)
3495# define RS600_MC_IND_CITF_ARB0 (1 << 21)
3496# define RS600_MC_IND_CITF_ARB1 (1 << 22)
3497# define RS600_MC_IND_WR_EN (1 << 23)
3498#define RS600_MC_DATA 0x74
3499
3500#define RS600_MC_STATUS 0x0
3501#define RS600_MC_IDLE (1 << 1)
3502#define RS600_MC_FB_LOCATION 0x4
3503#define RS600_MC_AGP_LOCATION 0x5
3504#define RS600_AGP_BASE 0x6
3505#define RS600_AGP_BASE2 0x7
3506
3507#define AVIVO_MC_INDEX0x0070
3508#define R520_MC_STATUS 0x00
3509# define R520_MC_STATUS_IDLE (1 << 1)
3510#define RV515_MC_STATUS 0x08
3511# define RV515_MC_STATUS_IDLE (1 << 4)
3512#define RV515_MC_INIT_MISC_LAT_TIMER 0x09
3513#define AVIVO_MC_DATA0x0074
3514
3515#define RV515_MC_FB_LOCATION 0x1
3516#define RV515_MC_AGP_LOCATION 0x2
3517#define RV515_MC_AGP_BASE 0x3
3518#define RV515_MC_AGP_BASE_2 0x4
3519#define RV515_MC_CNTL 0x5
3520#define RV515_MEM_NUM_CHANNELS_MASK 0x3
3521#define R520_MC_FB_LOCATION 0x4
3522#define R520_MC_AGP_LOCATION 0x5
3523#define R520_MC_AGP_BASE 0x6
3524#define R520_MC_AGP_BASE_2 0x7
3525#define R520_MC_CNTL0 0x8
3526#define R520_MEM_NUM_CHANNELS_MASK (0x3 << 24)
3527#define R520_MEM_NUM_CHANNELS_SHIFT 24
3528#define R520_MC_CHANNEL_SIZE (1 << 23)
3529
3530#define RS780_MC_INDEX0x28f8
3531#define RS780_MC_INDEX_MASK0x1ff
3532#define RS780_MC_INDEX_WR_EN(1 << 9)
3533#define RS780_MC_DATA0x28fc
3534
3535#define R600_RAMCFG 0x2408
3536# define R600_CHANSIZE (1 << 7)
3537# define R600_CHANSIZE_OVERRIDE (1 << 10)
3538
3539#define R600_SRBM_STATUS 0x0e50
3540
3541#define AVIVO_CP_DYN_CNTL 0x000f /* PLL */
3542# define AVIVO_CP_FORCEON (1 << 0)
3543#define AVIVO_E2_DYN_CNTL 0x0011 /* PLL */
3544# define AVIVO_E2_FORCEON (1 << 0)
3545#define AVIVO_IDCT_DYN_CNTL 0x0013 /* PLL */
3546# define AVIVO_IDCT_FORCEON (1 << 0)
3547
3548#define AVIVO_HDP_FB_LOCATION 0x134
3549
3550#define AVIVO_VGA_RENDER_CONTROL0x0300
3551# define AVIVO_VGA_VSTATUS_CNTL_MASK (3 << 16)
3552#define AVIVO_D1VGA_CONTROL0x0330
3553# define AVIVO_DVGA_CONTROL_MODE_ENABLE (1<<0)
3554# define AVIVO_DVGA_CONTROL_TIMING_SELECT (1<<8)
3555# define AVIVO_DVGA_CONTROL_SYNC_POLARITY_SELECT (1<<9)
3556# define AVIVO_DVGA_CONTROL_OVERSCAN_TIMING_SELECT (1<<10)
3557# define AVIVO_DVGA_CONTROL_OVERSCAN_COLOR_EN (1<<16)
3558# define AVIVO_DVGA_CONTROL_ROTATE (1<<24)
3559#define AVIVO_D2VGA_CONTROL0x0338
3560
3561#define AVIVO_VGA25_PPLL_REF_DIV_SRC0x0360
3562#define AVIVO_VGA25_PPLL_REF_DIV0x0364
3563#define AVIVO_VGA28_PPLL_REF_DIV_SRC0x0368
3564#define AVIVO_VGA28_PPLL_REF_DIV0x036c
3565#define AVIVO_VGA41_PPLL_REF_DIV_SRC0x0370
3566#define AVIVO_VGA41_PPLL_REF_DIV0x0374
3567#define AVIVO_VGA25_PPLL_FB_DIV0x0378
3568#define AVIVO_VGA28_PPLL_FB_DIV0x037c
3569#define AVIVO_VGA41_PPLL_FB_DIV0x0380
3570#define AVIVO_VGA25_PPLL_POST_DIV_SRC0x0384
3571#define AVIVO_VGA25_PPLL_POST_DIV0x0388
3572#define AVIVO_VGA28_PPLL_POST_DIV_SRC0x038c
3573#define AVIVO_VGA28_PPLL_POST_DIV0x0390
3574#define AVIVO_VGA41_PPLL_POST_DIV_SRC0x0394
3575#define AVIVO_VGA41_PPLL_POST_DIV0x0398
3576#define AVIVO_VGA25_PPLL_CNTL0x039c
3577#define AVIVO_VGA28_PPLL_CNTL0x03a0
3578#define AVIVO_VGA41_PPLL_CNTL0x03a4
3579
3580#define AVIVO_EXT1_PPLL_REF_DIV_SRC 0x400
3581#define AVIVO_EXT1_PPLL_REF_DIV 0x404
3582#define AVIVO_EXT1_PPLL_UPDATE_LOCK 0x408
3583#define AVIVO_EXT1_PPLL_UPDATE_CNTL 0x40c
3584
3585#define AVIVO_EXT2_PPLL_REF_DIV_SRC 0x410
3586#define AVIVO_EXT2_PPLL_REF_DIV 0x414
3587#define AVIVO_EXT2_PPLL_UPDATE_LOCK 0x418
3588#define AVIVO_EXT2_PPLL_UPDATE_CNTL 0x41c
3589
3590#define AVIVO_EXT1_PPLL_FB_DIV 0x430
3591#define AVIVO_EXT2_PPLL_FB_DIV 0x434
3592
3593#define AVIVO_EXT1_PPLL_POST_DIV_SRC 0x438
3594#define AVIVO_EXT1_PPLL_POST_DIV 0x43c
3595
3596#define AVIVO_EXT2_PPLL_POST_DIV_SRC 0x440
3597#define AVIVO_EXT2_PPLL_POST_DIV 0x444
3598
3599#define AVIVO_EXT1_PPLL_CNTL 0x448
3600#define AVIVO_EXT2_PPLL_CNTL 0x44c
3601
3602#define AVIVO_P1PLL_CNTL 0x450
3603#define AVIVO_P2PLL_CNTL 0x454
3604#define AVIVO_P1PLL_INT_SS_CNTL 0x458
3605#define AVIVO_P2PLL_INT_SS_CNTL 0x45c
3606#define AVIVO_P1PLL_TMDSA_CNTL 0x460
3607#define AVIVO_P2PLL_LVTMA_CNTL 0x464
3608
3609#define AVIVO_PCLK_CRTC1_CNTL 0x480
3610#define AVIVO_PCLK_CRTC2_CNTL 0x484
3611
3612#define AVIVO_D1CRTC_H_TOTAL0x6000
3613#define AVIVO_D1CRTC_H_BLANK_START_END 0x6004
3614#define AVIVO_D1CRTC_H_SYNC_A 0x6008
3615#define AVIVO_D1CRTC_H_SYNC_A_CNTL 0x600c
3616#define AVIVO_D1CRTC_H_SYNC_B 0x6010
3617#define AVIVO_D1CRTC_H_SYNC_B_CNTL 0x6014
3618
3619#define AVIVO_D1CRTC_V_TOTAL0x6020
3620#define AVIVO_D1CRTC_V_BLANK_START_END 0x6024
3621#define AVIVO_D1CRTC_V_SYNC_A 0x6028
3622#define AVIVO_D1CRTC_V_SYNC_A_CNTL 0x602c
3623#define AVIVO_D1CRTC_V_SYNC_B 0x6030
3624#define AVIVO_D1CRTC_V_SYNC_B_CNTL 0x6034
3625
3626#define AVIVO_D1CRTC_CONTROL 0x6080
3627# define AVIVO_CRTC_EN (1<<0)
3628#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
3629#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
3630#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
3631#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
3632
3633/* master controls */
3634#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
3635#define AVIVO_DC_CRTC_TV_CONTROL 0x60fc
3636
3637#define AVIVO_D1GRPH_ENABLE 0x6100
3638#define AVIVO_D1GRPH_CONTROL 0x6104
3639# define AVIVO_D1GRPH_CONTROL_DEPTH_8BPP (0<<0)
3640# define AVIVO_D1GRPH_CONTROL_DEPTH_16BPP (1<<0)
3641# define AVIVO_D1GRPH_CONTROL_DEPTH_32BPP (2<<0)
3642# define AVIVO_D1GRPH_CONTROL_DEPTH_64BPP (3<<0)
3643
3644# define AVIVO_D1GRPH_CONTROL_8BPP_INDEXED (0<<8)
3645
3646# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555 (0<<8)
3647# define AVIVO_D1GRPH_CONTROL_16BPP_RGB565 (1<<8)
3648# define AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444 (2<<8)
3649# define AVIVO_D1GRPH_CONTROL_16BPP_AI88 (3<<8)
3650# define AVIVO_D1GRPH_CONTROL_16BPP_MONO16 (4<<8)
3651
3652# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888 (0<<8)
3653# define AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010 (1<<8)
3654# define AVIVO_D1GRPH_CONTROL_32BPP_DIGITAL (2<<8)
3655# define AVIVO_D1GRPH_CONTROL_32BPP_8B_ARGB2101010 (3<<8)
3656
3657
3658# define AVIVO_D1GRPH_CONTROL_64BPP_ARGB16161616 (0<<8)
3659
3660# define AVIVO_D1GRPH_SWAP_RB (1<<16)
3661# define AVIVO_D1GRPH_TILED (1<<20)
3662# define AVIVO_D1GRPH_MACRO_ADDRESS_MODE (1<<21)
3663
3664#define AVIVO_D1GRPH_LUT_SEL 0x6108
3665
3666#define R600_D1GRPH_SWAP_CONTROL 0x610C
3667# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0)
3668# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0)
3669# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0)
3670# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0)
3671
3672/* the *_HIGH surface regs are backwards; the D1 regs are in the D2
3673 * block and vice versa. This applies to GRPH, CUR, etc.
3674 */
3675
3676#define AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
3677#define R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
3678#define R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
3679#define AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
3680#define R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
3681#define R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
3682#define AVIVO_D1GRPH_PITCH 0x6120
3683#define AVIVO_D1GRPH_SURFACE_OFFSET_X 0x6124
3684#define AVIVO_D1GRPH_SURFACE_OFFSET_Y 0x6128
3685#define AVIVO_D1GRPH_X_START 0x612c
3686#define AVIVO_D1GRPH_Y_START 0x6130
3687#define AVIVO_D1GRPH_X_END 0x6134
3688#define AVIVO_D1GRPH_Y_END 0x6138
3689#define AVIVO_D1GRPH_UPDATE 0x6144
3690# define AVIVO_D1GRPH_UPDATE_LOCK (1<<16)
3691#define AVIVO_D1GRPH_FLIP_CONTROL 0x6148
3692
3693#define AVIVO_D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL 0x6380
3694
3695#define AVIVO_D1CUR_CONTROL 0x6400
3696# define AVIVO_D1CURSOR_EN (1<<0)
3697# define AVIVO_D1CURSOR_MODE_SHIFT 8
3698# define AVIVO_D1CURSOR_MODE_MASK (0x3<<8)
3699# define AVIVO_D1CURSOR_MODE_24BPP (0x2)
3700#define AVIVO_D1CUR_SURFACE_ADDRESS 0x6408
3701#define R700_D1CUR_SURFACE_ADDRESS_HIGH 0x6c0c
3702#define R700_D2CUR_SURFACE_ADDRESS_HIGH 0x640c
3703#define AVIVO_D1CUR_SIZE 0x6410
3704#define AVIVO_D1CUR_POSITION 0x6414
3705#define AVIVO_D1CUR_HOT_SPOT 0x6418
3706#define AVIVO_D1CUR_UPDATE 0x6424
3707# define AVIVO_D1CURSOR_UPDATE_LOCK (1 << 16)
3708
3709#define AVIVO_DC_LUT_RW_SELECT 0x6480
3710#define AVIVO_DC_LUT_RW_MODE 0x6484
3711#define AVIVO_DC_LUT_RW_INDEX 0x6488
3712#define AVIVO_DC_LUT_SEQ_COLOR 0x648c
3713#define AVIVO_DC_LUT_PWL_DATA 0x6490
3714#define AVIVO_DC_LUT_30_COLOR 0x6494
3715#define AVIVO_DC_LUT_READ_PIPE_SELECT 0x6498
3716#define AVIVO_DC_LUT_WRITE_EN_MASK 0x649c
3717#define AVIVO_DC_LUT_AUTOFILL 0x64a0
3718
3719#define AVIVO_DC_LUTA_CONTROL 0x64c0
3720#define AVIVO_DC_LUTA_BLACK_OFFSET_BLUE 0x64c4
3721#define AVIVO_DC_LUTA_BLACK_OFFSET_GREEN 0x64c8
3722#define AVIVO_DC_LUTA_BLACK_OFFSET_RED 0x64cc
3723#define AVIVO_DC_LUTA_WHITE_OFFSET_BLUE 0x64d0
3724#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
3725#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
3726
3727#define AVIVO_DC_LB_MEMORY_SPLIT 0x6520
3728# define AVIVO_DC_LB_MEMORY_SPLIT_MASK 0x3
3729# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT 0
3730# define AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF 0
3731# define AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q 1
3732# define AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY 2
3733# define AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q 3
3734# define AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE (1 << 2)
3735# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
3736# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
3737#define AVIVO_D1MODE_PRIORITY_A_CNT 0x6548
3738# define AVIVO_DxMODE_PRIORITY_MARK_MASK 0x7fff
3739# define AVIVO_DxMODE_PRIORITY_OFF (1 << 16)
3740# define AVIVO_DxMODE_PRIORITY_ALWAYS_ON (1 << 20)
3741# define AVIVO_DxMODE_PRIORITY_FORCE_MASK (1 << 24)
3742#define AVIVO_D1MODE_PRIORITY_B_CNT 0x654c
3743#define AVIVO_D2MODE_PRIORITY_A_CNT 0x6d48
3744#define AVIVO_D2MODE_PRIORITY_B_CNT 0x6d4c
3745#define AVIVO_LB_MAX_REQ_OUTSTANDING 0x6d58
3746# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_MASK 0xf
3747# define AVIVO_LB_D1_MAX_REQ_OUTSTANDING_SHIFT 0
3748# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_MASK 0xf
3749# define AVIVO_LB_D2_MAX_REQ_OUTSTANDING_SHIFT 16
3750
3751#define AVIVO_D1MODE_DATA_FORMAT 0x6528
3752# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
3753#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c
3754#define AVIVO_D1MODE_VLINE_START_END 0x6538
3755# define AVIVO_D1MODE_VLINE_START_SHIFT 0
3756# define AVIVO_D1MODE_VLINE_END_SHIFT 16
3757# define AVIVO_D1MODE_VLINE_INV (1 << 31)
3758#define AVIVO_D1MODE_VLINE_STATUS 0x653c
3759# define AVIVO_D1MODE_VLINE_STAT (1 << 12)
3760#define AVIVO_D1MODE_VIEWPORT_START 0x6580
3761#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
3762#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
3763#define AVIVO_D1MODE_EXT_OVERSCAN_TOP_BOTTOM 0x658c
3764
3765#define AVIVO_D1SCL_SCALER_ENABLE 0x6590
3766#define AVIVO_D1SCL_SCALER_TAP_CONTROL 0x6594
3767#define AVIVO_D1SCL_UPDATE 0x65cc
3768# define AVIVO_D1SCL_UPDATE_LOCK (1<<16)
3769
3770/* second crtc */
3771#define AVIVO_D2CRTC_H_TOTAL0x6800
3772#define AVIVO_D2CRTC_H_BLANK_START_END 0x6804
3773#define AVIVO_D2CRTC_H_SYNC_A 0x6808
3774#define AVIVO_D2CRTC_H_SYNC_A_CNTL 0x680c
3775#define AVIVO_D2CRTC_H_SYNC_B 0x6810
3776#define AVIVO_D2CRTC_H_SYNC_B_CNTL 0x6814
3777
3778#define AVIVO_D2CRTC_V_TOTAL0x6820
3779#define AVIVO_D2CRTC_V_BLANK_START_END 0x6824
3780#define AVIVO_D2CRTC_V_SYNC_A 0x6828
3781#define AVIVO_D2CRTC_V_SYNC_A_CNTL 0x682c
3782#define AVIVO_D2CRTC_V_SYNC_B 0x6830
3783#define AVIVO_D2CRTC_V_SYNC_B_CNTL 0x6834
3784
3785#define AVIVO_D2CRTC_CONTROL 0x6880
3786#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
3787#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
3788#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
3789#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
3790
3791#define AVIVO_D2GRPH_ENABLE 0x6900
3792#define AVIVO_D2GRPH_CONTROL 0x6904
3793#define AVIVO_D2GRPH_LUT_SEL 0x6908
3794#define AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS 0x6910
3795#define AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS 0x6918
3796#define AVIVO_D2GRPH_PITCH 0x6920
3797#define AVIVO_D2GRPH_SURFACE_OFFSET_X 0x6924
3798#define AVIVO_D2GRPH_SURFACE_OFFSET_Y 0x6928
3799#define AVIVO_D2GRPH_X_START 0x692c
3800#define AVIVO_D2GRPH_Y_START 0x6930
3801#define AVIVO_D2GRPH_X_END 0x6934
3802#define AVIVO_D2GRPH_Y_END 0x6938
3803#define AVIVO_D2GRPH_UPDATE 0x6944
3804#define AVIVO_D2GRPH_FLIP_CONTROL 0x6948
3805
3806#define AVIVO_D2CUR_CONTROL 0x6c00
3807#define AVIVO_D2CUR_SURFACE_ADDRESS 0x6c08
3808#define AVIVO_D2CUR_SIZE 0x6c10
3809#define AVIVO_D2CUR_POSITION 0x6c14
3810
3811#define RS690_DCP_CONTROL 0x6c9c
3812
3813#define AVIVO_D2MODE_DATA_FORMAT 0x6d28
3814#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c
3815#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
3816#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
3817#define AVIVO_D2MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6d88
3818#define AVIVO_D2MODE_EXT_OVERSCAN_TOP_BOTTOM 0x6d8c
3819
3820#define AVIVO_D2SCL_SCALER_ENABLE 0x6d90
3821#define AVIVO_D2SCL_SCALER_TAP_CONTROL 0x6d94
3822#define AVIVO_D2SCL_UPDATE 0x6dcc
3823
3824#define AVIVO_DDIA_BIT_DEPTH_CONTROL0x7214
3825
3826#define AVIVO_DACA_ENABLE0x7800
3827#define AVIVO_DAC_ENABLE(1 << 0)
3828#define AVIVO_DACA_SOURCE_SELECT0x7804
3829# define AVIVO_DAC_SOURCE_CRTC1 (0 << 0)
3830# define AVIVO_DAC_SOURCE_CRTC2 (1 << 0)
3831# define AVIVO_DAC_SOURCE_TV (2 << 0)
3832
3833#define AVIVO_DACA_FORCE_OUTPUT_CNTL0x783c
3834# define AVIVO_DACA_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
3835# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
3836# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
3837# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
3838# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
3839# define AVIVO_DACA_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
3840#define AVIVO_DACA_POWERDOWN0x7850
3841# define AVIVO_DACA_POWERDOWN_POWERDOWN (1 << 0)
3842# define AVIVO_DACA_POWERDOWN_BLUE (1 << 8)
3843# define AVIVO_DACA_POWERDOWN_GREEN (1 << 16)
3844# define AVIVO_DACA_POWERDOWN_RED (1 << 24)
3845
3846#define AVIVO_DACB_ENABLE0x7a00
3847#define AVIVO_DACB_SOURCE_SELECT0x7a04
3848#define AVIVO_DACB_FORCE_OUTPUT_CNTL0x7a3c
3849# define AVIVO_DACB_FORCE_OUTPUT_CNTL_FORCE_DATA_EN (1 << 0)
3850# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_SHIFT (8)
3851# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_BLUE (1 << 0)
3852# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_GREEN (1 << 1)
3853# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_SEL_RED (1 << 2)
3854# define AVIVO_DACB_FORCE_OUTPUT_CNTL_DATA_ON_BLANKB_ONLY (1 << 24)
3855#define AVIVO_DACB_POWERDOWN0x7a50
3856# define AVIVO_DACB_POWERDOWN_POWERDOWN (1 << 0)
3857# define AVIVO_DACB_POWERDOWN_BLUE (1 << 8)
3858# define AVIVO_DACB_POWERDOWN_GREEN (1 << 16)
3859# define AVIVO_DACB_POWERDOWN_RED
3860
3861#define AVIVO_TMDSA_CNTL 0x7880
3862# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
3863# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
3864# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
3865# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
3866# define AVIVO_TMDSA_CNTL_PIXEL_ENCODING (1 << 16)
3867# define AVIVO_TMDSA_CNTL_DUAL_LINK_ENABLE (1 << 24)
3868# define AVIVO_TMDSA_CNTL_SWAP (1 << 28)
3869#define AVIVO_TMDSA_SOURCE_SELECT0x7884
3870/* 78a8 appears to be some kind of (reasonably tolerant) clock?
3871 * 78d0 definitely hits the transmitter, definitely clock. */
3872/* MYSTERY1 This appears to control dithering? */
3873#define AVIVO_TMDSA_BIT_DEPTH_CONTROL0x7894
3874# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
3875# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
3876# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
3877# define AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
3878# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
3879# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
3880# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
3881# define AVIVO_TMDS_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
3882#define AVIVO_TMDSA_DCBALANCER_CONTROL 0x78d0
3883# define AVIVO_TMDSA_DCBALANCER_CONTROL_EN (1 << 0)
3884# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
3885# define AVIVO_TMDSA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
3886# define AVIVO_TMDSA_DCBALANCER_CONTROL_FORCE (1 << 24)
3887#define AVIVO_TMDSA_DATA_SYNCHRONIZATION 0x78d8
3888# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
3889# define AVIVO_TMDSA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
3890#define AVIVO_TMDSA_CLOCK_ENABLE 0x7900
3891#define AVIVO_TMDSA_TRANSMITTER_ENABLE 0x7904
3892# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX0_ENABLE (1 << 0)
3893# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
3894# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
3895# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
3896# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
3897# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX1_ENABLE (1 << 8)
3898# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
3899# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
3900# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
3901# define AVIVO_TMDSA_TRANSMITTER_ENABLE_TX_ENABLE_HPD_MASK (1 << 16)
3902# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
3903# define AVIVO_TMDSA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
3904
3905#define AVIVO_TMDSA_TRANSMITTER_CONTROL0x7910
3906#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_ENABLE(1 << 0)
3907#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
3908#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT(2)
3909#define AVIVO_TMDSA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
3910# define AVIVO_TMDSA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
3911#define AVIVO_TMDSA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN(1 << 6)
3912#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
3913#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS(1 << 13)
3914#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
3915#define AVIVO_TMDSA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS(1 << 15)
3916# define AVIVO_TMDSA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
3917#define AVIVO_TMDSA_TRANSMITTER_CONTROL_BYPASS_PLL(1 << 28)
3918# define AVIVO_TMDSA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
3919#define AVIVO_TMDSA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL(1 << 31)
3920
3921#define AVIVO_LVTMA_CNTL0x7a80
3922# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
3923# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
3924# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
3925# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
3926# define AVIVO_LVTMA_CNTL_PIXEL_ENCODING (1 << 16)
3927# define AVIVO_LVTMA_CNTL_DUAL_LINK_ENABLE (1 << 24)
3928# define AVIVO_LVTMA_CNTL_SWAP (1 << 28)
3929#define AVIVO_LVTMA_SOURCE_SELECT 0x7a84
3930#define AVIVO_LVTMA_COLOR_FORMAT 0x7a88
3931#define AVIVO_LVTMA_BIT_DEPTH_CONTROL 0x7a94
3932# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN (1 << 0)
3933# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH (1 << 4)
3934# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN (1 << 8)
3935# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH (1 << 12)
3936# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_EN (1 << 16)
3937# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH (1 << 20)
3938# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL (1 << 24)
3939# define AVIVO_LVTMA_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_RESET (1 << 26)
3940
3941
3942
3943#define AVIVO_LVTMA_DCBALANCER_CONTROL 0x7ad0
3944# define AVIVO_LVTMA_DCBALANCER_CONTROL_EN (1 << 0)
3945# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_EN (1 << 8)
3946# define AVIVO_LVTMA_DCBALANCER_CONTROL_TEST_IN_SHIFT (16)
3947# define AVIVO_LVTMA_DCBALANCER_CONTROL_FORCE (1 << 24)
3948
3949#define AVIVO_LVTMA_DATA_SYNCHRONIZATION 0x78d8
3950# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_DSYNSEL (1 << 0)
3951# define AVIVO_LVTMA_DATA_SYNCHRONIZATION_PFREQCHG (1 << 8)
3952#define R500_LVTMA_CLOCK_ENABLE0x7b00
3953#define R600_LVTMA_CLOCK_ENABLE0x7b04
3954
3955#define R500_LVTMA_TRANSMITTER_ENABLE 0x7b04
3956#define R600_LVTMA_TRANSMITTER_ENABLE 0x7b08
3957# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC0EN (1 << 1)
3958# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD00EN (1 << 2)
3959# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD01EN (1 << 3)
3960# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD02EN (1 << 4)
3961# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD03EN (1 << 5)
3962# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKC1EN (1 << 9)
3963# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD10EN (1 << 10)
3964# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD11EN (1 << 11)
3965# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKD12EN (1 << 12)
3966# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKCEN_HPD_MASK (1 << 17)
3967# define AVIVO_LVTMA_TRANSMITTER_ENABLE_LNKDEN_HPD_MASK (1 << 18)
3968
3969#define R500_LVTMA_TRANSMITTER_CONTROL 0x7b10
3970#define R600_LVTMA_TRANSMITTER_CONTROL 0x7b14
3971#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_ENABLE (1 << 0)
3972#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_RESET (1 << 1)
3973#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_HPD_MASK_SHIFT (2)
3974#define AVIVO_LVTMA_TRANSMITTER_CONTROL_IDSCKSEL (1 << 4)
3975# define AVIVO_LVTMA_TRANSMITTER_CONTROL_BGSLEEP (1 << 5)
3976#define AVIVO_LVTMA_TRANSMITTER_CONTROL_PLL_PWRUP_SEQ_EN (1 << 6)
3977#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK (1 << 8)
3978#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TMCLK_FROM_PADS (1 << 13)
3979#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK (1 << 14)
3980#define AVIVO_LVTMA_TRANSMITTER_CONTROL_TDCLK_FROM_PADS (1 << 15)
3981# define AVIVO_LVTMA_TRANSMITTER_CONTROL_CLK_PATTERN_SHIFT (16)
3982#define AVIVO_LVTMA_TRANSMITTER_CONTROL_BYPASS_PLL (1 << 28)
3983# define AVIVO_LVTMA_TRANSMITTER_CONTROL_USE_CLK_DATA (1 << 29)
3984#define AVIVO_LVTMA_TRANSMITTER_CONTROL_INPUT_TEST_CLK_SEL (1 << 31)
3985
3986#define R500_LVTMA_PWRSEQ_CNTL0x7af0
3987#define R600_LVTMA_PWRSEQ_CNTL0x7af4
3988#define AVIVO_LVTMA_PWRSEQ_EN (1 << 0)
3989#define AVIVO_LVTMA_PWRSEQ_PLL_ENABLE_MASK (1 << 2)
3990#define AVIVO_LVTMA_PWRSEQ_PLL_RESET_MASK (1 << 3)
3991#define AVIVO_LVTMA_PWRSEQ_TARGET_STATE (1 << 4)
3992#define AVIVO_LVTMA_SYNCEN (1 << 8)
3993#define AVIVO_LVTMA_SYNCEN_OVRD (1 << 9)
3994#define AVIVO_LVTMA_SYNCEN_POL (1 << 10)
3995#define AVIVO_LVTMA_DIGON (1 << 16)
3996#define AVIVO_LVTMA_DIGON_OVRD (1 << 17)
3997#define AVIVO_LVTMA_DIGON_POL (1 << 18)
3998#define AVIVO_LVTMA_BLON (1 << 24)
3999#define AVIVO_LVTMA_BLON_OVRD (1 << 25)
4000#define AVIVO_LVTMA_BLON_POL (1 << 26)
4001
4002#define R500_LVTMA_PWRSEQ_STATE 0x7af4
4003#define R600_LVTMA_PWRSEQ_STATE 0x7af8
4004# define AVIVO_LVTMA_PWRSEQ_STATE_TARGET_STATE_R (1 << 0)
4005# define AVIVO_LVTMA_PWRSEQ_STATE_DIGON (1 << 1)
4006# define AVIVO_LVTMA_PWRSEQ_STATE_SYNCEN (1 << 2)
4007# define AVIVO_LVTMA_PWRSEQ_STATE_BLON (1 << 3)
4008# define AVIVO_LVTMA_PWRSEQ_STATE_DONE (1 << 4)
4009# define AVIVO_LVTMA_PWRSEQ_STATE_STATUS_SHIFT (8)
4010
4011#define AVIVO_LVDS_BACKLIGHT_CNTL0x7af8
4012#define AVIVO_LVDS_BACKLIGHT_CNTL_EN(1 << 0)
4013#define AVIVO_LVDS_BACKLIGHT_LEVEL_MASK0x0000ff00
4014#define AVIVO_LVDS_BACKLIGHT_LEVEL_SHIFT8
4015
4016#define AVIVO_DVOA_BIT_DEPTH_CONTROL0x7988
4017
4018#define AVIVO_GPIO_0 0x7e30
4019#define AVIVO_GPIO_1 0x7e40
4020#define AVIVO_GPIO_2 0x7e50
4021#define AVIVO_GPIO_3 0x7e60
4022
4023#define AVIVO_DC_GPIO_HPD_MASK 0x7e90
4024#define AVIVO_DC_GPIO_HPD_A 0x7e94
4025#define AVIVO_DC_GPIO_HPD_EN 0x7e98
4026#define AVIVO_DC_GPIO_HPD_Y 0x7e9c
4027
4028#define AVIVO_I2C_STATUS0x7d30
4029#define AVIVO_I2C_STATUS_DONE(1 << 0)
4030#define AVIVO_I2C_STATUS_NACK(1 << 1)
4031#define AVIVO_I2C_STATUS_HALT(1 << 2)
4032#define AVIVO_I2C_STATUS_GO(1 << 3)
4033#define AVIVO_I2C_STATUS_MASK0x7
4034/* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe
4035 * DONE? */
4036#define AVIVO_I2C_STATUS_CMD_RESET0x7
4037#define AVIVO_I2C_STATUS_CMD_WAIT(1 << 3)
4038#define AVIVO_I2C_STOP0x7d34
4039#define AVIVO_I2C_START_CNTL0x7d38
4040#define AVIVO_I2C_START(1 << 8)
4041#define AVIVO_I2C_CONNECTOR0(0 << 16)
4042#define AVIVO_I2C_CONNECTOR1(1 << 16)
4043#define R520_I2C_START (1<<0)
4044#define R520_I2C_STOP (1<<1)
4045#define R520_I2C_RX (1<<2)
4046#define R520_I2C_EN (1<<8)
4047#define R520_I2C_DDC1 (0<<16)
4048#define R520_I2C_DDC2 (1<<16)
4049#define R520_I2C_DDC3 (2<<16)
4050#define R520_I2C_DDC_MASK (3<<16)
4051#define AVIVO_I2C_CONTROL20x7d3c
4052#define AVIVO_I2C_7D3C_SIZE_SHIFT8
4053#define AVIVO_I2C_7D3C_SIZE_MASK(0xf << 8)
4054#define AVIVO_I2C_CONTROL30x7d40
4055/* Reading is done 4 bytes at a time: read the bottom 8 bits from
4056 * 7d44, four times in a row.
4057 * Writing is a little more complex. First write DATA with
4058 * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic
4059 * magic number, zz is, I think, the slave address, and yy is the byte
4060 * you want to write. */
4061#define AVIVO_I2C_DATA0x7d44
4062#define R520_I2C_ADDR_COUNT_MASK (0x7)
4063#define R520_I2C_DATA_COUNT_SHIFT (8)
4064#define R520_I2C_DATA_COUNT_MASK (0xF00)
4065#define AVIVO_I2C_CNTL0x7d50
4066#define AVIVO_I2C_EN(1 << 0)
4067#define AVIVO_I2C_RESET(1 << 8)
4068
4069#define R600_GENERAL_PWRMGT 0x618
4070#define R600_OPEN_DRAIN_PADS (1 << 11)
4071
4072#define R600_LOWER_GPIO_ENABLE 0x710
4073#define R600_CTXSW_VID_LOWER_GPIO_CNTL 0x718
4074#define R600_HIGH_VID_LOWER_GPIO_CNTL 0x71c
4075#define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720
4076#define R600_LOW_VID_LOWER_GPIO_CNTL 0x724
4077
4078#define R600_MC_VM_FB_LOCATION 0x2180
4079#define R600_MC_VM_AGP_TOP 0x2184
4080#define R600_MC_VM_AGP_BOT 0x2188
4081#define R600_MC_VM_AGP_BASE 0x218c
4082#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190
4083#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194
4084#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198
4085
4086#define R700_MC_VM_FB_LOCATION 0x2024
4087#define R700_MC_VM_AGP_TOP 0x2028
4088#define R700_MC_VM_AGP_BOT 0x202c
4089#define R700_MC_VM_AGP_BASE 0x2030
4090
4091#define R600_HDP_NONSURFACE_BASE 0x2c04
4092
4093#define R600_BUS_CNTL 0x5420
4094#define R600_CONFIG_CNTL 0x5424
4095#define R600_CONFIG_MEMSIZE 0x5428
4096#define R600_CONFIG_F0_BASE 0x542C
4097#define R600_CONFIG_APER_SIZE 0x5430
4098
4099#define R600_ROM_CNTL 0x1600
4100# define R600_SCK_OVERWRITE (1 << 1)
4101# define R600_SCK_PRESCALE_CRYSTAL_CLK_SHIFT 28
4102# define R600_SCK_PRESCALE_CRYSTAL_CLK_MASK (0xf << 28)
4103
4104#define R600_CG_SPLL_FUNC_CNTL 0x600
4105# define R600_SPLL_BYPASS_EN (1 << 3)
4106#define R600_CG_SPLL_STATUS 0x60c
4107# define R600_SPLL_CHG_STATUS (1 << 1)
4108
4109#define R600_BIOS_0_SCRATCH 0x1724
4110#define R600_BIOS_1_SCRATCH 0x1728
4111#define R600_BIOS_2_SCRATCH 0x172c
4112#define R600_BIOS_3_SCRATCH 0x1730
4113#define R600_BIOS_4_SCRATCH 0x1734
4114#define R600_BIOS_5_SCRATCH 0x1738
4115#define R600_BIOS_6_SCRATCH 0x173c
4116#define R600_BIOS_7_SCRATCH 0x1740
4117
4118/* evergreen */
4119#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
4120#define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
4121#define EVERGREEN_D3VGA_CONTROL 0x3e0
4122#define EVERGREEN_D4VGA_CONTROL 0x3e4
4123#define EVERGREEN_D5VGA_CONTROL 0x3e8
4124#define EVERGREEN_D6VGA_CONTROL 0x3ec
4125
4126#define EVERGREEN_P1PLL_SS_CNTL 0x414
4127#define EVERGREEN_P2PLL_SS_CNTL 0x454
4128# define EVERGREEN_PxPLL_SS_EN (1 << 12)
4129/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
4130#define EVERGREEN_GRPH_ENABLE 0x6800
4131#define EVERGREEN_GRPH_CONTROL 0x6804
4132# define EVERGREEN_GRPH_DEPTH(x) (((x) & 0x3) << 0)
4133# define EVERGREEN_GRPH_DEPTH_8BPP 0
4134# define EVERGREEN_GRPH_DEPTH_16BPP 1
4135# define EVERGREEN_GRPH_DEPTH_32BPP 2
4136# define EVERGREEN_GRPH_FORMAT(x) (((x) & 0x7) << 8)
4137/* 8 BPP */
4138# define EVERGREEN_GRPH_FORMAT_INDEXED 0
4139/* 16 BPP */
4140# define EVERGREEN_GRPH_FORMAT_ARGB1555 0
4141# define EVERGREEN_GRPH_FORMAT_ARGB565 1
4142# define EVERGREEN_GRPH_FORMAT_ARGB4444 2
4143# define EVERGREEN_GRPH_FORMAT_AI88 3
4144# define EVERGREEN_GRPH_FORMAT_MONO16 4
4145# define EVERGREEN_GRPH_FORMAT_BGRA5551 5
4146/* 32 BPP */
4147# define EVERGREEN_GRPH_FORMAT_ARGB8888 0
4148# define EVERGREEN_GRPH_FORMAT_ARGB2101010 1
4149# define EVERGREEN_GRPH_FORMAT_32BPP_DIG 2
4150# define EVERGREEN_GRPH_FORMAT_8B_ARGB2101010 3
4151# define EVERGREEN_GRPH_FORMAT_BGRA1010102 4
4152# define EVERGREEN_GRPH_FORMAT_8B_BGRA1010102 5
4153# define EVERGREEN_GRPH_FORMAT_RGB111110 6
4154# define EVERGREEN_GRPH_FORMAT_BGR101111 7
4155#define EVERGREEN_GRPH_SWAP_CONTROL 0x680c
4156# define EVERGREEN_GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
4157# define EVERGREEN_GRPH_ENDIAN_NONE 0
4158# define EVERGREEN_GRPH_ENDIAN_8IN16 1
4159# define EVERGREEN_GRPH_ENDIAN_8IN32 2
4160# define EVERGREEN_GRPH_ENDIAN_8IN64 3
4161# define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
4162# define EVERGREEN_GRPH_RED_SEL_R 0
4163# define EVERGREEN_GRPH_RED_SEL_G 1
4164# define EVERGREEN_GRPH_RED_SEL_B 2
4165# define EVERGREEN_GRPH_RED_SEL_A 3
4166# define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
4167# define EVERGREEN_GRPH_GREEN_SEL_G 0