1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "modules.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | static uint16_t simpleGetSMBOemProcessorType(void);␊ |
21 | ␊ |
22 | ␊ |
23 | bool getProcessorInformationExternalClock(returnType *value)␊ |
24 | {␊ |
25 | ␉value->word = Platform->CPU.FSBFrequency/1000000;␊ |
26 | ␉return true;␊ |
27 | }␊ |
28 | ␊ |
29 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
30 | {␊ |
31 | ␉// Note: it seems that AppleSMBIOS use the maximum clock to set the cpu clock␊ |
32 | ␉// that is showed in "About this mac" or in the System Information. ␊ |
33 | ␉// in my opinion the current clock should be used for this.␊ |
34 | ␉// value->word = Platform->CPU.TSCFrequency/1000000;␊ |
35 | ␉␊ |
36 | ␉value->word = Platform->CPU.CPUFrequency/1000000;␊ |
37 | ␉return true;␊ |
38 | }␊ |
39 | ␊ |
40 | bool getProcessorInformationCurrentClock(returnType *value)␊ |
41 | {␊ |
42 | ␉value->word = Platform->CPU.CPUFrequency/1000000;␊ |
43 | ␉return true;␊ |
44 | }␊ |
45 | ␊ |
46 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
47 | {␊ |
48 | ␉if (Platform->CPU.Vendor == 0x756E6547) // Intel␊ |
49 | ␉{␉␉␊ |
50 | ␉␉switch (Platform->CPU.Family) ␊ |
51 | ␉␉{␊ |
52 | ␉␉␉case 0x06:␊ |
53 | ␉␉␉{␊ |
54 | ␉␉␉␉switch (Platform->CPU.Model)␊ |
55 | ␉␉␉␉{␊ |
56 | case CPUID_MODEL_BANIAS:␉// Banias␉␉0x09␊ |
57 | case CPUID_MODEL_DOTHAN:␉// Dothan␉␉0x0D␊ |
58 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊ |
59 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Merom␉␉0x0F␊ |
60 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊ |
61 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊ |
62 | ␉␉␉␉␉␉return false;␊ |
63 | ␊ |
64 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
65 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊ |
66 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊ |
67 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊ |
68 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊ |
69 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊ |
70 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
71 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
72 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
73 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
74 | ␉␉␉␉␉{␊ |
75 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
76 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
77 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
78 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
79 | ␉␉␉␉␉␉unsigned int i;␊ |
80 | ␉␉␉␉␉␉␊ |
81 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
82 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
83 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
84 | ␉␉␉␉␉␉{␊ |
85 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
86 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
87 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
88 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
89 | ␉␉␉␉␉␉␉␊ |
90 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
91 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
92 | ␉␉␉␉␉␉}␊ |
93 | ␉␉␉␉␉␉␊ |
94 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
95 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
96 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
97 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
98 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform->CPU.FSBFrequency/1000000));␊ |
99 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
100 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
101 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
102 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
103 | ␉␉␉␉␉␉return true;␊ |
104 | ␉␉␉␉␉}␊ |
105 | ␉␉␉␉␉default:␊ |
106 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
107 | ␉␉␉␉}␊ |
108 | ␉␉␉}␊ |
109 | ␉␉␉default:␊ |
110 | ␉␉␉␉break; ␊ |
111 | ␉␉}␊ |
112 | ␉}␊ |
113 | ␉return false;␊ |
114 | }␊ |
115 | ␊ |
116 | static uint16_t simpleGetSMBOemProcessorType(void)␊ |
117 | {␊ |
118 | ␉if (Platform->CPU.NoCores >= 4) ␊ |
119 | ␉{␊ |
120 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
121 | ␉}␊ |
122 | ␉if (((Platform->CPU.NoCores == 1) || (Platform->CPU.NoCores == 2)) && !(platformCPUExtFeature(CPUID_EXTFEATURE_EM64T))) ␊ |
123 | ␉{␊ |
124 | ␉␉return 0x0201;␉// Core Solo / Duo␊ |
125 | ␉};␊ |
126 | ␉␊ |
127 | ␉return 0x0301;␉␉// Core 2 Solo / Duo␊ |
128 | }␊ |
129 | ␊ |
130 | bool getSMBOemProcessorType(returnType *value)␊ |
131 | {␊ |
132 | ␉static bool done = false;␉␉␊ |
133 | ␉␉␊ |
134 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
135 | ␊ |
136 | ␉if (Platform->CPU.Vendor == 0x756E6547) // Intel␊ |
137 | ␉{␊ |
138 | ␉␉if (!done)␊ |
139 | ␉␉{␊ |
140 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform->CPU.BrandString, Platform->CPU.Family, Platform->CPU.Model);␊ |
141 | ␉␉␉done = true;␊ |
142 | ␉␉}␊ |
143 | ␉␉␊ |
144 | ␉␉switch (Platform->CPU.Family) ␊ |
145 | ␉␉{␊ |
146 | ␉␉␉case 0x06:␊ |
147 | ␉␉␉{␊ |
148 | ␉␉␉␉switch (Platform->CPU.Model)␊ |
149 | ␉␉␉␉{␊ |
150 | case CPUID_MODEL_BANIAS:␉// Banias␉␉␊ |
151 | case CPUID_MODEL_DOTHAN:␉// Dothan␉␉␊ |
152 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// Yonah␊ |
153 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// Merom␊ |
154 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉␉// Penryn␊ |
155 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
156 | ␉␉␉␉␉␉return true;␊ |
157 | ␊ |
158 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊ |
159 | ␉␉␉␉␉␉if (strstr(Platform->CPU.BrandString, "Core(TM) i7"))␊ |
160 | value->word = 0x0701;␉// Core i7 ␊ |
161 | ␉␉␉␉␉␉return true;␊ |
162 | ␊ |
163 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊ |
164 | ␉␉␉␉␉␉if (strstr(Platform->CPU.BrandString, "Core(TM) i5"))␊ |
165 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
166 | ␉␉␉␉␉␉else␊ |
167 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊ |
168 | ␉␉␉␉␉␉return true;␊ |
169 | ␊ |
170 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
171 | ␉␉␉␉␉␉if (strstr(Platform->CPU.BrandString, "Core(TM) i5"))␊ |
172 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
173 | ␉␉␉␉␉␉else␊ |
174 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
175 | ␉␉␉␉␉␉return true;␊ |
176 | ␊ |
177 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
178 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
179 | ␉␉␉␉␉␉if (strstr(Platform->CPU.BrandString, "Core(TM) i3"))␊ |
180 | ␉␉␉␉␉␉␉␉value->word = 0x901;␉// Core i3␊ |
181 | ␉␉␉␉␉␉else if (strstr(Platform->CPU.BrandString, "Core(TM) i5"))␊ |
182 | ␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊ |
183 | ␉␉␉␉␉␉else if (strstr(Platform->CPU.BrandString, "Core(TM) i7"))␊ |
184 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊ |
185 | ␉␉␉␉␉␉/*else ␊ |
186 | ␉␉␉␉␉␉␉␉value->word = simpleGetSMBOemProcessorType();*/␊ |
187 | ␉␉␉␉␉␉return true;␊ |
188 | ␊ |
189 | case CPUID_MODEL_JAKETOWN:␊ |
190 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊ |
191 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
192 | ␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Core i7␊ |
193 | ␉␉␉␉␉␉return true;␊ |
194 | ␊ |
195 | ␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
196 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
197 | ␉␉␉␉␉␉return true;␊ |
198 | ␉␉␉␉␉default:␊ |
199 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
200 | ␉␉␉␉}␊ |
201 | ␉␉␉}␊ |
202 | ␉␉␉default:␊ |
203 | ␉␉␉␉break; ␊ |
204 | ␉␉}␊ |
205 | ␉}␊ |
206 | ␉␊ |
207 | ␉return false;␊ |
208 | }␊ |
209 | ␊ |
210 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
211 | {␊ |
212 | ␉static int idx = -1;␊ |
213 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
214 | ␉␉int␉map;␊ |
215 | ␊ |
216 | ␉␉idx++;␊ |
217 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
218 | ␉␉{␊ |
219 | ␉␉␉map = Platform->DMI.DIMM[idx];␊ |
220 | ␉␉␉if (Platform->RAM.DIMM[map].InUse && Platform->RAM.DIMM[map].Type != 0)␊ |
221 | ␉␉␉{␊ |
222 | ␉␉␉␉DBG("RAM Detected Type = %d\n", Platform->RAM.DIMM[map].Type);␊ |
223 | ␉␉␉␉value->byte = Platform->RAM.DIMM[map].Type;␊ |
224 | ␉␉␉␉return true;␊ |
225 | ␉␉␉}␊ |
226 | ␉␉}␊ |
227 | ␉}␊ |
228 | ␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
229 | ␉return true;␊ |
230 | }␊ |
231 | ␊ |
232 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
233 | {␊ |
234 | ␉static int idx = -1;␊ |
235 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
236 | ␉␉int␉map;␊ |
237 | ␊ |
238 | ␉␉idx++;␊ |
239 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
240 | ␉␉{␊ |
241 | ␉␉␉map = Platform->DMI.DIMM[idx];␊ |
242 | ␉␉␉if (Platform->RAM.DIMM[map].InUse && Platform->RAM.DIMM[map].Frequency != 0)␊ |
243 | ␉␉␉{␊ |
244 | ␉␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform->RAM.DIMM[map].Frequency);␊ |
245 | ␉␉␉␉value->dword = Platform->RAM.DIMM[map].Frequency;␊ |
246 | ␉␉␉␉return true;␊ |
247 | ␉␉␉}␊ |
248 | ␉␉}␊ |
249 | ␉}␊ |
250 | ␉value->dword = 800;␊ |
251 | ␉return true;␊ |
252 | }␊ |
253 | ␊ |
254 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
255 | {␊ |
256 | ␉static int idx = -1;␊ |
257 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
258 | ␉␉int␉map;␊ |
259 | ␊ |
260 | ␉␉idx++;␊ |
261 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
262 | ␉␉{␊ |
263 | ␉␉␉map = Platform->DMI.DIMM[idx];␊ |
264 | ␉␉␉if (Platform->RAM.DIMM[map].InUse && strlen(Platform->RAM.DIMM[map].Vendor) > 0)␊ |
265 | ␉␉␉{␊ |
266 | ␉␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform->RAM.DIMM[map].Vendor);␊ |
267 | ␉␉␉␉value->string = Platform->RAM.DIMM[map].Vendor;␊ |
268 | ␉␉␉␉return true;␊ |
269 | ␉␉␉}␊ |
270 | ␉␉}␊ |
271 | ␉}␊ |
272 | ␉value->string = "N/A";␊ |
273 | ␉return true;␊ |
274 | }␊ |
275 | ␉␊ |
276 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
277 | {␊ |
278 | ␉static int idx = -1;␊ |
279 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
280 | ␉␉int␉map;␊ |
281 | ␊ |
282 | ␉␉idx++;␊ |
283 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
284 | ␉␉{␊ |
285 | ␉␉␉map = Platform->DMI.DIMM[idx];␊ |
286 | ␉␉␉if (Platform->RAM.DIMM[map].InUse && strlen(Platform->RAM.DIMM[map].SerialNo) > 0)␊ |
287 | ␉␉␉{␊ |
288 | ␉␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊ |
289 | ␉␉␉␉map, idx, Platform->RAM.DIMM[map].SerialNo);␊ |
290 | ␉␉␉␉value->string = Platform->RAM.DIMM[map].SerialNo;␊ |
291 | ␉␉␉␉return true;␊ |
292 | ␉␉␉}␊ |
293 | ␉␉}␊ |
294 | ␉}␊ |
295 | ␉value->string = "N/A";␊ |
296 | ␉return true;␊ |
297 | }␊ |
298 | ␊ |
299 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
300 | {␊ |
301 | ␉static int idx = -1;␊ |
302 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
303 | ␉␉int␉map;␊ |
304 | ␊ |
305 | ␉␉idx++;␊ |
306 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
307 | ␉␉{␊ |
308 | ␉␉␉map = Platform->DMI.DIMM[idx];␊ |
309 | ␉␉␉if (Platform->RAM.DIMM[map].InUse && strlen(Platform->RAM.DIMM[map].PartNo) > 0)␊ |
310 | ␉␉␉{␊ |
311 | ␉␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform->RAM.DIMM[map].PartNo);␊ |
312 | ␉␉␉␉value->string = Platform->RAM.DIMM[map].PartNo;␊ |
313 | ␉␉␉␉return true;␊ |
314 | ␉␉␉}␊ |
315 | ␉␉}␊ |
316 | ␉}␊ |
317 | ␉value->string = "N/A";␊ |
318 | ␉return true;␊ |
319 | }␊ |
320 | |