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Root/tags/2.0/i386/libsaio/cpu.c

Source at commit 1808 created 12 years 3 months ago.
By blackosx, Revise layout of package installer 'Welcome' file so it looks cleaner. Change the copyright notice to begin from 2009 as seen in the Chameleon 2.0 r431 installer. Should this date be set earlier?
1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
24 */␊
25static uint64_t measure_tsc_frequency(void)␊
26{␊
27␉uint64_t tscStart;␊
28␉uint64_t tscEnd;␊
29␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
30␉unsigned long pollCount;␊
31␉uint64_t retval = 0;␊
32␉int i;␊
33␉␊
34␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
35␉ * counter 2. We run this loop 3 times to make sure the cache␊
36␉ * is hot and we take the minimum delta from all of the runs.␊
37␉ * That is to say that we're biased towards measuring the minimum␊
38␉ * number of TSC ticks that occur while waiting for the timer to␊
39␉ * expire. That theoretically helps avoid inconsistencies when␊
40␉ * running under a VM if the TSC is not virtualized and the host␊
41␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
42␉ */␊
43␉for(i = 0; i < 10; ++i)␊
44␉{␊
45␉␉enable_PIT2();␊
46␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
47␉␉tscStart = rdtsc64();␊
48␉␉pollCount = poll_PIT2_gate();␊
49␉␉tscEnd = rdtsc64();␊
50␉␉/* The poll loop must have run at least a few times for accuracy */␊
51␉␉if (pollCount <= 1)␊
52␉␉␉continue;␊
53␉␉/* The TSC must increment at LEAST once every millisecond.␊
54␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
55␉␉ * be >= 30. Anything less and the processor is way too slow.␊
56␉␉ */␊
57␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
58␉␉␉continue;␊
59␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
60␉␉if ( (tscEnd - tscStart) < tscDelta )␊
61␉␉␉tscDelta = tscEnd - tscStart;␊
62␉}␊
63␉/* tscDelta is now the least number of TSC ticks the processor made in␊
64␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
65␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
66␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
67␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
68␉ * dividing by the milliseconds, we simply multiply by 1000.␊
69␉ */␊
70␉␊
71␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
72␉ * that we're going to multiply by 1000 first so we do need at least some␊
73␉ * arithmetic headroom. For now, 32-bit should be enough.␊
74␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
75␉ */␊
76␉if (tscDelta > (1ULL<<32))␊
77␉␉retval = 0;␊
78␉else␊
79␉{␊
80␉␉retval = tscDelta * 1000 / 30;␊
81␉}␊
82␉disable_PIT2();␊
83␉return retval;␊
84}␊
85␊
86/*␊
87 * Original comment/code:␊
88 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
89 *␊
90 * Measures the Actual Performance Frequency in Hz (64-bit)␊
91 * (just a naming change, mperf --> aperf )␊
92 */␊
93static uint64_t measure_aperf_frequency(void)␊
94{␊
95␉uint64_t aperfStart;␊
96␉uint64_t aperfEnd;␊
97␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
98␉unsigned long pollCount;␊
99␉uint64_t retval = 0;␊
100␉int i;␊
101␉␊
102␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
103␉ * counter 2. We run this loop 3 times to make sure the cache␊
104␉ * is hot and we take the minimum delta from all of the runs.␊
105␉ * That is to say that we're biased towards measuring the minimum␊
106␉ * number of APERF ticks that occur while waiting for the timer to␊
107␉ * expire.␊
108␉ */␊
109␉for(i = 0; i < 10; ++i)␊
110␉{␊
111␉␉enable_PIT2();␊
112␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
113␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
114␉␉pollCount = poll_PIT2_gate();␊
115␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
116␉␉/* The poll loop must have run at least a few times for accuracy */␊
117␉␉if (pollCount <= 1)␊
118␉␉␉continue;␊
119␉␉/* The TSC must increment at LEAST once every millisecond.␊
120␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
121␉␉ * be >= 30. Anything less and the processor is way too slow.␊
122␉␉ */␊
123␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
124␉␉␉continue;␊
125␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
126␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
127␉␉␉aperfDelta = aperfEnd - aperfStart;␊
128␉}␊
129␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
130␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
131␉ */␊
132␉␊
133␉if (aperfDelta > (1ULL<<32))␊
134␉␉retval = 0;␊
135␉else␊
136␉{␊
137␉␉retval = aperfDelta * 1000 / 30;␊
138␉}␊
139␉disable_PIT2();␊
140␉return retval;␊
141}␊
142␊
143/*␊
144 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
145 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
146 *␉ a max multi. (used to calculate the FSB freq.),␊
147 *␉ and a current multi. (used to calculate the CPU freq.)␊
148 * - fsbFrequency = tscFrequency / multi␊
149 * - cpuFrequency = fsbFrequency * multi␊
150 */␊
151void scan_cpu(PlatformInfo_t *p)␊
152{␊
153␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
154␉uint64_t␉msr, flex_ratio;␊
155␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊
156␉const char␉*newratio;␊
157␉int␉␉␉len, myfsb;␊
158␉uint8_t␉␉bus_ratio_min;␊
159␉uint32_t␉max_ratio, min_ratio;␊
160␉␊
161␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊
162␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊
163␉␊
164␉/* get cpuid values */␊
165␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
166␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
167␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
168␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
169␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
170␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
171␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊
172␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
173␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
174␉}␊
175␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
176␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
177␉}␊
178␉␊
179#if DEBUG_CPU␊
180␉{␊
181␉␉int␉␉i;␊
182␉␉printf("CPUID Raw Values:\n");␊
183␉␉for (i=0; i<CPUID_MAX; i++) {␊
184␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
185␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
186␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
187␉␉}␊
188␉}␊
189#endif␊
190␉␊
191␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
192␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
193␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
194␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
195␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
196␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
197␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
198␉␊
199␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
200␉␊
201␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
202␉␉p->CPU.Family == 0x06 &&␊
203␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊
204␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
205␉␉)␊
206␉{␊
207␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
208␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊
209␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊
210␉}␊
211␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
212␉{␊
213␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
214␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
215␉}␊
216␉else␊
217␉{␊
218␉␉// Use previous method for Cores and Threads␊
219␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
220␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
221␉}␊
222␉␊
223␉/* get brand string (if supported) */␊
224␉/* Copyright: from Apple's XNU cpuid.c */␊
225␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
226␉␉uint32_t␉reg[4];␊
227␉␉char␉␉str[128], *s;␊
228␉␉/*␊
229␉␉ * The brand string 48 bytes (max), guaranteed to␊
230␉␉ * be NULL terminated.␊
231␉␉ */␊
232␉␉do_cpuid(0x80000002, reg);␊
233␉␉bcopy((char *)reg, &str[0], 16);␊
234␉␉do_cpuid(0x80000003, reg);␊
235␉␉bcopy((char *)reg, &str[16], 16);␊
236␉␉do_cpuid(0x80000004, reg);␊
237␉␉bcopy((char *)reg, &str[32], 16);␊
238␉␉for (s = str; *s != '\0'; s++) {␊
239␉␉␉if (*s != ' ') break;␊
240␉␉}␊
241␉␉␊
242␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊
243␉␉␊
244␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
245␉␉␉/*␊
246␉␉␉ * This string means we have a firmware-programmable brand string,␊
247␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
248␉␉␉ */␊
249␉␉␉p->CPU.BrandString[0] = '\0';␊
250␉␉}␊
251␉}␊
252␉␊
253␉/* setup features */␊
254␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
255␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
256␉}␊
257␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
258␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
259␉}␊
260␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
261␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
262␉}␊
263␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
264␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
265␉}␊
266␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
267␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
268␉}␊
269␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
270␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
271␉}␊
272␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
273␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
274␉}␊
275␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
276␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
277␉}␊
278␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
279␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
280␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
281␉}␊
282␉␊
283␉tscFrequency = measure_tsc_frequency();␊
284␉fsbFrequency = 0;␊
285␉cpuFrequency = 0;␊
286␉␊
287␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
288␉␉int intelCPU = p->CPU.Model;␊
289␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
290␉␉␉/* Nehalem CPU model */␊
291␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM ||␊
292␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS ||␊
293␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES ||␊
294␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM ||␊
295␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE ||␊
296␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
297␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
298␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDY ||␊
299␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDY_XEON)) {␊
300␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
301␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
302␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
303␉␉␉␉bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
304␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
305␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
306␉␉␉␉if (bitfield(msr, 16, 16)) {␊
307␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊
308␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
309␉␉␉␉␉ where the cpu multipler can't be changed to␊
310␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
311␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊
312␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊
313␉␉␉␉␉ causing the system to crash since tscGranularity␊
314␉␉␉␉␉ is inadvertently set to 0.␊
315␉␉␉␉␉ */␊
316␉␉␉␉␉if (flex_ratio == 0) {␊
317␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
318␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
319␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
320␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
321␉␉␉␉␉} else {␊
322␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
323␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
324␉␉␉␉␉␉}␊
325␉␉␉␉␉}␊
326␉␉␉␉}␊
327␉␉␉␉␊
328␉␉␉␉if (bus_ratio_max) {␊
329␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
330␉␉␉␉}␊
331␉␉␉␉//valv: Turbo Ratio Limit␊
332␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊
333␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
334␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊
335␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
336␉␉␉␉} else {␊
337␉␉␉␉␉cpuFrequency = tscFrequency;␊
338␉␉␉␉}␊
339␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
340␉␉␉␉␉max_ratio = atoi(newratio);␊
341␉␉␉␉␉max_ratio = (max_ratio * 10);␊
342␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
343␉␉␉␉␉␊
344␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
345␉␉␉␉␉␊
346␉␉␉␉␉// extreme overclockers may love 320 ;)␊
347␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
348␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
349␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
350␉␉␉␉␉␉else maxdiv = 0;␊
351␉␉␉␉␉} else {␊
352␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
353␉␉␉␉␉}␊
354␉␉␉␉}␊
355␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
356␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊
357␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
358␉␉␉␉p->CPU.MinRatio = min_ratio;␊
359␉␉␉␉␊
360␉␉␉␉myfsb = fsbFrequency / 1000000;␊
361␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊
362␉␉␉␉currcoef = bus_ratio_max;␊
363␉␉␉} else {␊
364␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
365␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
366␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
367␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
368␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
369␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
370␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
371␉␉␉␉␊
372␉␉␉␉// This will always be model >= 3␊
373␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
374␉␉␉␉{␊
375␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
376␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
377␉␉␉␉} else {␊
378␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
379␉␉␉␉␉/* XXX */␊
380␉␉␉␉␉maxcoef = currcoef;␊
381␉␉␉␉}␊
382␉␉␉␉␊
383␉␉␉␉if (maxcoef) {␊
384␉␉␉␉␉if (maxdiv) {␊
385␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
386␉␉␉␉␉} else {␊
387␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
388␉␉␉␉␉}␊
389␉␉␉␉␉if (currdiv) {␊
390␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
391␉␉␉␉␉} else {␊
392␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
393␉␉␉␉␉}␊
394␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
395␉␉␉␉}␊
396␉␉␉}␊
397␉␉}␊
398␉␉/* Mobile CPU */␊
399␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
400␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
401␉␉}␊
402␉}␊
403␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
404␉{␊
405␉␉switch(p->CPU.ExtFamily)␊
406␉␉{␊
407␉␉␉case 0x00: /* K8 */␊
408␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
409␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
410␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
411␉␉␉␉break;␊
412␉␉␉␉␊
413␉␉␉case 0x01: /* K10 */␊
414␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
415␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
416␉␉␉␉// EffFreq: effective frequency interface␊
417␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
418␉␉␉␉{␊
419␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
420␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
421␉␉␉␉␉cpuFrequency = aperf;␊
422␉␉␉␉}␊
423␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
424␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
425␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
426␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
427␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
428␉␉␉␉␊
429␉␉␉␉break;␊
430␉␉␉␉␊
431␉␉␉case 0x05: /* K14 */␊
432␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
433␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
434␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
435␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
436␉␉␉␉␊
437␉␉␉␉break;␊
438␉␉␉␉␊
439␉␉␉case 0x02: /* K11 */␊
440␉␉␉␉// not implimented␊
441␉␉␉␉break;␊
442␉␉}␊
443␉␉␊
444␉␉if (maxcoef)␊
445␉␉{␊
446␉␉␉if (currdiv)␊
447␉␉␉{␊
448␉␉␉␉if (!currcoef) currcoef = maxcoef;␊
449␉␉␉␉if (!cpuFrequency)␊
450␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
451␉␉␉␉else␊
452␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
453␉␉␉␉␊
454␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
455␉␉␉} else {␊
456␉␉␉␉if (!cpuFrequency)␊
457␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
458␉␉␉␉else ␊
459␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
460␉␉␉␉DBG("%d\n", currcoef);␊
461␉␉␉}␊
462␉␉}␊
463␉␉else if (currcoef)␊
464␉␉{␊
465␉␉␉if (currdiv)␊
466␉␉␉{␊
467␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
468␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
469␉␉␉} else {␊
470␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
471␉␉␉␉DBG("%d\n", currcoef);␊
472␉␉␉}␊
473␉␉}␊
474␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
475␉}␊
476␉␊
477#if 0␊
478␉if (!fsbFrequency) {␊
479␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
480␉␉cpuFrequency = tscFrequency;␊
481␉␉DBG("0 ! using the default value for FSB !\n");␊
482␉}␊
483#endif␊
484␉␊
485␉p->CPU.MaxCoef = maxcoef;␊
486␉p->CPU.MaxDiv = maxdiv;␊
487␉p->CPU.CurrCoef = currcoef;␊
488␉p->CPU.CurrDiv = currdiv;␊
489␉p->CPU.TSCFrequency = tscFrequency;␊
490␉p->CPU.FSBFrequency = fsbFrequency;␊
491␉p->CPU.CPUFrequency = cpuFrequency;␊
492␉␊
493␉// keep formatted with spaces instead of tabs␊
494␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊
495 DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
496 DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
497 DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊
498 DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊
499 DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊
500 DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊
501 DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊
502 DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
503 DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
504#if DEBUG_CPU␊
505␉pause();␊
506#endif␊
507}␊
508

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