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Root/tags/2.0/i386/libsaio/platform.h

Source at commit 1808 created 12 years 3 months ago.
By blackosx, Revise layout of package installer 'Welcome' file so it looks cleaner. Change the copyright notice to begin from 2009 as seen in the Chameleon 2.0 r431 installer. Should this date be set earlier?
1/*
2 * platform.h
3 * AsereBLN: reworked and extended
4 *
5 */
6
7#ifndef __LIBSAIO_PLATFORM_H
8#define __LIBSAIO_PLATFORM_H
9
10//#include "libsaio.h"
11
12extern bool platformCPUFeature(uint32_t);
13extern void scan_platform(void);
14extern void dumpPhysAddr(const char * title, void * a, int len);
15
16/* CPUID Vendor */
17#define CPUID_VENDOR_INTEL 0x756E6547
18#define CPUID_VENDOR_AMD 0x68747541
19
20/* CPUID index into cpuid_raw */
21#define CPUID_00
22#define CPUID_11
23#define CPUID_22
24#define CPUID_33
25#define CPUID_44
26#define CPUID_65
27#define CPUID_806
28#define CPUID_817
29#define CPUID_888
30#define CPUID_MAX9
31
32#define CPU_MODEL_DOTHAN0x0D// Dothan
33#define CPU_MODEL_YONAH0x0E// Sossaman, Yonah
34#define CPU_MODEL_MEROM0x0F// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom
35#define CPU_MODEL_PENRYN0x17// Wolfdale, Yorkfield, Harpertown, Penryn
36#define CPU_MODEL_NEHALEM0x1A// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown
37#define CPU_MODEL_ATOM0x1C// Atom
38#define CPU_MODEL_FIELDS0x1E// Lynnfield, Clarksfield, Jasper Forest
39#define CPU_MODEL_DALES0x1F// Havendale, Auburndale
40#define CPU_MODEL_DALES_32NM0x25// Clarkdale, Arrandale
41#define CPU_MODEL_SANDY0x2A// Sandy Bridge
42#define CPU_MODEL_WESTMERE0x2C// Gulftown, Westmere-EP, Westmere-WS
43#define CPU_MODEL_SANDY_XEON0x2D// Sandy Bridge Xeon
44#define CPU_MODEL_NEHALEM_EX0x2E// Beckton
45#define CPU_MODEL_WESTMERE_EX0x2F
46
47/* CPU Features */
48#define CPU_FEATURE_MMX0x00000001// MMX Instruction Set
49#define CPU_FEATURE_SSE0x00000002// SSE Instruction Set
50#define CPU_FEATURE_SSE20x00000004// SSE2 Instruction Set
51#define CPU_FEATURE_SSE30x00000008// SSE3 Instruction Set
52#define CPU_FEATURE_SSE410x00000010// SSE41 Instruction Set
53#define CPU_FEATURE_SSE420x00000020// SSE42 Instruction Set
54#define CPU_FEATURE_EM64T0x00000040// 64Bit Support
55#define CPU_FEATURE_HTT0x00000080// HyperThreading
56#define CPU_FEATURE_MOBILE0x00000100// Mobile CPU
57#define CPU_FEATURE_MSR0x00000200// MSR Support
58
59/* SMBIOS Memory Types */
60#define SMB_MEM_TYPE_UNDEFINED0
61#define SMB_MEM_TYPE_OTHER1
62#define SMB_MEM_TYPE_UNKNOWN2
63#define SMB_MEM_TYPE_DRAM3
64#define SMB_MEM_TYPE_EDRAM4
65#define SMB_MEM_TYPE_VRAM5
66#define SMB_MEM_TYPE_SRAM6
67#define SMB_MEM_TYPE_RAM7
68#define SMB_MEM_TYPE_ROM8
69#define SMB_MEM_TYPE_FLASH9
70#define SMB_MEM_TYPE_EEPROM10
71#define SMB_MEM_TYPE_FEPROM11
72#define SMB_MEM_TYPE_EPROM12
73#define SMB_MEM_TYPE_CDRAM13
74#define SMB_MEM_TYPE_3DRAM14
75#define SMB_MEM_TYPE_SDRAM15
76#define SMB_MEM_TYPE_SGRAM16
77#define SMB_MEM_TYPE_RDRAM17
78#define SMB_MEM_TYPE_DDR18
79#define SMB_MEM_TYPE_DDR219
80#define SMB_MEM_TYPE_FBDIMM20
81#define SMB_MEM_TYPE_DDR324// Supported in 10.5.6+ AppleSMBIOS
82
83/* Memory Configuration Types */
84#define SMB_MEM_CHANNEL_UNKNOWN0
85#define SMB_MEM_CHANNEL_SINGLE1
86#define SMB_MEM_CHANNEL_DUAL2
87#define SMB_MEM_CHANNEL_TRIPLE3
88
89/* Maximum number of ram slots */
90#define MAX_RAM_SLOTS8
91#define RAM_SLOT_ENUMERATOR{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}
92
93/* Maximum number of SPD bytes */
94#define MAX_SPD_SIZE256
95
96/* Size of SMBIOS UUID in bytes */
97#define UUID_LEN16
98
99typedef struct _RamSlotInfo_t {
100 uint32_tModuleSize;// Size of Module in MB
101 uint32_tFrequency;// in Mhz
102 const char*Vendor;
103 const char*PartNo;
104 const char*SerialNo;
105 char*spd;// SPD Dump
106 boolInUse;
107 uint8_tType;
108 uint8_tBankConnections;// table type 6, see (3.3.7)
109 uint8_tBankConnCnt;
110} RamSlotInfo_t;
111
112typedef struct _PlatformInfo_t {
113struct CPU {
114uint32_tFeatures;// CPU Features like MMX, SSE2, VT, MobileCPU
115uint32_tVendor;// Vendor
116uint32_tSignature;// Signature
117uint32_tStepping;// Stepping
118uint32_tModel;// Model
119uint32_tExtModel;// Extended Model
120uint32_tFamily;// Family
121uint32_tExtFamily;// Extended Family
122uint32_tNoCores;// No Cores per Package
123uint32_tNoThreads;// Threads per Package
124uint8_tMaxCoef;// Max Multiplier
125uint8_tMaxDiv;
126uint8_tCurrCoef;// Current Multiplier
127uint8_tCurrDiv;
128uint64_tTSCFrequency;// TSC Frequency Hz
129uint64_tFSBFrequency;// FSB Frequency Hz
130uint64_tCPUFrequency;// CPU Frequency Hz
131uint32_tMaxRatio;// Max Bus Ratio
132uint32_tMinRatio;// Min Bus Ratio
133charBrandString[48];// 48 Byte Branding String
134uint32_tCPUID[CPUID_MAX][4];// CPUID 0..4, 80..81 Raw Values
135} CPU;
136
137struct RAM {
138uint64_tFrequency;// Ram Frequency
139uint32_tDivider;// Memory divider
140uint8_tCAS;// CAS 1/2/2.5/3/4/5/6/7
141uint8_tTRC;
142uint8_tTRP;
143uint8_tRAS;
144uint8_tChannels;// Channel Configuration Single,Dual or Triple
145uint8_tNoSlots;// Maximum no of slots available
146uint8_tType;// Standard SMBIOS v2.5 Memory Type
147RamSlotInfo_tDIMM[MAX_RAM_SLOTS];// Information about each slot
148} RAM;
149
150struct DMI {
151intMaxMemorySlots;// number of memory slots populated by SMBIOS
152intCntMemorySlots;// number of memory slots counted
153intMemoryModules;// number of memory modules installed
154intDIMM[MAX_RAM_SLOTS];// Information and SPD mapping for each slot
155} DMI;
156
157uint8_tType; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)
158uint8_t*UUID;
159} PlatformInfo_t;
160
161extern PlatformInfo_t Platform;
162
163#endif /* !__LIBSAIO_PLATFORM_H */
164

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