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Root/tags/2.0/i386/modules/Resolution/915resolution.c

Source at commit 1808 created 12 years 4 months ago.
By blackosx, Revise layout of package installer 'Welcome' file so it looks cleaner. Change the copyright notice to begin from 2009 as seen in the Chameleon 2.0 r431 installer. Should this date be set earlier?
1/*␊
2 * resolution.h␊
3 * ␊
4 *␉NOTE: I don't beleive this code is production ready / should be in trunk␊
5 * Atleast, not in it's current state. ␊
6 *␊
7 * Created by Evan Lojewski on 3/4/10.␊
8 * Copyright 2009. All rights reserved.␊
9 *␊
10 */␊
11#ifndef _RESOLUTION_H_␊
12#define _RESOLUTION_H_␊
13␊
14//#include "libsaio.h"␊
15//#include "edid.h" //included␊
16#include "915resolution.h"␊
17␊
18␊
19void patchVideoBios()␊
20{␉␉␊
21␉UInt32 x = 0, y = 0, bp = 0;␊
22␉␊
23␉getResolution(&x, &y, &bp);␊
24␉verbose("getResolution: %dx%dx%d\n", (int)x, (int)y, (int)bp);␊
25␉␊
26␉if (x != 0 &&␊
27␉␉y != 0 && ␊
28␉␉bp != 0)␊
29␉{␊
30␉␉vbios_map * map;␊
31␉␉␊
32␉␉map = open_vbios(CT_UNKNOWN);␊
33␉␉if(map)␊
34␉␉{␊
35␉␉␉unlock_vbios(map);␊
36␉␉␉␊
37␉␉␉set_mode(map, x, y, bp, 0, 0);␊
38␉␉␉␊
39␉␉␉relock_vbios(map);␊
40␉␉␉␊
41␉␉␉close_vbios(map);␊
42␉␉}␊
43␉}␊
44}␊
45␊
46␊
47/* Copied from 915 resolution created by steve tomljenovic␊
48 *␊
49 * This code is based on the techniques used in :␊
50 *␊
51 * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊
52 * for demonstrating how to shadow the VBIOS into system RAM␊
53 * and then modify it.␊
54 *␊
55 * - 1280patch by Andrew Tipton (andrewtipton null li).␊
56 *␊
57 * - 855resolution by Alain Poirier␊
58 *␊
59 * This source code is into the public domain.␊
60 */␊
61␊
62/**␊
63 **␊
64 **/␊
65␊
66#define CONFIG_MECH_ONE_ADDR␉0xCF8␊
67#define CONFIG_MECH_ONE_DATA␉0xCFC␊
68␊
69int freqs[] = { 60, 75, 85 };␊
70␊
71UInt32 get_chipset_id(void)␊
72{␊
73␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊
74␉return inl(CONFIG_MECH_ONE_DATA);␊
75}␊
76␊
77chipset_type get_chipset(UInt32 id)␊
78{␊
79␉chipset_type type;␊
80␉␉␊
81␉switch (id) {␊
82␉␉case 0x35758086:␊
83␉␉␉type = CT_830;␊
84␉␉␉break;␊
85␉␉␉␊
86␉␉case 0x25608086:␊
87␉␉␉type = CT_845G;␊
88␉␉␉break;␊
89␉␉␉␊
90␉␉case 0x35808086:␊
91␉␉␉type = CT_855GM;␊
92␉␉␉break;␊
93␉␉␉␊
94␉␉case 0x25708086:␊
95␉␉␉type = CT_865G;␊
96␉␉␉break;␊
97␉␉␉␊
98␉␉case 0x25808086:␊
99␉␉␉type = CT_915G;␊
100␉␉␉break;␊
101␉␉␉␊
102␉␉case 0x25908086:␊
103␉␉␉type = CT_915GM;␊
104␉␉␉break;␊
105␉␉␉␊
106␉␉case 0x27708086:␊
107␉␉␉type = CT_945G;␊
108␉␉␉break;␊
109␉␉␉␊
110␉␉case 0x27a08086:␊
111␉␉␉type = CT_945GM;␊
112␉␉␉break;␊
113␉␉␉␊
114␉␉case 0x27ac8086:␊
115␉␉␉type = CT_945GME;␊
116␉␉␉break;␊
117␉␉␉␊
118␉␉case 0x29708086:␊
119␉␉␉type = CT_946GZ;␊
120␉␉␉break;␊
121␉␉␉␊
122␉␉case 0x27748086:␊
123␉␉␉type = CT_955X;␊
124␉␉␉break;␊
125␉␉␉␊
126␉␉case 0x277c8086:␊
127␉␉␉type = CT_975X;␊
128␉␉␉break;␊
129␊
130␉␉case 0x29a08086:␊
131␉␉␉type = CT_G965;␊
132␉␉␉break;␊
133␉␉␉␊
134␉␉case 0x29908086:␊
135␉␉␉type = CT_Q965;␊
136␉␉␉break;␊
137␉␉␉␊
138␉␉case 0x81008086:␊
139␉␉␉type = CT_500;␊
140␉␉␉break;␊
141␉␉␉␊
142␉␉case 0x2e108086:␊
143␉␉case 0X2e908086:␊
144␉␉␉type = CT_B43;␊
145␉␉␉break;␊
146␊
147␉␉case 0x2e208086:␊
148␉␉␉type = CT_P45;␊
149␉␉␉break;␊
150␊
151␉␉case 0x2e308086:␊
152␉␉␉type = CT_G41;␊
153␉␉␉break;␊
154␉␉␉␉␉␊
155␉␉case 0x29c08086:␊
156␉␉␉type = CT_G31;␊
157␉␉␉break;␊
158␉␉␉␊
159␉␉case 0x29208086:␊
160␉␉␉type = CT_G45;␊
161␉␉␉break;␊
162␉␉␉␊
163␉␉case 0xA0108086:␉// mobile␊
164␉␉case 0xA0008086:␉// desktop␊
165␉␉␉type = CT_3150;␊
166␉␉␉break;␊
167␉␉␉␊
168␉␉case 0x2a008086:␊
169␉␉␉type = CT_965GM;␊
170␉␉␉break;␊
171␉␉␉␊
172␉␉case 0x29e08086:␊
173␉␉␉type = CT_X48;␊
174␉␉␉break;␉␉␉␊
175␉␉␉␉␊
176␉␉case 0x2a408086:␊
177␉␉␉type = CT_GM45;␊
178␉␉␉break;␊
179␉␉␉␊
180␉␉␉␊
181␉␉default:␊
182␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊
183␉␉␉{␊
184␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊
185␉␉␉␉//getc();␊
186␉␉␉␉type = CT_UNKNOWN_INTEL;␊
187␉␉␉␉//type = CT_UNKNOWN;␊
188␊
189␉␉␉}␊
190␉␉␉else␊
191␉␉␉{␊
192␉␉␉␉type = CT_UNKNOWN;␊
193␉␉␉}␊
194␉␉␉break;␊
195␉}␊
196␉return type;␊
197}␊
198␊
199vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊
200{␊
201␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊
202␉return ptr;␊
203}␊
204␊
205vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊
206{␊
207␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊
208␉return ptr;␊
209}␊
210␊
211vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊
212{␊
213␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊
214␉return ptr;␊
215}␊
216␊
217char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊
218{␊
219␉UInt32 i;␊
220␉UInt16 r1, r2;␊
221␉␊
222␉r1 = r2 = 32000;␊
223␉␊
224␉for (i=0; i < map->mode_table_size; i++)␊
225␉{␊
226␉␉if (map->mode_table[i].resolution <= r1)␊
227␉␉{␊
228␉␉␉r1 = map->mode_table[i].resolution;␊
229␉␉}␊
230␉␉else␊
231␉␉{␊
232␉␉␉if (map->mode_table[i].resolution <= r2)␊
233␉␉␉{␊
234␉␉␉␉r2 = map->mode_table[i].resolution;␊
235␉␉␉}␊
236␉␉}␊
237␉␉␊
238␉␉/*printf("r1 = %d r2 = %d\n", r1, r2);*/␊
239␉}␊
240␉␊
241␉return (r2-r1-6) % entry_size == 0;␊
242}␊
243␊
244void close_vbios(vbios_map * map);␊
245␊
246char detect_ati_bios_type(vbios_map * map)␊
247{␉␊
248␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊
249}␊
250␊
251␊
252vbios_map * open_vbios(chipset_type forced_chipset)␊
253{␊
254␉UInt32 z;␊
255␉vbios_map * map = malloc(sizeof(vbios_map));␊
256␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊
257␉/*␊
258␉ * Determine chipset␊
259␉ */␊
260␉␊
261␉if (forced_chipset == CT_UNKNOWN)␊
262␉{␊
263␉␉map->chipset_id = get_chipset_id();␊
264␉␉map->chipset = get_chipset(map->chipset_id);␊
265␉}␊
266␉else if (forced_chipset != CT_UNKNOWN)␊
267␉{␊
268␉␉map->chipset = forced_chipset;␊
269␉}␊
270␉␊
271␉␊
272␉if (map->chipset == CT_UNKNOWN)␊
273␉{␊
274␉␉//verbose("Unknown chipset type.\n");␊
275␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊
276␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊
277␉␉close_vbios(map);␊
278␉␉return 0;␊
279␉}␊
280␉␊
281␉␊
282␉/*␊
283␉ * Map the video bios to memory␊
284␉ */␊
285␉map->bios_ptr=(char*)VBIOS_START;␊
286␉␊
287␉/*␊
288␉ * check if we have ATI Radeon␊
289␉ */␊
290␉map->ati_tables.base = map->bios_ptr;␊
291␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊
292␉if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)␊
293␉{␊
294␉␉// ATI Radeon Card␊
295␉␉map->bios = BT_ATI_1;␊
296␉␉␊
297␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊
298␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊
299␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊
300␉␉␊
301␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊
302␉␉if (map->ati_mode_table == 0)␊
303␉␉{␊
304␉␉␉printf("Unable to locate the mode table.\n");␊
305␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
306␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
307␉␉␉printf("Chipset: %d\n", map->chipset);␊
308␉␉␉close_vbios(map);␊
309␉␉␉return 0;␊
310␉␉}␊
311␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊
312␉␉␊
313␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊
314␉␉␊
315␉}␊
316␉else {␊
317␉␉␊
318␉␉/*␊
319␉␉ * check if we have NVIDIA␊
320␉␉ */␊
321␊
322␉␉int i = 0;␊
323␉␉while (i < 512)␊
324␉␉{ // we don't need to look through the whole bios, just the first 512 bytes␊
325␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊
326␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊
327␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊
328␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊
329␉␉␉{␊
330␉␉␉␉map->bios = BT_NVDA;␊
331␉␉␉␉unsigned short nv_data_table_offset = 0;␊
332␉␉␉␉unsigned short * nv_data_table;␊
333␉␉␉␉NV_VESA_TABLE * std_vesa;␊
334␉␉␉␉␊
335␉␉␉␉int i = 0;␊
336␉␉␉␉␊
337␉␉␉␉while (i < 0x300)␊
338␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊
339␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊
340␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊
341␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊
342␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊
343␉␉␉␉␉{␊
344␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊
345␉␉␉␉␉␉break;␊
346␉␉␉␉␉}␊
347␉␉␉␉␉i++;␊
348␉␉␉␉}␊
349␉␉␉␉␊
350␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊
351␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊
352␉␉␉␉␊
353␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊
354␉␉␉␉if (map->nv_mode_table == 0)␊
355␉␉␉␉{␊
356␉␉␉␉␉printf("Unable to locate the mode table.\n");␊
357␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊
358␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊
359␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊
360␉␉␉␉␉close_vbios(map);␊
361␉␉␉␉␉return 0;␊
362␉␉␉␉}␊
363␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊
364␉␉␉␉␊
365␉␉␉␉break;␊
366␉␉␉}␊
367␉␉␉i++;␊
368␉␉}␊
369␉}␊
370␉␊
371␉␊
372␉/*␊
373␉ * check if we have Intel␊
374␉ */␊
375␉␊
376␉/*if (map->chipset == CT_UNKNOWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊
377␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊
378␉ ␊
379␉ printf("Chipset Id: %x\n", map->chipset_id);␊
380␉ ␊
381␉ printf("Please report this problem to stomljen@yahoo.com\n");␊
382␉ ␊
383␉ close_vbios(map);␊
384␉ return 0;␊
385␉ }*/␊
386␉␊
387␉/*␊
388␉ * check for others␊
389␉ */␊
390␉␊
391␊
392␉␊
393␉/*␊
394␉ * Figure out where the mode table is ␊
395␉ */␊
396␉if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA)) ␊
397␉{␊
398␉␉char* p = map->bios_ptr + 16;␊
399␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊
400␉␉␊
401␉␉while (p < limit && map->mode_table == 0)␊
402␉␉{␊
403␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊
404␉␉␉␊
405␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊
406␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊
407␉␉␉{␊
408␉␉␉␉map->mode_table = mode_ptr;␊
409␉␉␉}␊
410␉␉␉␊
411␉␉␉p++;␊
412␉␉}␊
413␉␉␊
414␉␉if (map->mode_table == 0) ␊
415␉␉{␊
416␉␉␉close_vbios(map);␊
417␉␉␉return 0;␊
418␉␉}␊
419␉}␊
420␉␊
421␉␊
422␉/*␊
423␉ * Determine size of mode table␊
424␉ */␊
425␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
426␉{␊
427␉␉vbios_mode * mode_ptr = map->mode_table;␊
428␉␉␊
429␉␉while (mode_ptr->mode != 0xff)␊
430␉␉{␊
431␉␉␉map->mode_table_size++;␊
432␉␉␉mode_ptr++;␊
433␉␉}␊
434␉}␊
435␉␊
436␉/*␊
437␉ * Figure out what type of bios we have␊
438␉ * order of detection is important␊
439␉ */␊
440␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊
441␉{␊
442␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊
443␉␉{␊
444␉␉␉map->bios = BT_3;␊
445␉␉}␊
446␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊
447␉␉{␊
448␉␉␉map->bios = BT_2;␊
449␉␉}␊
450␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊
451␉␉{␊
452␉␉␉map->bios = BT_1;␊
453␉␉}␊
454␉␉else {␊
455␉␉␉return 0;␊
456␉␉}␊
457␉}␊
458␉␊
459␉return map;␊
460}␊
461␊
462void close_vbios(vbios_map * map)␊
463{␊
464␉free(map);␊
465}␊
466␊
467void unlock_vbios(vbios_map * map)␊
468{␊
469␉␊
470␉map->unlocked = TRUE;␊
471␊
472␉switch (map->chipset) {␊
473␉␉case CT_UNKNOWN:␊
474␉␉␉break;␊
475␉␉case CT_830:␊
476␉␉case CT_855GM:␊
477␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
478␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊
479␉␉␉␊
480␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
481␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
482␉␉␉break;␊
483␉␉case CT_845G:␊
484␉␉case CT_865G:␊
485␉␉case CT_915G:␊
486␉␉case CT_915GM:␊
487␉␉case CT_945G:␊
488␉␉case CT_945GM:␊
489␉␉case CT_945GME:␊
490␉␉case CT_946GZ:␊
491␉␉case CT_G965:␊
492␉␉case CT_Q965:␊
493␉␉case CT_965GM:␊
494␉␉case CT_975X:␊
495␉␉case CT_P35:␊
496␉␉case CT_955X:␊
497␉␉case CT_X48:␊
498␉␉case CT_B43:␊
499␉␉case CT_Q45:␊
500␉␉case CT_P45:␊
501␉␉case CT_GM45:␊
502␉␉case CT_G45:␊
503␉␉case CT_G41:␊
504␉␉case CT_G31:␊
505␉␉case CT_500:␊
506␉␉case CT_3150:␊
507␉␉case CT_UNKNOWN_INTEL:␉// Assume newer intel chipset is the same as before␊
508␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
509␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊
510␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊
511␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
512␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊
513␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊
514␉␉␉break;␊
515␉}␊
516␉␊
517#if DEBUG␊
518␉{␊
519␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
520␉␉verbose("unlock PAM: (0x%08x)\n", t);␊
521␉}␊
522#endif␊
523}␊
524␊
525void relock_vbios(vbios_map * map)␊
526{␊
527␉␊
528␉map->unlocked = FALSE;␊
529␉␊
530␉switch (map->chipset)␊
531␉{␊
532␉␉case CT_UNKNOWN:␊
533␉␉␉break;␊
534␉␉case CT_830:␊
535␉␉case CT_855GM:␊
536␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊
537␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊
538␉␉␉break;␊
539␉␉case CT_845G:␊
540␉␉case CT_865G:␊
541␉␉case CT_915G:␊
542␉␉case CT_915GM:␊
543␉␉case CT_945G:␊
544␉␉case CT_945GM:␊
545␉␉case CT_945GME:␊
546␉␉case CT_946GZ:␊
547␉␉case CT_G965:␊
548␉␉case CT_955X:␊
549␉␉case CT_G45:␊
550␉␉case CT_Q965:␊
551␉␉case CT_965GM:␊
552␉␉case CT_975X:␊
553␉␉case CT_P35:␊
554␉␉case CT_X48:␊
555␉␉case CT_B43:␊
556␉␉case CT_Q45:␊
557␉␉case CT_P45:␊
558␉␉case CT_GM45:␊
559␉␉case CT_G41:␊
560␉␉case CT_G31:␊
561␉␉case CT_500:␊
562␉␉case CT_3150:␊
563␉␉case CT_UNKNOWN_INTEL:␊
564␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊
565␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊
566␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊
567␉␉␉break;␊
568␉}␊
569␉␊
570#if DEBUG␊
571␉{␊
572 UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊
573␉␉verbose("relock PAM: (0x%08x)\n", t);␊
574␉}␊
575#endif␊
576}␊
577␊
578␊
579int getMode(edid_mode *mode)␊
580{␊
581␉char* edidInfo = readEDID();␊
582␉␉␉␊
583␉if(!edidInfo) return 1;␊
584//Slice␊
585␉if(!fb_parse_edid((struct EDID *)edidInfo, mode)) ␊
586␉{␊
587␉␉free( edidInfo );␊
588␉␉return 1;␊
589␉}␊
590/*␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊
591␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊
592␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊
593␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊
594␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊
595␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊
596␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊
597␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊
598␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊
599*/␉␉␊
600␉␉␊
601␉free( edidInfo );␊
602␉␉␊
603␉if(!mode->h_active) return 1;␊
604␉␊
605␉return 0;␊
606␉␉␊
607}␊
608␊
609␊
610static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊
611␉␉␉␉␉␉unsigned long *clock,␊
612␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊
613␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊
614{␊
615␉UInt32 hbl, vbl, vfreq;␊
616␉␊
617␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊
618␉vfreq = vbl * freq;␊
619␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊
620␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊
621␉␊
622␉*vsyncstart = y;␊
623␉*vsyncend = y + 3;␊
624␉*vblank = vbl - 1;␊
625␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊
626␉*hsyncend = x + hbl / 2 - 1;␊
627␉*hblank = x + hbl - 1;␊
628␉*clock = (x + hbl) * vfreq / 1000;␊
629}␊
630␊
631void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊
632␉UInt32 xprev, yprev;␊
633␉UInt32 i = 0, j;␊
634␉// patch first available mode␊
635␉␊
636␉//␉for (i=0; i < map->mode_table_size; i++) {␊
637␉//␉␉if (map->mode_table[0].mode == mode) {␊
638␉switch(map->bios) {␊
639␉␉case BT_INTEL:␊
640␉␉␉return;␊
641␊
642␉␉case BT_1:␊
643␉␉{␊
644␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊
645␉␉␉␊
646␉␉␉if (bp) {␊
647␉␉␉␉map->mode_table[i].bits_per_pixel = bp;␊
648␉␉␉}␊
649␉␉␉␊
650␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊
651␉␉␉res->x1 = (x & 0xff);␊
652␉␉␉␊
653␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊
654␉␉␉res->y1 = (y & 0xff);␊
655␉␉␉if (htotal)␊
656␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊
657␉␉␉␊
658␉␉␉if (vtotal)␊
659␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊
660␉␉␉␊
661␉␉␉break;␊
662␉␉}␊
663␉␉case BT_2:␊
664␉␉{␊
665␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊
666␉␉␉␊
667␉␉␉res->xchars = x / 8;␊
668␉␉␉res->ychars = y / 16 - 1;␊
669␉␉␉xprev = res->modelines[0].x1;␊
670␉␉␉yprev = res->modelines[0].y1;␊
671␉␉␉␊
672␉␉␉for(j=0; j < 3; j++) {␊
673␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊
674␉␉␉␉␊
675␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
676␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
677␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
678␉␉␉␉␉␊
679␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
680␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
681␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
682␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
683␉␉␉␉␉␊
684␉␉␉␉␉if (htotal)␊
685␉␉␉␉␉␉modeline->htotal = htotal;␊
686␉␉␉␉␉else␊
687␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
688␉␉␉␉␉␊
689␉␉␉␉␉if (vtotal)␊
690␉␉␉␉␉␉modeline->vtotal = vtotal;␊
691␉␉␉␉␉else␊
692␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
693␉␉␉␉}␊
694␉␉␉}␊
695␉␉␉break;␊
696␉␉}␊
697␉␉case BT_3:␊
698␉␉{␊
699␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊
700␉␉␉␊
701␉␉␉xprev = res->modelines[0].x1;␊
702␉␉␉yprev = res->modelines[0].y1;␊
703␉␉␉␊
704␉␉␉for (j=0; j < 3; j++) {␊
705␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊
706␉␉␉␉␊
707␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊
708␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊
709␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊
710␉␉␉␉␉␊
711␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊
712␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊
713␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊
714␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊
715␉␉␉␉␉if (htotal)␊
716␉␉␉␉␉␉modeline->htotal = htotal;␊
717␉␉␉␉␉else␊
718␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊
719␉␉␉␉␉if (vtotal)␊
720␉␉␉␉␉␉modeline->vtotal = vtotal;␊
721␉␉␉␉␉else␊
722␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊
723␉␉␉␉␉␊
724␉␉␉␉␉modeline->timing_h = y-1;␊
725␉␉␉␉␉modeline->timing_v = x-1;␊
726␉␉␉␉}␊
727␉␉␉}␊
728␉␉␉break;␊
729␉␉}␊
730␉␉case BT_ATI_1:␊
731␉␉{␊
732␉␉␉edid_mode mode;␊
733␉␉␉␉␊
734␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊
735␊
736␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊
737␉␉␉if (!getMode(&mode)) {␊
738␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊
739␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊
740␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊
741␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊
742␉␉␉␉␉␊
743␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊
744␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊
745␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊
746␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊
747␊
748␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊
749␉␉␉}␊
750␉␉␉/*else␊
751␉␉␉{␊
752␉␉␉␉vbios_modeline_type2 modeline;␊
753␊
754␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
755␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
756␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
757␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
758␊
759␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊
760␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊
761␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊
762␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
763␊
764␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊
765␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊
766␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊
767␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊
768␉␉␉␉␉␉␉␉␉␉␉␉␊
769␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊
770␉␉␉ }*/␊
771␉␊
772␉␉␉break;␊
773␉␉}␊
774␉␉case BT_ATI_2:␊
775␉␉{␊
776␉␉␉edid_mode mode;␊
777␉␉␉␉␉␉␊
778␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊
779␉␉␉␊
780␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
781␉␉␉if (!getMode(&mode)) {␊
782␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊
783␉␉␉␉mode_timing->usHActive = mode.h_active;␊
784␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊
785␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊
786␉␉␉␉␉␉␉␉␉␉␊
787␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊
788␉␉␉␉mode_timing->usVActive = mode.v_active;␊
789␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊
790␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊
791␉␉␉␉␉␉␉␉␉␉␊
792␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊
793␉␉␉}␊
794␉␉␉/*else␊
795␉␉␉{␊
796␉␉␉␉vbios_modeline_type2 modeline;␊
797␉␉␉␊
798␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊
799␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊
800␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊
801␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊
802␉␉␉␉␉␉␉␉␉␉␉␊
803␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊
804␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHActive = x;␊
805␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊
806␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
807␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
808␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊
809␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVActive = y;␊
810␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊
811␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊
812␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊
813␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊
814␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉}*/␊
815␉␉␉␉␊
816␉␉␉␊
817␉␉␉break;␊
818␉␉}␊
819␉␉case BT_NVDA:␊
820␉␉{␊
821␉␉␉edid_mode mode;␊
822␉␉␉␊
823␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊
824␉␉␉␊
825␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊
826␉␉␉if (!getMode(&mode)) {␊
827␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊
828␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊
829␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊
830␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊
831␉␉␉␉␊
832␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊
833␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊
834␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊
835␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊
836␉␉␉␉␊
837␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊
838␉␉␉}␊
839␉␉␉/*else␊
840␉␉␉ {␊
841␉␉␉ vbios_modeline_type2 modeline;␊
842␉␉␉ ␊
843␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊
844␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊
845␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊
846␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊
847␉␉␉ ␊
848␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊
849␉␉␉ mode_timing[i].usH_Active = x;␊
850␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊
851␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊
852␉␉␉ ␊
853␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊
854␉␉␉ mode_timing[i].usV_Active = y;␊
855␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊
856␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊
857␉␉␉ ␊
858␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊
859␉␉␉ }*/␊
860␉␉␉break;␊
861␉␉}␊
862␉␉case BT_UNKNOWN:␊
863␉␉{␊
864␉␉␉break;␊
865␉␉}␊
866␉}␊
867␉//␉␉}␊
868␉//␉}␊
869}␊
870␊
871#endif // _RESOLUTION_H_

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