1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␉␉␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's. ␊ |
34 | ␉␉␉␉␉case CPU_MODEL_SANDY_XEON: ␊ |
35 | ␉␉␉␉␉case CPU_MODEL_SANDY:␊ |
36 | ␉␉␉␉␉␉value->word = 0;␊ |
37 | ␉␉␉␉␉␉break;␊ |
38 | ␉␉␉␉␉default:␊ |
39 | ␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
40 | ␉␉␉␉}␊ |
41 | ␉␉␉}␊ |
42 | ␉␉␉␉break;␊ |
43 | ␉␉␉␉␊ |
44 | ␉␉␉default:␊ |
45 | ␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
46 | ␉␉}␊ |
47 | ␉}␊ |
48 | ␉else␊ |
49 | ␉{␊ |
50 | ␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
51 | ␉}␊ |
52 | ␊ |
53 | ␉return true;␊ |
54 | }␊ |
55 | ␊ |
56 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
57 | {␊ |
58 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
59 | ␉return true;␊ |
60 | }␊ |
61 | ␊ |
62 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
63 | {␊ |
64 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
65 | ␉{␉␉␊ |
66 | ␉␉switch (Platform.CPU.Family) ␊ |
67 | ␉␉{␊ |
68 | ␉␉␉case 0x06:␊ |
69 | ␉␉␉{␊ |
70 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
71 | ␉␉␉␉{␊ |
72 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
73 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
74 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
75 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
76 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
77 | ␉␉␉␉␉␉return false;␊ |
78 | ␊ |
79 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
80 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
81 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
82 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
83 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
84 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
85 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
86 | ␉␉␉␉␉{␊ |
87 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
88 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
89 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
90 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
91 | ␉␉␉␉␉␉int i;␊ |
92 | ␉␉␉␉␉␉␊ |
93 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
94 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
95 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
96 | ␉␉␉␉␉␉{␊ |
97 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
98 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
99 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
100 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
101 | ␉␉␉␉␉␉␉␊ |
102 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
103 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
104 | ␉␉␉␉␉␉}␊ |
105 | ␉␉␉␉␉␉␊ |
106 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
107 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
108 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
109 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
110 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
111 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
112 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
113 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
114 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
115 | ␉␉␉␉␉␉return true;␊ |
116 | ␉␉␉␉␉}␊ |
117 | ␉␉␉␉}␊ |
118 | ␉␉␉}␊ |
119 | ␉␉}␊ |
120 | ␉}␊ |
121 | ␉return false;␊ |
122 | }␊ |
123 | ␊ |
124 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
125 | {␊ |
126 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
127 | ␉{␊ |
128 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
129 | ␉}␊ |
130 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
131 | ␉{␊ |
132 | ␉␉return 0x0201;␉// Core Solo␊ |
133 | ␉};␊ |
134 | ␉␊ |
135 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
136 | }␊ |
137 | ␊ |
138 | bool getSMBOemProcessorType(returnType *value)␊ |
139 | {␊ |
140 | ␉static bool done = false;␉␉␊ |
141 | ␉␉␊ |
142 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
143 | ␊ |
144 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
145 | ␉{␊ |
146 | ␉␉if (!done)␊ |
147 | ␉␉{␊ |
148 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
149 | ␉␉␉done = true;␊ |
150 | ␉␉}␊ |
151 | ␉␉␊ |
152 | ␉␉switch (Platform.CPU.Family) ␊ |
153 | ␉␉{␊ |
154 | ␉␉␉case 0x06:␊ |
155 | ␉␉␉{␊ |
156 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
157 | ␉␉␉␉{␊ |
158 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊ |
159 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
160 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
161 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
162 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
163 | ␉␉␉␉␉␉return true;␊ |
164 | ␊ |
165 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
166 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
167 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊ |
168 | ␉␉␉␉␉␉else␊ |
169 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
170 | ␉␉␉␉␉␉return true;␊ |
171 | ␊ |
172 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
173 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
174 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
175 | ␉␉␉␉␉␉else␊ |
176 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
177 | ␉␉␉␉␉␉return true;␊ |
178 | ␊ |
179 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
180 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
181 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
182 | ␉␉␉␉␉␉else␊ |
183 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
184 | ␉␉␉␉␉␉return true;␊ |
185 | ␊ |
186 | ␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
187 | case CPU_MODEL_SANDY_XEON:␉␉␉// Intel Xeon E3␊ |
188 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
189 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
190 | ␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊ |
191 | ␉␉␉␉␉␉else␊ |
192 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
193 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊ |
194 | ␉␉␉␉␉␉␉else␊ |
195 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
196 | ␉␉␉␉␉␉return true;␊ |
197 | ␊ |
198 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
199 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
200 | ␉␉␉␉␉␉value->word = 0x0501;␉␉␉␉// Core i7␊ |
201 | ␉␉␉␉␉␉return true;␊ |
202 | ␉␉␉␉}␊ |
203 | ␉␉␉}␊ |
204 | ␉␉}␊ |
205 | ␉}␊ |
206 | ␉␊ |
207 | ␉return false;␊ |
208 | }␊ |
209 | ␊ |
210 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
211 | {␊ |
212 | ␉static int idx = -1;␊ |
213 | ␉int␉map;␊ |
214 | ␊ |
215 | ␉idx++;␊ |
216 | ␉if (idx < MAX_RAM_SLOTS)␊ |
217 | ␉{␊ |
218 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
219 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
220 | ␉␉{␊ |
221 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
222 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
223 | ␉␉␉return true;␊ |
224 | ␉␉}␊ |
225 | ␉}␊ |
226 | ␉␊ |
227 | ␉return false;␊ |
228 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
229 | //␉return true;␊ |
230 | }␊ |
231 | ␊ |
232 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
233 | {␊ |
234 | ␉static int idx = -1;␊ |
235 | ␉int␉map;␊ |
236 | ␊ |
237 | ␉idx++;␊ |
238 | ␉if (idx < MAX_RAM_SLOTS)␊ |
239 | ␉{␊ |
240 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
241 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
242 | ␉␉{␊ |
243 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
244 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
245 | ␉␉␉return true;␊ |
246 | ␉␉}␊ |
247 | ␉}␊ |
248 | ␊ |
249 | ␉return false;␊ |
250 | //␉value->dword = 800;␊ |
251 | //␉return true;␊ |
252 | }␊ |
253 | ␊ |
254 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
255 | {␊ |
256 | ␉static int idx = -1;␊ |
257 | ␉int␉map;␊ |
258 | ␊ |
259 | ␉idx++;␊ |
260 | ␉if (idx < MAX_RAM_SLOTS)␊ |
261 | ␉{␊ |
262 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
263 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
264 | ␉␉{␊ |
265 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
266 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
267 | ␉␉␉return true;␊ |
268 | ␉␉}␊ |
269 | ␉}␊ |
270 | ␊ |
271 | ␉if (!bootInfo->memDetect)␊ |
272 | ␉␉return false;␊ |
273 | ␉value->string = NOT_AVAILABLE;␊ |
274 | ␉return true;␊ |
275 | }␊ |
276 | ␉␊ |
277 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
278 | {␊ |
279 | ␉static int idx = -1;␊ |
280 | ␉int␉map;␊ |
281 | ␊ |
282 | ␉idx++;␊ |
283 | ␊ |
284 | DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
285 | ␊ |
286 | ␉if (idx < MAX_RAM_SLOTS)␊ |
287 | ␉{␊ |
288 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
289 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
290 | ␉␉{␊ |
291 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
292 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
293 | ␉␉␉return true;␊ |
294 | ␉␉}␊ |
295 | ␉}␊ |
296 | ␊ |
297 | ␉if (!bootInfo->memDetect)␊ |
298 | ␉␉return false;␊ |
299 | ␉value->string = NOT_AVAILABLE;␊ |
300 | ␉return true;␊ |
301 | }␊ |
302 | ␊ |
303 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
304 | {␊ |
305 | ␉static int idx = -1;␊ |
306 | ␉int␉map;␊ |
307 | ␊ |
308 | ␉idx++;␊ |
309 | ␉if (idx < MAX_RAM_SLOTS)␊ |
310 | ␉{␊ |
311 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
312 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
313 | ␉␉{␊ |
314 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
315 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
316 | ␉␉␉return true;␊ |
317 | ␉␉}␊ |
318 | ␉}␊ |
319 | ␊ |
320 | ␉if (!bootInfo->memDetect)␊ |
321 | ␉␉return false;␊ |
322 | ␉value->string = NOT_AVAILABLE;␊ |
323 | ␉return true;␊ |
324 | }␊ |
325 | ␊ |
326 | ␊ |
327 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
328 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
329 | static const char * const SMTAG = "_SM_";␊ |
330 | static const char* const DMITAG = "_DMI_";␊ |
331 | ␊ |
332 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
333 | {␊ |
334 | ␉SMBEntryPoint␉*smbios;␊ |
335 | ␉/* ␊ |
336 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
337 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
338 | ␉ */␊ |
339 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
340 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
341 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
342 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
343 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
344 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
345 | ␉ {␊ |
346 | ␉␉␉return smbios;␊ |
347 | ␉ }␊ |
348 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
349 | ␉}␊ |
350 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
351 | ␉pause();␊ |
352 | ␉return NULL;␊ |
353 | }␊ |
354 | ␊ |
355 | |