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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
24 */␊
25static uint64_t measure_tsc_frequency(void)␊
26{␊
27␉uint64_t tscStart;␊
28␉uint64_t tscEnd;␊
29␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
30␉unsigned long pollCount;␊
31␉uint64_t retval = 0;␊
32␉int i;␊
33␉␊
34␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
35␉ * counter 2. We run this loop 3 times to make sure the cache␊
36␉ * is hot and we take the minimum delta from all of the runs.␊
37␉ * That is to say that we're biased towards measuring the minimum␊
38␉ * number of TSC ticks that occur while waiting for the timer to␊
39␉ * expire. That theoretically helps avoid inconsistencies when␊
40␉ * running under a VM if the TSC is not virtualized and the host␊
41␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
42␉ */␊
43␉for(i = 0; i < 10; ++i)␊
44␉{␊
45␉␉enable_PIT2();␊
46␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
47␉␉tscStart = rdtsc64();␊
48␉␉pollCount = poll_PIT2_gate();␊
49␉␉tscEnd = rdtsc64();␊
50␉␉/* The poll loop must have run at least a few times for accuracy */␊
51␉␉if (pollCount <= 1)␊
52␉␉␉continue;␊
53␉␉/* The TSC must increment at LEAST once every millisecond.␊
54␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
55␉␉ * be >= 30. Anything less and the processor is way too slow.␊
56␉␉ */␊
57␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
58␉␉␉continue;␊
59␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
60␉␉if ( (tscEnd - tscStart) < tscDelta )␊
61␉␉␉tscDelta = tscEnd - tscStart;␊
62␉}␊
63␉/* tscDelta is now the least number of TSC ticks the processor made in␊
64␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
65␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
66␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
67␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
68␉ * dividing by the milliseconds, we simply multiply by 1000.␊
69␉ */␊
70␉␊
71␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
72␉ * that we're going to multiply by 1000 first so we do need at least some␊
73␉ * arithmetic headroom. For now, 32-bit should be enough.␊
74␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
75␉ */␊
76␉if (tscDelta > (1ULL<<32))␊
77␉␉retval = 0;␊
78␉else␊
79␉{␊
80␉␉retval = tscDelta * 1000 / 30;␊
81␉}␊
82␉disable_PIT2();␊
83␉return retval;␊
84}␊
85␊
86/*␊
87 * Original comment/code:␊
88 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
89 *␊
90 * Measures the Actual Performance Frequency in Hz (64-bit)␊
91 * (just a naming change, mperf --> aperf )␊
92 */␊
93static uint64_t measure_aperf_frequency(void)␊
94{␊
95␉uint64_t aperfStart;␊
96␉uint64_t aperfEnd;␊
97␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
98␉unsigned long pollCount;␊
99␉uint64_t retval = 0;␊
100␉int i;␊
101␉␊
102␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
103␉ * counter 2. We run this loop 3 times to make sure the cache␊
104␉ * is hot and we take the minimum delta from all of the runs.␊
105␉ * That is to say that we're biased towards measuring the minimum␊
106␉ * number of APERF ticks that occur while waiting for the timer to␊
107␉ * expire.␊
108␉ */␊
109␉for(i = 0; i < 10; ++i)␊
110␉{␊
111␉␉enable_PIT2();␊
112␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
113␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
114␉␉pollCount = poll_PIT2_gate();␊
115␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
116␉␉/* The poll loop must have run at least a few times for accuracy */␊
117␉␉if (pollCount <= 1)␊
118␉␉␉continue;␊
119␉␉/* The TSC must increment at LEAST once every millisecond.␊
120␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
121␉␉ * be >= 30. Anything less and the processor is way too slow.␊
122␉␉ */␊
123␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
124␉␉␉continue;␊
125␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
126␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
127␉␉␉aperfDelta = aperfEnd - aperfStart;␊
128␉}␊
129␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
130␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
131␉ */␊
132␉␊
133␉if (aperfDelta > (1ULL<<32))␊
134␉␉retval = 0;␊
135␉else␊
136␉{␊
137␉␉retval = aperfDelta * 1000 / 30;␊
138␉}␊
139␉disable_PIT2();␊
140␉return retval;␊
141}␊
142␊
143/*␊
144 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
145 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
146 *␉ a max multi. (used to calculate the FSB freq.),␊
147 *␉ and a current multi. (used to calculate the CPU freq.)␊
148 * - fsbFrequency = tscFrequency / multi␊
149 * - cpuFrequency = fsbFrequency * multi␊
150 */␊
151void scan_cpu(PlatformInfo_t *p)␊
152{␊
153␉uint64_t␉tscFrequency = 0;␊
154␉uint64_t␉fsbFrequency = 0;␊
155␉uint64_t␉cpuFrequency =0;␊
156␉uint64_t␉msr = 0;␊
157␉uint64_t␉flex_ratio = 0;␊
158␉uint32_t␉max_ratio = 0;␊
159␉uint32_t␉min_ratio = 0;␊
160␉uint8_t␉␉bus_ratio_max = 0;␊
161␉uint8_t␉␉bus_ratio_min = 0;␊
162␉uint8_t␉␉currdiv = 0;␊
163␉uint8_t␉␉currcoef = 0;␊
164␉uint8_t␉␉maxdiv = 0;␊
165␉uint8_t␉␉maxcoef = 0;␊
166␊
167␉const char␉*newratio;␊
168␉int␉␉␉len = 0;␊
169␉␊
170␉/* get cpuid values */␊
171␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
172␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
173␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
174␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
175␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
176␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
177␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊
178␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
179␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
180␉}␊
181␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
182␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
183␉}␊
184␉␊
185#if DEBUG_CPU␊
186␉{␊
187␉␉int␉␉i;␊
188␉␉printf("CPUID Raw Values:\n");␊
189␉␉for (i=0; i<CPUID_MAX; i++) {␊
190␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
191␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
192␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
193␉␉}␊
194␉}␊
195#endif␊
196␉␊
197␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
198␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
199␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
200␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
201␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
202␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
203␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
204␉␊
205␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
206␉␊
207␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
208␉␉p->CPU.Family == 0x06 &&␊
209␉␉p->CPU.Model >= CPU_MODEL_NEHALEM &&␊
210␉␉p->CPU.Model != CPU_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
211␉␉)␊
212␉{␊
213␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
214␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊
215␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊
216␉}␊
217␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
218␉{␊
219␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
220␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
221␉}␊
222␉else␊
223␉{␊
224␉␉// Use previous method for Cores and Threads␊
225␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
226␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
227␉}␊
228␉␊
229␉/* get brand string (if supported) */␊
230␉/* Copyright: from Apple's XNU cpuid.c */␊
231␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
232␉␉uint32_t␉reg[4];␊
233␉␉char␉␉str[128], *s;␊
234␉␉/*␊
235␉␉ * The brand string 48 bytes (max), guaranteed to␊
236␉␉ * be NULL terminated.␊
237␉␉ */␊
238␉␉do_cpuid(0x80000002, reg);␊
239␉␉bcopy((char *)reg, &str[0], 16);␊
240␉␉do_cpuid(0x80000003, reg);␊
241␉␉bcopy((char *)reg, &str[16], 16);␊
242␉␉do_cpuid(0x80000004, reg);␊
243␉␉bcopy((char *)reg, &str[32], 16);␊
244␉␉for (s = str; *s != '\0'; s++) {␊
245␉␉␉if (*s != ' ') break;␊
246␉␉}␊
247␉␉␊
248␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊
249␉␉␊
250␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
251␉␉␉/*␊
252␉␉␉ * This string means we have a firmware-programmable brand string,␊
253␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
254␉␉␉ */␊
255␉␉␉p->CPU.BrandString[0] = '\0';␊
256␉␉}␊
257␉}␊
258␉␊
259␉/* setup features */␊
260␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
261␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
262␉}␊
263␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
264␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
265␉}␊
266␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
267␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
268␉}␊
269␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
270␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
271␉}␊
272␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
273␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
274␉}␊
275␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
276␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
277␉}␊
278␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
279␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
280␉}␊
281␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
282␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
283␉}␊
284␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
285␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
286␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
287␉}␊
288␉␊
289␉tscFrequency = measure_tsc_frequency();␊
290␉␊
291␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
292␉␉int intelCPU = p->CPU.Model;␊
293␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
294␉␉␉/* Nehalem CPU model */␊
295␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊
296␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉␉||␊
297␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉␉||␊
298␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊
299␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊
300␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊
301␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
302␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
303␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN␉||␊
304␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE␉)) {␊
305␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
306//␉␉␉␉DBG("MSR_PLATFORM_INFO: 0x%x\n", bitfield(msr, 63, 0));␊
307␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
308␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40);␉//MacMan: Changed bitfield to match Apple tsc.c␊
309␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
310//␉␉␉␉DBG("MSR_FLEX_RATIO: 0x%x\n", bitfield(msr, 31, 0));␊
311␉␉␉␉if (bitfield(msr, 16, 16)) {␊
312␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
313␉␉␉␉␉if (flex_ratio == 0) {␊
314␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
315␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
316␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
317//␉␉␉␉␉␉DBG("Null flex ratio detected. MSR_FLEX_RATIO now: %08x\n", bitfield(msr, 31, 0));␊
318␉␉␉␉␉} else {␊
319␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
320␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
321␉␉␉␉␉␉}␊
322␉␉␉␉␉}␊
323␉␉␉␉}␊
324␉␉␉␉␊
325␉␉␉␉if (bus_ratio_max) {␊
326␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
327␉␉␉␉}␊
328␊
329␉␉␉␉//MacMan: Turbo Ratio Limit␊
330␉␉␉␉switch (intelCPU) ␊
331␉␉␉␉{␊
332␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
333␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
334␉␉␉␉␉{␊
335␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
336␉␉␉␉␉␉DBG("cpu.c (%d)CPU_MODEL_NEHALEM_EX or CPU_MODEL_WESTMERE_EX Found\n", __LINE__);␊
337␉␉␉␉␉␉break;␊
338␉␉␉␉␉}␊
339␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
340␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
341␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
342␉␉␉␉␉{␊
343␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
344␉␉␉␉␉␉currcoef = bitfield(msr, 15, 8);␊
345␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
346␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
347␉␉␉␉␉␉break;␊
348␉␉␉␉␉}␊
349␉␉␉␉␉default:␊
350␉␉␉␉␉{␊
351␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
352␉␉␉␉␉␉currcoef = bitfield(msr, 7, 0);␊
353␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
354␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
355␉␉␉␉␉␉break;␊
356␉␉␉␉␉}␊
357␉␉␉␉}␊
358␉␉␉␉␉␉␊
359␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
360␉␉␉␉␉max_ratio = atoi(newratio);␊
361␉␉␉␉␉max_ratio = (max_ratio * 10);␊
362␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
363␉␉␉␉␉␊
364␉␉␉␉␉DBG("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
365␉␉␉␉␉␊
366␉␉␉␉␉// extreme overclockers may love 320 ;)␊
367␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
368␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
369␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
370␉␉␉␉␉␉else maxdiv = 0;␊
371␉␉␉␉␉} else {␊
372␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
373␉␉␉␉␉}␊
374␉␉␉␉}␊
375␊
376␉␉␉␉p->CPU.MaxRatio = bus_ratio_max;␊
377␉␉␉␉p->CPU.MinRatio = bus_ratio_min;␊
378␉␉␉␉␊
379␉␉␉} else {␊
380␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
381␉␉␉␉DBG("MSR_IA32_PERF_STATUS: 0x%08x\n", bitfield(msr, 31, 0));␊
382␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
383␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
384␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
385␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
386␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
387␉␉␉␉␊
388␉␉␉␉// This will always be model >= 3␊
389␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
390␉␉␉␉{␊
391␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
392␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
393␉␉␉␉} else {␊
394␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
395␉␉␉␉␉/* XXX */␊
396␉␉␉␉␉maxcoef = currcoef;␊
397␉␉␉␉}␊
398␉␉␉␉␊
399␉␉␉␉if (maxcoef) {␊
400␉␉␉␉␉if (maxdiv) {␊
401␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
402␉␉␉␉␉} else {␊
403␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
404␉␉␉␉␉}␊
405␉␉␉␉␉if (currdiv) {␊
406␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
407␉␉␉␉␉} else {␊
408␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
409␉␉␉␉␉}␊
410␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
411␉␉␉␉}␊
412␉␉␉}␊
413␉␉}␊
414␉␉/* Mobile CPU */␊
415␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
416␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
417␉␉}␊
418␉}␊
419␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
420␉{␊
421␉␉switch(p->CPU.ExtFamily)␊
422␉␉{␊
423␉␉␉case 0x00: /* K8 */␊
424␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
425␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
426␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
427␉␉␉␉break;␊
428␉␉␉␉␊
429␉␉␉case 0x01: /* K10 */␊
430␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
431␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
432␉␉␉␉// EffFreq: effective frequency interface␊
433␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
434␉␉␉␉{␊
435␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
436␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
437␉␉␉␉␉cpuFrequency = aperf;␊
438␉␉␉␉}␊
439␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
440␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
441␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
442␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
443␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
444␉␉␉␉␊
445␉␉␉␉break;␊
446␉␉␉␉␊
447␉␉␉case 0x05: /* K14 */␊
448␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
449␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
450␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
451␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
452␉␉␉␉␊
453␉␉␉␉break;␊
454␉␉␉␉␊
455␉␉␉case 0x02: /* K11 */␊
456␉␉␉␉// not implimented␊
457␉␉␉␉break;␊
458␉␉}␊
459␉␉␊
460␉␉if (maxcoef)␊
461␉␉{␊
462␉␉␉if (currdiv)␊
463␉␉␉{␊
464␉␉␉␉if (!currcoef) currcoef = maxcoef;␊
465␉␉␉␉if (!cpuFrequency)␊
466␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
467␉␉␉␉else␊
468␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
469␉␉␉␉␊
470␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
471␉␉␉} else {␊
472␉␉␉␉if (!cpuFrequency)␊
473␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
474␉␉␉␉else ␊
475␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
476␉␉␉␉DBG("%d\n", currcoef);␊
477␉␉␉}␊
478␉␉}␊
479␉␉else if (currcoef)␊
480␉␉{␊
481␉␉␉if (currdiv)␊
482␉␉␉{␊
483␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
484␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
485␉␉␉} else {␊
486␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
487␉␉␉␉DBG("%d\n", currcoef);␊
488␉␉␉}␊
489␉␉}␊
490␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
491␉}␊
492␉␊
493#if 0␊
494␉if (!fsbFrequency) {␊
495␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
496␉␉cpuFrequency = tscFrequency;␊
497␉␉DBG("0 ! using the default value for FSB !\n");␊
498␉}␊
499#endif␊
500␉␊
501␉p->CPU.MaxCoef = maxcoef;␊
502␉if (maxdiv == 0){␊
503␉␉p->CPU.MaxDiv = bus_ratio_max;␊
504␉}␊
505␉else {␊
506␉␉p->CPU.MaxDiv = maxdiv;␊
507␉}␊
508␉p->CPU.CurrCoef = currcoef;␊
509␉if (currdiv == 0){␊
510␉␉p->CPU.CurrDiv = currcoef;␊
511␉}␊
512␉else {␊
513␉␉p->CPU.CurrDiv = currdiv;␊
514␉}␊
515␉p->CPU.TSCFrequency = tscFrequency;␊
516␉p->CPU.FSBFrequency = fsbFrequency;␊
517␉p->CPU.CPUFrequency = cpuFrequency;␊
518␉␊
519␉// keep formatted with spaces instead of tabs␊
520␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊
521 DBG("CPU: Vendor: 0x%x\n",␉␉␉␉ p->CPU.Vendor);␊
522␉DBG("CPU: Family / ExtFamily: 0x%x / 0x%x\n",␉␉ p->CPU.Family, p->CPU.ExtFamily);␊
523 DBG("CPU: Model / ExtModel / Stepping: 0x%x / 0x%x / 0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
524 DBG("CPU: Number of Cores / Threads: %d / %d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
525 DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
526 DBG("CPU: TSC Frequency: %d MHz\n", p->CPU.TSCFrequency / 1000000);␊
527 DBG("CPU: FSB Frequency: %d MHz\n", p->CPU.FSBFrequency / 1000000);␊
528 DBG("CPU: CPU Frequency: %d MHz\n", p->CPU.CPUFrequency / 1000000);␊
529␉DBG("CPU: Minimum Bus Ratio: %d\n", p->CPU.MinRatio);␊
530 DBG("CPU: Maximum Bus Ratio: %d\n", p->CPU.MaxRatio);␊
531␉DBG("CPU: Current Bus Ratio: %d\n", p->CPU.CurrCoef);␊
532//␉DBG("CPU: Maximum Multiplier: %d\n",␉␉␉␉ p->CPU.MaxCoef);␊
533// DBG("CPU: Maximum Divider: %d\n",␉␉␉␉ p->CPU.MaxDiv);␊
534//␉DBG("CPU: Current Divider: %d\n",␉␉␉␉ p->CPU.CurrDiv);␊
535␊
536#if DEBUG_CPU ␊
537␉pause();␊
538#endif␊
539}␊
540

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