Chameleon

Chameleon Svn Source Tree

Root/branches/Chimera/Release/i386/libsaio/nvidia.c

1/*␊
2 *␉NVidia injector␊
3 *␊
4 *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊
5 *␊
6 *␉NVidia injector is free software: you can redistribute it and/or modify␊
7 *␉it under the terms of the GNU General Public License as published by␊
8 *␉the Free Software Foundation, either version 3 of the License, or␊
9 *␉(at your option) any later version.␊
10 *␊
11 *␉NVidia driver and injector is distributed in the hope that it will be useful,␊
12 *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊
13 *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊
14 *␉GNU General Public License for more details.␊
15 *␊
16 *␉You should have received a copy of the GNU General Public License␊
17 *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊
18 */ ␊
19/*␊
20 * Alternatively you can choose to comply with APSL␊
21 */␊
22 ␊
23 ␊
24/*␊
25 * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊
26 *␊
27 *␊
28 * Copyright 2005-2006 Erik Waling␊
29 * Copyright 2006 Stephane Marchesin␊
30 * Copyright 2007-2009 Stuart Bennett␊
31 *␊
32 * Permission is hereby granted, free of charge, to any person obtaining a␊
33 * copy of this software and associated documentation files (the "Software"),␊
34 * to deal in the Software without restriction, including without limitation␊
35 * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊
36 * and/or sell copies of the Software, and to permit persons to whom the␊
37 * Software is furnished to do so, subject to the following conditions:␊
38 *␊
39 * The above copyright notice and this permission notice shall be included in␊
40 * all copies or substantial portions of the Software.␊
41 *␊
42 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊
43 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊
44 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊
45 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊
46 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊
47 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊
48 * SOFTWARE.␊
49 */␊
50␊
51#include "boot.h"␊
52#include "bootstruct.h"␊
53#include "pci.h"␊
54#include "platform.h"␊
55#include "device_inject.h"␊
56#include "nvidia.h"␊
57␊
58#ifndef DEBUG_NVIDIA␊
59#define DEBUG_NVIDIA 0␊
60#endif␊
61␊
62#if DEBUG_NVIDIA␊
63#define DBG(x...)␉printf(x)␊
64#else␊
65#define DBG(x...)␊
66#endif␊
67␊
68#define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊
69#define PATCH_ROM_SUCCESS␉␉␉1␊
70#define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊
71#define PATCH_ROM_FAILED␉␉␉0␊
72#define MAX_NUM_DCB_ENTRIES␉␉␉16␊
73#define TYPE_GROUPED␉␉␉␉0xff␊
74␊
75extern uint32_t devices_number;␊
76␊
77const char *nvidia_compatible_0[]␉␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊
78const char *nvidia_compatible_1[]␉␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
79const char *nvidia_device_type_0[]␉␉=␉{ "@0,device_type", "display"␉␉ };␊
80const char *nvidia_device_type_1[]␉␉=␉{ "@1,device_type", "display"␉␉ };␊
81const char *nvidia_device_type[]␉␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊
82const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
83const char *nvidia_name_0[]␉␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊
84const char *nvidia_name_1[]␉␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊
85const char *nvidia_slot_name[]␉␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊
86␊
87static uint8_t default_NVCAP[]= {␊
88␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊
89␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊
90␉0x00, 0x00, 0x00, 0x00␊
91};␊
92␊
93#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊
94␊
95static uint8_t default_dcfg_0[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
96static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0xff, 0xff};␊
97␊
98#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊
99#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊
100␊
101static struct nv_chipsets_t NVKnownChipsets[] = {␊
102␉{ 0x00000000, "Unknown" },␊
103//========================================␊
104␉// 0040 - 004F␊
105␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊
106␉{ 0x10DE0041, "GeForce 6800" },␊
107␉{ 0x10DE0042, "GeForce 6800 LE" },␊
108␉{ 0x10DE0043, "GeForce 6800 XE" },␊
109␉{ 0x10DE0044, "GeForce 6800 XT" },␊
110␉{ 0x10DE0045, "GeForce 6800 GT" },␊
111␉{ 0x10DE0046, "GeForce 6800 GT" },␊
112␉{ 0x10DE0047, "GeForce 6800 GS" },␊
113␉{ 0x10DE0048, "GeForce 6800 XT" },␊
114␉{ 0x10DE004D, "Quadro FX 3400" },␊
115␉{ 0x10DE004E, "Quadro FX 4000" },␊
116␉// 0050 - 005F␊
117␉// 0060 - 006F␊
118␉// 0070 - 007F␊
119␉// 0080 - 008F␊
120␉// 0090 - 009F␊
121␉{ 0x10DE0090, "GeForce 7800 GTX" },␊
122␉{ 0x10DE0091, "GeForce 7800 GTX" },␊
123␉{ 0x10DE0092, "GeForce 7800 GT" },␊
124␉{ 0x10DE0093, "GeForce 7800 GS" },␊
125␉{ 0x10DE0095, "GeForce 7800 SLI" },␊
126␉{ 0x10DE0098, "GeForce Go 7800" },␊
127␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊
128␉{ 0x10DE009D, "Quadro FX 4500" },␊
129␉// 00A0 - 00AF␊
130␉// 00B0 - 00BF␊
131␉// 00C0 - 00CF␊
132␉{ 0x10DE00C0, "GeForce 6800 GS" },␊
133␉{ 0x10DE00C1, "GeForce 6800" },␊
134␉{ 0x10DE00C2, "GeForce 6800 LE" },␊
135␉{ 0x10DE00C3, "GeForce 6800 XT" },␊
136␉{ 0x10DE00C8, "GeForce Go 6800" },␊
137␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊
138␉{ 0x10DE00CC, "Quadro FX Go1400" },␊
139␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊
140␉{ 0x10DE00CE, "Quadro FX 1400" },␊
141␉// 00D0 - 00DF␊
142␉// 00E0 - 00EF␊
143␉// 00F0 - 00FF␊
144␉{ 0x10DE00F1, "GeForce 6600 GT" },␊
145␉{ 0x10DE00F2, "GeForce 6600" },␊
146␉{ 0x10DE00F3, "GeForce 6200" },␊
147␉{ 0x10DE00F4, "GeForce 6600 LE" },␊
148␉{ 0x10DE00F5, "GeForce 7800 GS" },␊
149␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊
150␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊
151␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊
152␉// 0100 - 010F␊
153␉// 0110 - 011F␊
154␉// 0120 - 012F␊
155␉// 0130 - 013F␊
156␉// 0140 - 014F␊
157␉{ 0x10DE0140, "GeForce 6600 GT" },␊
158␉{ 0x10DE0141, "GeForce 6600" },␊
159␉{ 0x10DE0142, "GeForce 6600 LE" },␊
160␉{ 0x10DE0143, "GeForce 6600 VE" },␊
161␉{ 0x10DE0144, "GeForce Go 6600" },␊
162␉{ 0x10DE0145, "GeForce 6610 XL" },␊
163␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊
164␉{ 0x10DE0147, "GeForce 6700 XL" },␊
165␉{ 0x10DE0148, "GeForce Go 6600" },␊
166␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊
167␉{ 0x10DE014A, "Quadro NVS 440" },␊
168␉{ 0x10DE014C, "Quadro FX 550" },␊
169␉{ 0x10DE014D, "Quadro FX 550" },␊
170␉{ 0x10DE014E, "Quadro FX 540" },␊
171␉{ 0x10DE014F, "GeForce 6200" },␊
172␉// 0150 - 015F␊
173␉// 0160 - 016F␊
174␉{ 0x10DE0160, "GeForce 6500" },␊
175␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊
176␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊
177␉{ 0x10DE0163, "GeForce 6200 LE" },␊
178␉{ 0x10DE0164, "GeForce Go 6200" },␊
179␉{ 0x10DE0165, "Quadro NVS 285" },␊
180␉{ 0x10DE0166, "GeForce Go 6400" },␊
181␉{ 0x10DE0167, "GeForce Go 6200" },␊
182␉{ 0x10DE0168, "GeForce Go 6400" },␊
183␉{ 0x10DE0169, "GeForce 6250" },␊
184␉{ 0x10DE016A, "GeForce 7100 GS" },␊
185␉// 0170 - 017F␊
186␉// 0180 - 018F␊
187␉// 0190 - 019F␊
188␉{ 0x10DE0191, "GeForce 8800 GTX" },␊
189␉{ 0x10DE0193, "GeForce 8800 GTS" },␊
190␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊
191␉{ 0x10DE0197, "Tesla C870" },␊
192␉{ 0x10DE019D, "Quadro FX 5600" },␊
193␉{ 0x10DE019E, "Quadro FX 4600" },␊
194␉// 01A0 - 01AF␊
195␉// 01B0 - 01BF␊
196␉// 01C0 - 01CF␊
197␉// 01D0 - 01DF␊
198␉{ 0x10DE01D0, "GeForce 7350 LE" },␊
199␉{ 0x10DE01D1, "GeForce 7300 LE" },␊
200␉{ 0x10DE01D2, "GeForce 7550 LE" },␊
201␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊
202␉{ 0x10DE01D6, "GeForce Go 7200" },␊
203␉{ 0x10DE01D7, "GeForce Go 7300" },␊
204␉{ 0x10DE01D8, "GeForce Go 7400" },␊
205␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊
206␉{ 0x10DE01DA, "Quadro NVS 110M" },␊
207␉{ 0x10DE01DB, "Quadro NVS 120M" },␊
208␉{ 0x10DE01DC, "Quadro FX 350M" },␊
209␉{ 0x10DE01DD, "GeForce 7500 LE" },␊
210␉{ 0x10DE01DE, "Quadro FX 350" },␊
211␉{ 0x10DE01DF, "GeForce 7300 GS" },␊
212␉// 01E0 - 01EF␊
213␉// 01F0 - 01FF␊
214␉// 0200 - 020F␊
215␉// 0210 - 021F␊
216␉{ 0x10DE0211, "GeForce 6800" },␊
217␉{ 0x10DE0212, "GeForce 6800 LE" },␊
218␉{ 0x10DE0215, "GeForce 6800 GT" },␊
219␉{ 0x10DE0218, "GeForce 6800 XT" },␊
220␉// 0220 - 022F␊
221␉{ 0x10DE0221, "GeForce 6200" },␊
222␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊
223␉// 0230 - 023F␊
224␉// 0240 - 024F␊
225␉{ 0x10DE0240, "GeForce 6150" },␊
226␉{ 0x10DE0241, "GeForce 6150 LE" },␊
227␉{ 0x10DE0242, "GeForce 6100" },␊
228␉{ 0x10DE0244, "GeForce Go 6150" },␊
229␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊
230␉{ 0x10DE0247, "GeForce Go 6100" },␊
231␉// 0250 - 025F␊
232␉// 0260 - 026F␊
233␉// 0270 - 027F␊
234␉// 0280 - 028F␊
235␉// 0290 - 029F␊
236␉{ 0x10DE0290, "GeForce 7900 GTX" },␊
237␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊
238␉{ 0x10DE0292, "GeForce 7900 GS" },␊
239␉{ 0x10DE0293, "GeForce 7950 GX2" },␊
240␉{ 0x10DE0294, "GeForce 7950 GX2" },␊
241␉{ 0x10DE0295, "GeForce 7950 GT" },␊
242␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊
243␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊
244␉{ 0x10DE029A, "Quadro FX 2500M" },␊
245␉{ 0x10DE029B, "Quadro FX 1500M" },␊
246␉{ 0x10DE029C, "Quadro FX 5500" },␊
247␉{ 0x10DE029D, "Quadro FX 3500" },␊
248␉{ 0x10DE029E, "Quadro FX 1500" },␊
249␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊
250␉// 02A0 - 02AF␊
251␉// 02B0 - 02BF␊
252␉// 02C0 - 02CF␊
253␉// 02D0 - 02DF␊
254␉// 02E0 - 02EF␊
255␉{ 0x10DE02E0, "GeForce 7600 GT" },␊
256␉{ 0x10DE02E1, "GeForce 7600 GS" },␊
257␉{ 0x10DE02E2, "GeForce 7300 GT" },␊
258␉{ 0x10DE02E3, "GeForce 7900 GS" },␊
259␉{ 0x10DE02E4, "GeForce 7950 GT" },␊
260␉// 02F0 - 02FF␊
261␉// 0300 - 030F␊
262␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊
263␉{ 0x10DE0302, "GeForce FX 5800" },␊
264␉{ 0x10DE0308, "Quadro FX 2000" },␊
265␉{ 0x10DE0309, "Quadro FX 1000" },␊
266␉// 0310 - 031F␊
267␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊
268␉{ 0x10DE0312, "GeForce FX 5600" },␊
269␉{ 0x10DE0314, "GeForce FX 5600XT" },␊
270␉{ 0x10DE031A, "GeForce FX Go5600" },␊
271␉{ 0x10DE031B, "GeForce FX Go5650" },␊
272␉{ 0x10DE031C, "Quadro FX Go700" },␊
273␉// 0320 - 032F␊
274␉{ 0x10DE0324, "GeForce FX Go5200" },␊
275␉{ 0x10DE0325, "GeForce FX Go5250" },␊
276␉{ 0x10DE0326, "GeForce FX 5500" },␊
277␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊
278␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊
279␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊
280␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊
281␉{ 0x10DE032D, "GeForce FX Go5100" },␊
282␉// 0330 - 033F␊
283␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊
284␉{ 0x10DE0331, "GeForce FX 5900" },␊
285␉{ 0x10DE0332, "GeForce FX 5900XT" },␊
286␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊
287␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊
288␉{ 0x10DE0338, "Quadro FX 3000" },␊
289␉{ 0x10DE033F, "Quadro FX 700" },␊
290␉// 0340 - 034F␊
291␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊
292␉{ 0x10DE0342, "GeForce FX 5700" },␊
293␉{ 0x10DE0343, "GeForce FX 5700LE" },␊
294␉{ 0x10DE0344, "GeForce FX 5700VE" },␊
295␉{ 0x10DE0347, "GeForce FX Go5700" },␊
296␉{ 0x10DE0348, "GeForce FX Go5700" },␊
297␉{ 0x10DE034C, "Quadro FX Go1000" },␊
298␉{ 0x10DE034E, "Quadro FX 1100" },␊
299␉// 0350 - 035F␊
300␉// 0360 - 036F␊
301␉// 0370 - 037F␊
302␉// 0380 - 038F␊
303␉{ 0x10DE038B, "GeForce 7650 GS" },␊
304␉// 0390 - 039F␊
305␉{ 0x10DE0390, "GeForce 7650 GS" },␊
306␉{ 0x10DE0391, "GeForce 7600 GT" },␊
307␉{ 0x10DE0392, "GeForce 7600 GS" },␊
308␉{ 0x10DE0393, "GeForce 7300 GT" },␊
309␉{ 0x10DE0394, "GeForce 7600 LE" },␊
310␉{ 0x10DE0395, "GeForce 7300 GT" },␊
311␉{ 0x10DE0397, "GeForce Go 7700" },␊
312␉{ 0x10DE0398, "GeForce Go 7600" },␊
313␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊
314␉{ 0x10DE039A, "Quadro NVS 300M" },␊
315␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊
316␉{ 0x10DE039C, "Quadro FX 550M" },␊
317␉{ 0x10DE039E, "Quadro FX 560" },␊
318␉// 03A0 - 03AF␊
319␉// 03B0 - 03BF␊
320␉// 03C0 - 03CF␊
321␉// 03D0 - 03DF␊
322␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊
323␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊
324␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊
325␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊
326␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊
327␉// 03E0 - 03EF␊
328␉// 03F0 - 03FF␊
329␉// 0400 - 040F␊
330␉{ 0x10DE0400, "GeForce 8600 GTS" },␊
331␉{ 0x10DE0401, "GeForce 8600 GT" },␊
332␉{ 0x10DE0402, "GeForce 8600 GT" },␊
333␉{ 0x10DE0403, "GeForce 8600 GS" },␊
334␉{ 0x10DE0404, "GeForce 8400 GS" },␊
335␉{ 0x10DE0405, "GeForce 9500M GS" },␊
336␉{ 0x10DE0406, "GeForce 8300 GS" },␊
337␉{ 0x10DE0407, "GeForce 8600M GT" },␊
338␉{ 0x10DE0408, "GeForce 9650M GS" },␊
339␉{ 0x10DE0409, "GeForce 8700M GT" },␊
340␉{ 0x10DE040A, "Quadro FX 370" },␊
341␉{ 0x10DE040B, "Quadro NVS 320M" },␊
342␉{ 0x10DE040C, "Quadro FX 570M" },␊
343␉{ 0x10DE040D, "Quadro FX 1600M" },␊
344␉{ 0x10DE040E, "Quadro FX 570" },␊
345␉{ 0x10DE040F, "Quadro FX 1700" },␊
346␉// 0410 - 041F␊
347␉{ 0x10DE0410, "GeForce GT 330" },␊
348␉// 0420 - 042F␊
349␉{ 0x10DE0420, "GeForce 8400 SE" },␊
350␉{ 0x10DE0421, "GeForce 8500 GT" },␊
351␉{ 0x10DE0422, "GeForce 8400 GS" },␊
352␉{ 0x10DE0423, "GeForce 8300 GS" },␊
353␉{ 0x10DE0424, "GeForce 8400 GS" },␊
354␉{ 0x10DE0425, "GeForce 8600M GS" },␊
355␉{ 0x10DE0426, "GeForce 8400M GT" },␊
356␉{ 0x10DE0427, "GeForce 8400M GS" },␊
357␉{ 0x10DE0428, "GeForce 8400M G" },␊
358␉{ 0x10DE0429, "Quadro NVS 140M" },␊
359␉{ 0x10DE042A, "Quadro NVS 130M" },␊
360␉{ 0x10DE042B, "Quadro NVS 135M" },␊
361␉{ 0x10DE042C, "GeForce 9400 GT" },␊
362␉{ 0x10DE042D, "Quadro FX 360M" },␊
363␉{ 0x10DE042E, "GeForce 9300M G" },␊
364␉{ 0x10DE042F, "Quadro NVS 290" },␊
365␉// 0430 - 043F␊
366␉// 0440 - 044F␊
367␉// 0450 - 045F␊
368␉// 0460 - 046F␊
369␉// 0470 - 047F␊
370␉// 0480 - 048F␊
371␉// 0490 - 049F␊
372␉// 04A0 - 04AF␊
373␉// 04B0 - 04BF␊
374␉// 04C0 - 04CF␊
375␉// 04D0 - 04DF␊
376␉// 04E0 - 04EF␊
377␉// 04F0 - 04FF␊
378␉// 0500 - 050F␊
379␉// 0510 - 051F␊
380␉// 0520 - 052F␊
381␉// 0530 - 053F␊
382␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊
383␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊
384␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊
385␉// 0540 - 054F␊
386␉// 0550 - 055F␊
387␉// 0560 - 056F␊
388␉// 0570 - 057F␊
389␉// 0580 - 058F␊
390␉// 0590 - 059F␊
391␉// 05A0 - 05AF␊
392␉// 05B0 - 05BF␊
393␉// 05C0 - 05CF␊
394␉// 05D0 - 05DF␊
395␉// 05E0 - 05EF␊
396␉{ 0x10DE05E0, "GeForce GTX 295" },␊
397␉{ 0x10DE05E1, "GeForce GTX 280" },␊
398␉{ 0x10DE05E2, "GeForce GTX 260" },␊
399␉{ 0x10DE05E3, "GeForce GTX 285" },␊
400␉{ 0x10DE05E6, "GeForce GTX 275" },␊
401␉{ 0x10DE05E7, "Tesla C1060 / M1060" },␊
402␉// { 0x10DE05E7, 0x0595, "Tesla C1060" },␊
403␉// { 0x10DE05E7, 0x068F, "Tesla C1060" },␊
404␉// { 0x10DE05E7, 0x0697, "Tesla M1060" },␊
405␉// { 0x10DE05E7, 0x0743, "Tesla M1060" },␊
406␉{ 0x10DE05EA, "GeForce GTX 260" },␊
407␉{ 0x10DE05EB, "GeForce GTX 295" },␊
408␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊
409␉// 05F0 - 05FF␊
410␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊
411␉{ 0x10DE05F9, "Quadro CX" },␊
412␉{ 0x10DE05FD, "Quadro FX 5800" },␊
413␉{ 0x10DE05FE, "Quadro FX 4800" },␊
414␉{ 0x10DE05FF, "Quadro FX 3800" },␊
415␉// 0600 - 060F␊
416␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊
417␉{ 0x10DE0601, "GeForce 9800 GT" },␊
418␉{ 0x10DE0602, "GeForce 8800 GT" },␊
419␉{ 0x10DE0603, "GeForce GT 230" },␊
420␉{ 0x10DE0604, "GeForce 9800 GX2" },␊
421␉{ 0x10DE0605, "GeForce 9800 GT" },␊
422␉{ 0x10DE0606, "GeForce 8800 GS" },␊
423␉{ 0x10DE0607, "GeForce GTS 240" },␊
424␉{ 0x10DE0608, "GeForce 9800M GTX" },␊
425␉{ 0x10DE0609, "GeForce 8800M GTS" },␊
426␉{ 0x10DE060A, "GeForce GTX 280M" },␊
427␉{ 0x10DE060B, "GeForce 9800M GT" },␊
428␉{ 0x10DE060C, "GeForce 8800M GTX" },␊
429␉{ 0x10DE060D, "GeForce 8800 GS" },␊
430␉{ 0x10DE060F, "GeForce GTX 285M" },␊
431␉// 0610 - 061F␊
432␉{ 0x10DE0610, "GeForce 9600 GSO" },␊
433␉{ 0x10DE0611, "GeForce 8800 GT" },␊
434␉{ 0x10DE0612, "GeForce 9800 GTX" },␊
435␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊
436␉{ 0x10DE0614, "GeForce 9800 GT" },␊
437␉{ 0x10DE0615, "GeForce GTS 250" },␊
438␉{ 0x10DE0617, "GeForce 9800M GTX" },␊
439␉{ 0x10DE0618, "GeForce GTX 260M" },␊
440␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊
441␉{ 0x10DE061A, "Quadro FX 3700" },␊
442␉{ 0x10DE061B, "Quadro VX 200" },␊
443␉{ 0x10DE061C, "Quadro FX 3600M" },␊
444␉{ 0x10DE061D, "Quadro FX 2800M" },␊
445␉{ 0x10DE061E, "Quadro FX 3700M" },␊
446␉{ 0x10DE061F, "Quadro FX 3800M" },␊
447␉// 0620 - 062F␊
448␉{ 0x10DE0621, "GeForce GT 230" },␊
449␉{ 0x10DE0622, "GeForce 9600 GT" },␊
450␉{ 0x10DE0623, "GeForce 9600 GS" },␊
451␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊
452␉{ 0x10DE0626, "GeForce GT 130" },␊
453␉{ 0x10DE0627, "GeForce GT 140" },␊
454␉{ 0x10DE0628, "GeForce 9800M GTS" },␊
455␉{ 0x10DE062A, "GeForce 9700M GTS" },␊
456␉{ 0x10DE062B, "GeForce 9800M GS" },␊
457␉{ 0x10DE062C, "GeForce 9800M GTS" },␊
458␉{ 0x10DE062D, "GeForce 9600 GT" },␊
459␉{ 0x10DE062E, "GeForce 9600 GT" },␊
460␉// 0630 - 063F␊
461␉{ 0x10DE0631, "GeForce GTS 160M" },␊
462␉{ 0x10DE0632, "GeForce GTS 150M" },␊
463␉{ 0x10DE0635, "GeForce 9600 GSO" },␊
464␉{ 0x10DE0637, "GeForce 9600 GT" },␊
465␉{ 0x10DE0638, "Quadro FX 1800" },␊
466␉{ 0x10DE063A, "Quadro FX 2700M" },␊
467␉// 0640 - 064F␊
468␉{ 0x10DE0640, "GeForce 9500 GT" },␊
469␉{ 0x10DE0641, "GeForce 9400 GT" },␊
470␉{ 0x10DE0642, "GeForce 8400 GS" },␊
471␉{ 0x10DE0643, "GeForce 9500 GT" },␊
472␉{ 0x10DE0644, "GeForce 9500 GS" },␊
473␉{ 0x10DE0645, "GeForce 9500 GS" },␊
474␉{ 0x10DE0646, "GeForce GT 120" },␊
475␉{ 0x10DE0647, "GeForce 9600M GT" },␊
476␉{ 0x10DE0648, "GeForce 9600M GS" },␊
477␉{ 0x10DE0649, "GeForce 9600M GT" },␊
478␉{ 0x10DE064A, "GeForce 9700M GT" },␊
479␉{ 0x10DE064B, "GeForce 9500M G" },␊
480␉{ 0x10DE064C, "GeForce 9650M GT" },␊
481␉// 0650 - 065F␊
482␉{ 0x10DE0651, "GeForce G 110M" },␊
483␉{ 0x10DE0652, "GeForce GT 130M" },␊
484␉{ 0x10DE0653, "GeForce GT 120M" },␊
485␉{ 0x10DE0654, "GeForce GT 220M" },␊
486␉{ 0x10DE0655, "GeForce GT 120" },␊
487␉{ 0x10DE0656, "GeForce 9650 S" },␊
488␉{ 0x10DE0658, "Quadro FX 380" },␊
489␉{ 0x10DE0659, "Quadro FX 580" },␊
490␉{ 0x10DE065A, "Quadro FX 1700M" },␊
491␉{ 0x10DE065B, "GeForce 9400 GT" },␊
492␉{ 0x10DE065C, "Quadro FX 770M" },␊
493␉{ 0x10DE065F, "GeForce G210" },␊
494␉// 0660 - 066F␊
495␉// 0670 - 067F␊
496␉// 0680 - 068F␊
497␉// 0690 - 069F␊
498␉// 06A0 - 06AF␊
499␉// 06B0 - 06BF␊
500␉// 06C0 - 06CF␊
501␉{ 0x10DE06C0, "GeForce GTX 480" },␊
502␉{ 0x10DE06C3, "GeForce GTX D12U" },␊
503␉{ 0x10DE06C4, "GeForce GTX 465" },␊
504␉{ 0x10DE06CA, "GeForce GTX 480M" },␊
505␉{ 0x10DE06CD, "GeForce GTX 470" },␊
506␉// 06D0 - 06DF␊
507␉{ 0x10DE06D1, "Tesla C2050 / C2070" },␊
508␉// { 0x10DE06D1, 0x0771, "Tesla C2050" },␊
509␉// { 0x10DE06D1, 0x0772, "Tesla C2070" },␊
510␉{ 0x10DE06D2, "Tesla M2070 / M2070" },␊
511␉// { 0x10DE06D2, 0x082F, "Tesla M2050" },␊
512␉// { 0x10DE06D2, 0x082F, "Tesla M2070" },␊
513␉{ 0x10DE06D8, "Quadro 6000" },␊
514␉{ 0x10DE06D9, "Quadro 5000" },␊
515␉{ 0x10DE06DA, "Quadro 5000M" },␊
516␉{ 0x10DE06DC, "Quadro 6000" },␊
517␉{ 0x10DE06DD, "Quadro 4000" },␊
518␉{ 0x10DE06DE, "Tesla M2050" },␊
519␉// { 0x10DE06DE, 0x082F, "Tesla M2050" },␊
520␉// { 0x10DE06DE, 0x0846, "Tesla M2050" },␊
521␉{ 0x10DE06DF, "Tesla M2070-Q" },␊
522␉// 06E0 - 06EF␊
523␉{ 0x10DE06E0, "GeForce 9300 GE" },␊
524␉{ 0x10DE06E1, "GeForce 9300 GS" },␊
525␉{ 0x10DE06E2, "GeForce 8400" },␊
526␉{ 0x10DE06E3, "GeForce 8400 SE" },␊
527␉{ 0x10DE06E4, "GeForce 8400 GS" },␊
528␉{ 0x10DE06E5, "GeForce 9300M GS" },␊
529␉{ 0x10DE06E6, "GeForce G100" },␊
530␉{ 0x10DE06E7, "GeForce 9300 SE" },␊
531␉{ 0x10DE06E8, "GeForce 9200M GS" },␊
532␉{ 0x10DE06E9, "GeForce 9300M GS" },␊
533␉{ 0x10DE06EA, "Quadro NVS 150M" },␊
534␉{ 0x10DE06EB, "Quadro NVS 160M" },␊
535␉{ 0x10DE06EC, "GeForce G 105M" },␊
536␉{ 0x10DE06EF, "GeForce G 103M" },␊
537␉// 06F0 - 06FF␊
538␉{ 0x10DE06F1, "GeForce G105M" },␊
539␉{ 0x10DE06F8, "Quadro NVS 420" },␊
540␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊
541␉{ 0x10DE06FA, "Quadro NVS 450" },␊
542␉{ 0x10DE06FB, "Quadro FX 370M" },␊
543␉{ 0x10DE06FD, "Quadro NVS 295" },␊
544␉{ 0x10DE06FF, "HICx16 + Graphics" },␊
545␉// 0700 - 070F␊
546␉// 0710 - 071F␊
547␉// 0720 - 072F␊
548␉// 0730 - 073F␊
549␉// 0740 - 074F␊
550␉// 0750 - 075F␊
551␉// 0760 - 076F␊
552␉// 0770 - 077F␊
553␉// 0780 - 078F␊
554␉// 0790 - 079F␊
555␉// 07A0 - 07AF␊
556␉// 07B0 - 07BF␊
557␉// 07C0 - 07CF␊
558␉// 07D0 - 07DF␊
559␉// 07E0 - 07EF␊
560␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊
561␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊
562␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊
563␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊
564␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊
565␉// 07F0 - 07FF␊
566␉// 0800 - 080F␊
567␉// 0810 - 081F␊
568␉// 0820 - 082F␊
569␉// 0830 - 083F␊
570␉// 0840 - 084F␊
571␉{ 0x10DE0840, "GeForce 8200M" },␊
572␉{ 0x10DE0844, "GeForce 9100M G" },␊
573␉{ 0x10DE0845, "GeForce 8200M G" },␊
574␉{ 0x10DE0846, "GeForce 9200" },␊
575␉{ 0x10DE0847, "GeForce 9100" },␊
576␉{ 0x10DE0848, "GeForce 8300" },␊
577␉{ 0x10DE0849, "GeForce 8200" },␊
578␉{ 0x10DE084A, "nForce 730a" },␊
579␉{ 0x10DE084B, "GeForce 9200" },␊
580␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊
581␉{ 0x10DE084D, "nForce 750a SLI" },␊
582␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊
583␉// 0850 - 085F␊
584␉// 0860 - 086F␊
585␉{ 0x10DE0860, "GeForce 9400" },␊
586␉{ 0x10DE0861, "GeForce 9400" },␊
587␉{ 0x10DE0862, "GeForce 9400M G" },␊
588␉{ 0x10DE0863, "GeForce 9400M" },␊
589␉{ 0x10DE0864, "GeForce 9300" },␊
590␉{ 0x10DE0865, "ION" },␊
591␉{ 0x10DE0866, "GeForce 9400M G" },␊
592␉{ 0x10DE0867, "GeForce 9400" },␊
593␉{ 0x10DE0868, "nForce 760i SLI" },␊
594␉{ 0x10DE0869, "GeForce 9400" },␊
595␉{ 0x10DE086A, "GeForce 9400" },␊
596␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊
597␉{ 0x10DE086D, "GeForce 9200" },␊
598␉{ 0x10DE086E, "GeForce 9100M G" },␊
599␉{ 0x10DE086F, "GeForce 8200M G" },␊
600␉// 0870 - 087F␊
601␉{ 0x10DE0870, "GeForce 9400M" },␊
602␉{ 0x10DE0871, "GeForce 9200" },␊
603␉{ 0x10DE0872, "GeForce G102M" },␊
604␉{ 0x10DE0873, "GeForce G102M" },␊
605␉{ 0x10DE0874, "ION" },␊
606␉{ 0x10DE0876, "ION" },␊
607␉{ 0x10DE087A, "GeForce 9400" },␊
608␉{ 0x10DE087D, "ION" },␊
609␉{ 0x10DE087E, "ION LE" },␊
610␉{ 0x10DE087F, "ION LE" },␊
611␉// 0880 - 088F␊
612␉// 0890 - 089F␊
613␉// 08A0 - 08AF␊
614␉{ 0x10DE08A0, "GeForce 320M" },␊
615␉{ 0x10DE08A4, "GeForce 320M" },␊
616␉{ 0x10DE08A5, "GeForce 320M" },␊
617␉// 08B0 - 08BF␊
618␉// 08C0 - 08CF␊
619␉// 08D0 - 08DF␊
620␉// 08E0 - 08EF␊
621␉// 08F0 - 08FF␊
622␉// 0900 - 090F␊
623␉// 0910 - 091F␊
624␉// 0920 - 092F␊
625␉// 0930 - 093F␊
626␉// 0940 - 094F␊
627␉// 0950 - 095F␊
628␉// 0960 - 096F␊
629␉// 0970 - 097F␊
630␉// 0980 - 098F␊
631␉// 0990 - 099F␊
632␉// 09A0 - 09AF␊
633␉// 09B0 - 09BF␊
634␉// 09C0 - 09CF␊
635␉// 09D0 - 09DF␊
636␉// 09E0 - 09EF␊
637␉// 09F0 - 09FF␊
638␉// 0A00 - 0A0F␊
639␉// 0A10 - 0A1F␊
640␉// 0A20 - 0A2F␊
641␉{ 0x10DE0A20, "GeForce GT220" },␊
642␉{ 0x10DE0A22, "GeForce 315" },␊
643␉{ 0x10DE0A23, "GeForce 210" },␊
644␉{ 0x10DE0A26, "GeForce 405" },␊
645␉{ 0x10DE0A27, "GeForce 405" },␊
646␉{ 0x10DE0A28, "GeForce GT 230M" },␊
647␉{ 0x10DE0A29, "GeForce GT 330M" },␊
648␉{ 0x10DE0A2A, "GeForce GT 230M" },␊
649␉{ 0x10DE0A2B, "GeForce GT 330M" },␊
650␉{ 0x10DE0A2C, "NVS 5100M" },␊
651␉{ 0x10DE0A2D, "GeForce GT 320M" },␊
652␉// 0A30 - 0A3F␊
653␉{ 0x10DE0A34, "GeForce GT 240M" },␊
654␉{ 0x10DE0A35, "GeForce GT 325M" },␊
655␉{ 0x10DE0A38, "Quadro 400" },␊
656␉{ 0x10DE0A3C, "Quadro FX 880M" },␊
657␉// 0A40 - 0A4F␊
658␉// 0A50 - 0A5F␊
659␉// 0A60 - 0A6F␊
660␉{ 0x10DE0A60, "GeForce G210" },␊
661␉{ 0x10DE0A62, "GeForce 205" },␊
662␉{ 0x10DE0A63, "GeForce 310" },␊
663␉{ 0x10DE0A64, "ION" },␊
664␉{ 0x10DE0A65, "GeForce 210" },␊
665␉{ 0x10DE0A66, "GeForce 310" },␊
666␉{ 0x10DE0A67, "GeForce 315" },␊
667␉{ 0x10DE0A68, "GeForce G105M" },␊
668␉{ 0x10DE0A69, "GeForce G105M" },␊
669␉{ 0x10DE0A6A, "NVS 2100M" },␊
670␉{ 0x10DE0A6C, "NVS 3100M" },␊
671␉{ 0x10DE0A6E, "GeForce 305M" },␊
672␉{ 0x10DE0A6F, "ION" },␊
673␉// 0A70 - 0A7F␊
674␉{ 0x10DE0A70, "GeForce 310M" },␊
675␉{ 0x10DE0A71, "GeForce 305M" },␊
676␉{ 0x10DE0A72, "GeForce 310M" },␊
677␉{ 0x10DE0A73, "GeForce 305M" },␊
678␉{ 0x10DE0A74, "GeForce G210M" },␊
679␉{ 0x10DE0A75, "GeForce 310M" },␊
680␉{ 0x10DE0A76, "ION" },␊
681␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊
682␉{ 0x10DE0A7A, "GeForce 315M" },␊
683␉{ 0x10DE0A7C, "Quadro FX 380M" },␊
684␉// 0A80 - 0A8F␊
685␉// 0A90 - 0A9F␊
686␉// 0AA0 - 0AAF␊
687␉// 0AB0 - 0ABF␊
688␉// 0AC0 - 0ACF␊
689␉// 0AD0 - 0ADF␊
690␉// 0AE0 - 0AEF␊
691␉// 0AF0 - 0AFF␊
692␉// 0B00 - 0B0F␊
693␉// 0B10 - 0B1F␊
694␉// 0B20 - 0B2F␊
695␉// 0B30 - 0B3F␊
696␉// 0B40 - 0B4F␊
697␉// 0B50 - 0B5F␊
698␉// 0B60 - 0B6F␊
699␉// 0B70 - 0B7F␊
700␉// 0B80 - 0B8F␊
701␉// 0B90 - 0B9F␊
702␉// 0BA0 - 0BAF␊
703␉// 0BB0 - 0BBF␊
704␉// 0BC0 - 0BCF␊
705␉// 0BD0 - 0BDF␊
706␉// 0BE0 - 0BEF␊
707␉// 0BF0 - 0BFF␊
708␉// 0C00 - 0C0F␊
709␉// 0C10 - 0C1F␊
710␉// 0C20 - 0C2F␊
711␉// 0C30 - 0C3F␊
712␉// 0C40 - 0C4F␊
713␉// 0C50 - 0C5F␊
714␉// 0C60 - 0C6F␊
715␉// 0C70 - 0C7F␊
716␉// 0C80 - 0C8F␊
717␉// 0C90 - 0C9F␊
718␉// 0CA0 - 0CAF␊
719␉{ 0x10DE0CA0, "GeForce GT 330 " },␊
720␉{ 0x10DE0CA2, "GeForce GT 320" },␊
721␉{ 0x10DE0CA3, "GeForce GT 240" },␊
722␉{ 0x10DE0CA4, "GeForce GT 340" },␊
723␉{ 0x10DE0CA5, "GeForce GT 220" },␊
724␉{ 0x10DE0CA7, "GeForce GT 330" },␊
725␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊
726␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊
727␉{ 0x10DE0CAC, "GeForce GT 220" },␊
728␉{ 0x10DE0CAF, "GeForce GT 335M" },␊
729␉// 0CB0 - 0CBF␊
730␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊
731␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊
732␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊
733␉// 0CC0 - 0CCF␊
734␉// 0CD0 - 0CDF␊
735␉// 0CE0 - 0CEF␊
736␉// 0CF0 - 0CFF␊
737␉// 0D00 - 0D0F␊
738␉// 0D10 - 0D1F␊
739␉// 0D20 - 0D2F␊
740␉// 0D30 - 0D3F␊
741␉// 0D40 - 0D4F␊
742␉// 0D50 - 0D5F␊
743␉// 0D60 - 0D6F␊
744␉// 0D70 - 0D7F␊
745␉// 0D80 - 0D8F␊
746␉// 0D90 - 0D9F␊
747␉// 0DA0 - 0DAF␊
748␉// 0DB0 - 0DBF␊
749␉// 0DC0 - 0DCF␊
750␉{ 0x10DE0DC0, "GeForce GT 440" },␊
751␉{ 0x10DE0DC1, "D12-P1-35" },␊
752␉{ 0x10DE0DC2, "D12-P1-35" },␊
753␉{ 0x10DE0DC4, "GeForce GTS 450" },␊
754␉{ 0x10DE0DC5, "GeForce GTS 450" },␊
755␉{ 0x10DE0DC6, "GeForce GTS 450" },␊
756␉{ 0x10DE0DCA, "GF10x" },␊
757␉{ 0x10DE0DCD, "GeForce GT 555M" },␊
758␉{ 0x10DE0DCE, "GeForce GT 555M" },␊
759␉// 0DD0 - 0DDF␊
760␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊
761␉{ 0x10DE0DD2, "GeForce GT 445M" },␊
762␉{ 0x10DE0DD3, "GeForce GT 435M" },␊
763␉{ 0x10DE0DD6, "GeForce GT 550M" },␊
764␉{ 0x10DE0DD8, "Quadro 2000" },␊
765␉{ 0x10DE0DDA, "Quadro 2000M" },␊
766␉{ 0x10DE0DDE, "GF106-ES" },␊
767␉{ 0x10DE0DDF, "GF106-INT" },␊
768␉// 0DE0 - 0DEF␊
769␉{ 0x10DE0DE0, "GeForce GT 440" },␊
770␉{ 0x10DE0DE1, "GeForce GT 430" },␊
771␉{ 0x10DE0DE2, "GeForce GT 420" },␊
772␉{ 0x10DE0DE4, "GeForce GT 520" },␊
773␉{ 0x10DE0DE5, "GeForce GT 530" },␊
774␉{ 0x10DE0DE9, "GeForce GT 630M" },␊
775␉{ 0x10DE0DEB, "GeForce GT 555M" },␊
776␉{ 0x10DE0DEC, "GeForce GT 525M" },␊
777␉{ 0x10DE0DED, "GeForce GT 520M" },␊
778␉{ 0x10DE0DEE, "GeForce GT 415M" },␊
779␉// 0DF0 - 0DFF␊
780␉{ 0x10DE0DF0, "GeForce GT 425M" },␊
781␉{ 0x10DE0DF1, "GeForce GT 420M" },␊
782␉{ 0x10DE0DF2, "GeForce GT 435M" },␊
783␉{ 0x10DE0DF3, "GeForce GT 420M" },␊
784␉{ 0x10DE0DF4, "GeForce GT 540M" },␊
785␉{ 0x10DE0DF5, "GeForce GT 525M" },␊
786␉{ 0x10DE0DF6, "GeForce GT 550M" },␊
787␉{ 0x10DE0DF7, "GeForce GT 520M" },␊
788␉{ 0x10DE0DF8, "Quadro 600" },␊
789␉{ 0x10DE0DFA, "Quadro 1000M" },␊
790␉{ 0x10DE0DFC, "NVS 5200M" },␊
791␉{ 0x10DE0DFE, "GF108 ES" },␊
792␉{ 0x10DE0DFF, "GF108 INT" },␊
793␉// 0E00 - 0E0F␊
794␉// 0E10 - 0E1F␊
795␉// 0E20 - 0E2F␊
796␉{ 0x10DE0E21, "D12U-25" },␊
797␉{ 0x10DE0E22, "GeForce GTX 460" },␊
798␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊
799␉{ 0x10DE0E24, "GeForce GTX 460" },␊
800␉{ 0x10DE0E25, "D12U-50" },␊
801␉// 0E30 - 0E3F␊
802␉{ 0x10DE0E30, "GeForce GTX 470M" },␊
803␉{ 0x10DE0E31, "GeForce GTX 485M" },␊
804␉{ 0x10DE0E38, "GF104GL" },␊
805␉{ 0x10DE0E3A, "Quadro 3000M" },␊
806␉{ 0x10DE0E3B, "Quadro 4000M" },␊
807␉{ 0x10DE0E3E, "GF104-ES" },␊
808␉{ 0x10DE0E3F, "GF104-INT" },␊
809␉// 0E40 - 0E4F␊
810␉// 0E50 - 0E5F␊
811␉// 0E60 - 0E6F␊
812␉// 0E70 - 0E7F␊
813␉// 0E80 - 0E8F␊
814␉// 0E90 - 0E9F␊
815␉// 0EA0 - 0EAF␊
816␉// 0EB0 - 0EBF␊
817␉// 0EC0 - 0ECF␊
818␉// 0ED0 - 0EDF␊
819␉// 0EE0 - 0EEF␊
820␉// 0EF0 - 0EFF␊
821␉// 0F00 - 0F0F␊
822␉// 0F10 - 0F1F␊
823␉// 0F20 - 0F2F␊
824␉// 0F30 - 0F3F␊
825␉// 0F40 - 0F4F␊
826␉// 0F50 - 0F5F␊
827␉// 0F60 - 0F6F␊
828␉// 0F70 - 0F7F␊
829␉// 0F80 - 0F8F␊
830␉// 0F90 - 0F9F␊
831␉// 0FA0 - 0FAF␊
832␉// 0FB0 - 0FBF␊
833␉// 0FC0 - 0FCF␊
834␉// 0FD0 - 0FDF␊
835␉// 0FE0 - 0FEF␊
836␉// 0FF0 - 0FFF␊
837␉// 1000 - 100F␊
838␉// 1010 - 101F␊
839␉// 1020 - 102F␊
840␉// 1030 - 103F␊
841␉// 1040 - 104F␊
842␉{ 0x10DE1040, "GeForce GT 520" },␊
843␉{ 0x10DE1042, "GeForce 510" },␊
844␉{ 0x10DE1049, "GeForce GT 620" },␊
845␉// 1050 - 105F␊
846␉{ 0x10DE1050, "GeForce GT 520M" },␊
847␉{ 0x10DE1051, "GeForce GT 520MX" },␊
848␉{ 0x10DE1054, "GeForce GT 410M" },␊
849␉{ 0x10DE1055, "GeForce 410M" },␊
850␉{ 0x10DE1056, "Quadro NVS 4200M" },␊
851␉{ 0x10DE1057, "Quadro NVS 4200M" },␊
852␉// 1060 - 106F␊
853␉// 1070 - 107F␊
854␉{ 0x10DE107F, "NVIDIA GF119-ES" },␊
855␉// 1080 - 108F␊
856␉{ 0x10DE1080, "GeForce GTX 580" },␊
857␉{ 0x10DE1081, "GeForce GTX 570" },␊
858␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊
859␉{ 0x10DE1083, "D13U" },␊
860␉{ 0x10DE1084, "GeForce GTX 560" },␊
861␉{ 0x10DE1086, "GeForce GTX 570" },␊
862␉{ 0x10DE1087, "GeForce GTX 560 Ti 448" },␊
863␉{ 0x10DE1088, "GeForce GTX 590" },␊
864␉{ 0x10DE1089, "GeForce GTX 580" },␊
865␉{ 0x10DE108B, "GeForce GTX 590" },␊
866␉// 1090 - 109F␊
867␉{ 0x10DE1091, "Tesla M2090 / X2090" },␊
868␉// { 0x10DE1091, 0x0974, "Tesla X2090" },␊
869␉{ 0x10DE1094, "Tesla M2075" },␊
870␉{ 0x10DE1096, "Tesla C2075" },␊
871␉{ 0x10DE1098, "D13U" },␊
872␉{ 0x10DE109A, "Quadro 5010M" },␊
873␉{ 0x10DE109B, "Quadro 7000" },␊
874␉// 10A0 - 10AF␊
875␉// 10B0 - 10BF␊
876␉// 10C0 - 10CF␊
877␉{ 0x10DE10C0, "GeForce 9300 GS" },␊
878␉{ 0x10DE10C3, "GeForce 8400 GS" },␊
879␉{ 0x10DE10C5, "GeForce 405" },␊
880␉// 10D0 - 10DF␊
881␉{ 0x10DE10D8, "NVS 300" },␊
882␉// 10E0 - 10EF␊
883␉// 10F0 - 10FF␊
884␉// 1100 - 110F␊
885␉// 1110 - 111F␊
886␉// 1120 - 112F␊
887␉// 1130 - 113F␊
888␉// 1140 - 114F␊
889␉// 1150 - 115F␊
890␉// 1160 - 116F␊
891␉// 1170 - 117F␊
892␉// 1180 - 118F␊
893␉{ 0x10DE1180, "GeForce GTX 680" },␊
894␉// 1190 - 119F␊
895␉// 11A0 - 11AF␊
896␉// 11B0 - 11BF␊
897␉// 11C0 - 11CF␊
898␉// 11D0 - 11DF␊
899␉// 11E0 - 11EF␊
900␉// 11F0 - 11FF␊
901␉// 1200 - 120F␊
902␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊
903␉{ 0x10DE1201, "GeForce GTX 560" },␊
904␉{ 0x10DE1203, "GeForce GTX 460 SE v2" },␊
905␉// 1210 - 121F␊
906␉{ 0x10DE1210, "GeForce GTX 570M" },␊
907␉{ 0x10DE1211, "GeForce GTX 580M" },␊
908␉// 1220 - 122F␊
909␉// 1230 - 123F␊
910␉// 1240 - 124F␊
911␉{ 0x10DE1241, "GeForce GT 545" },␊
912␉{ 0x10DE1243, "GeForce GT 545" },␊
913␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊
914␉{ 0x10DE1245, "GeForce GTS 450" },␊
915␉{ 0x10DE1247, "GeForce GT 555M / GT 635M" },␊
916␉// { 0x10DE1247, 0x212A, "GT 635M" },␊
917␉// { 0x10DE1247, 0x212B, "GT 635M" },␊
918␉// { 0x10DE1247, 0x212C, "GT 635M" },␊
919␉// 1250 - 125F␊
920␉{ 0x10DE1251, "GeForce GTX 560M" },␊
921␉// 1260 - 126F␊
922␉// 1270 - 127F␊
923␉// 1280 - 128F␊
924␉// 1290 - 129F␊
925␉// 12A0 - 12AF␊
926␉// 12B0 - 12BF␊
927␉// 12C0 - 12CF␊
928␉// 12D0 - 12DF␊
929␉// 12E0 - 12EF␊
930␉// 12F0 - 12FF␊
931};␊
932␊
933static uint16_t swap16(uint16_t x)␊
934{␊
935␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊
936}␊
937␊
938static uint16_t read16(uint8_t *ptr, uint16_t offset)␊
939{␊
940␉uint8_t ret[2];␊
941␉␊
942␉ret[0] = ptr[offset+1];␊
943␉ret[1] = ptr[offset];␊
944␉␊
945␉return *((uint16_t*)&ret);␊
946}␊
947␊
948#if 0␊
949static uint32_t swap32(uint32_t x)␊
950{␊
951␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊
952}␊
953␊
954static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊
955{ ␊
956␉return ptr[offset];␊
957}␊
958␊
959static uint32_t read32(uint8_t *ptr, uint16_t offset)␊
960{␊
961␉uint8_t ret[4];␊
962␉␊
963␉ret[0] = ptr[offset+3];␊
964␉ret[1] = ptr[offset+2];␊
965␉ret[2] = ptr[offset+1];␊
966␉ret[3] = ptr[offset];␊
967␉␊
968␉return *((uint32_t*)&ret);␊
969}␊
970#endif␊
971␊
972static int patch_nvidia_rom(uint8_t *rom)␊
973{␊
974␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊
975␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊
976␉␉return PATCH_ROM_FAILED;␊
977␉}␊
978␉␊
979␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊
980␉␊
981␉if (!dcbptr) {␊
982␉␉printf("no dcb table found\n");␊
983␉␉return PATCH_ROM_FAILED;␊
984␉}␊
985//␉else␊
986//␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊
987␉ ␊
988␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊
989␉uint8_t dcbtable_version = dcbtable[0];␊
990␉uint8_t headerlength␉ = 0;␊
991␉uint8_t numentries␉␉ = 0;␊
992␉uint8_t recordlength␉ = 0;␊
993␉␊
994␉if (dcbtable_version >= 0x20)␊
995␉{␊
996␉␉uint32_t sig;␊
997␉␉␊
998␉␉if (dcbtable_version >= 0x30)␊
999␉␉{␊
1000␉␉␉headerlength = dcbtable[1];␊
1001␉␉␉numentries␉ = dcbtable[2];␊
1002␉␉␉recordlength = dcbtable[3];␊
1003␊
1004␉␉␉sig = *(uint32_t *)&dcbtable[6];␊
1005␉␉}␊
1006␉␉else␊
1007␉␉{␊
1008␉␉␉sig = *(uint32_t *)&dcbtable[4];␊
1009␉␉␉headerlength = 8;␊
1010␉␉}␊
1011␉␉␊
1012␉␉if (sig != 0x4edcbdcb)␊
1013␉␉{␊
1014␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊
1015␉␉␉return PATCH_ROM_FAILED;␊
1016␉␉}␊
1017␉}␊
1018␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊
1019␉{␊
1020␉␉char sig[8] = { 0 };␊
1021␉␉␊
1022␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊
1023␉␉recordlength = 10;␊
1024␉␉␊
1025␉␉if (strcmp(sig, "DEV_REC"))␊
1026␉␉{␊
1027␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊
1028␉␉␉return PATCH_ROM_FAILED;␊
1029␉␉}␊
1030␉}␊
1031␉else␊
1032␉{␊
1033␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊
1034␉␉return PATCH_ROM_FAILED;␊
1035␉}␊
1036␉␊
1037␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊
1038␉␉numentries = MAX_NUM_DCB_ENTRIES;␊
1039␉␊
1040␉uint8_t num_outputs = 0, i = 0;␊
1041␉␊
1042␉struct dcbentry␊
1043␉{␊
1044␉␉uint8_t type;␊
1045␉␉uint8_t index;␊
1046␉␉uint8_t *heads;␊
1047␉} entries[numentries];␊
1048␉␊
1049␉for (i = 0; i < numentries; i++)␊
1050␉{␊
1051␉␉uint32_t connection;␊
1052␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊
1053␊
1054␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊
1055␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊
1056␉␉␉continue;␊
1057␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊
1058␉␉␉continue;␊
1059␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊
1060␉␉␉continue;␊
1061␉␉␊
1062␉␉entries[num_outputs].type = connection & 0xf;␊
1063␉␉entries[num_outputs].index = num_outputs;␊
1064␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊
1065␉}␊
1066␉␊
1067␉int has_lvds = false;␊
1068␉uint8_t channel1 = 0, channel2 = 0;␊
1069␉␊
1070␉for (i = 0; i < num_outputs; i++)␊
1071␉{␊
1072␉␉if (entries[i].type == 3)␊
1073␉␉{␊
1074␉␉␉has_lvds = true;␊
1075␉␉␉//printf("found LVDS\n");␊
1076␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1077␉␉␉entries[i].type = TYPE_GROUPED;␊
1078␉␉}␊
1079␉}␊
1080␉␊
1081␉// if we have a LVDS output, we group the rest to the second channel␊
1082␉if (has_lvds)␊
1083␉{␊
1084␉␉for (i = 0; i < num_outputs; i++)␊
1085␉␉{␊
1086␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1087␉␉␉␉continue;␊
1088␉␉␉␊
1089␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1090␉␉␉entries[i].type = TYPE_GROUPED;␊
1091␉␉}␊
1092␉}␊
1093␉else␊
1094␉{␊
1095␉␉int x;␊
1096␉␉// we loop twice as we need to generate two channels␊
1097␉␉for (x = 0; x <= 1; x++)␊
1098␉␉{␊
1099␉␉␉for (i=0; i<num_outputs; i++)␊
1100␉␉␉{␊
1101␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊
1102␉␉␉␉␉continue;␊
1103␉␉␉␉// if type is TMDS, the prior output is ANALOG␊
1104␉␉␉␉// we always group ANALOG and TMDS␊
1105␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊
1106␉␉␉␉if (i && entries[i].type == 0x2)␊
1107␉␉␉␉{␊
1108␉␉␉␉␉switch (x)␊
1109␉␉␉␉␉{␊
1110␉␉␉␉␉␉case 0:␊
1111␉␉␉␉␉␉␉//printf("group channel 1\n");␊
1112␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊
1113␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1114␉␉␉␉␉␉␉␊
1115␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊
1116␉␉␉␉␉␉␉{␊
1117␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊
1118␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1119␉␉␉␉␉␉␉}␊
1120␉␉␉␉␉␉␉// group TV as well if there is one␊
1121␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1122␉␉␉␉␉␉␉{␊
1123␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊
1124␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊
1125␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1126␉␉␉␉␉␉␉}␊
1127␉␉␉␉␉␉␉break;␊
1128␉␉␉␉␉␉␊
1129␉␉␉␉␉␉case 1:␊
1130␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊
1131␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊
1132␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊
1133␉␉␉␉␉␉␉␊
1134␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊
1135␉␉␉␉␉␉␉{␊
1136␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊
1137␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊
1138␉␉␉␉␉␉␉}␊
1139␉␉␉␉␉␉␉// group TV as well if there is one␊
1140␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊
1141␉␉␉␉␉␉␉{␊
1142␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊
1143␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊
1144␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊
1145␉␉␉␉␉␉␉}␊
1146␉␉␉␉␉␉␉break;␊
1147␉␉␉␉␉}␊
1148␉␉␉␉␉break;␊
1149␉␉␉␉}␊
1150␉␉␉}␊
1151␉␉}␊
1152␉}␊
1153␉␊
1154␉// if we have left ungrouped outputs merge them to the empty channel␊
1155␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊
1156␉togroup = &channel2;␊
1157␉␊
1158␉for (i = 0; i < num_outputs; i++)␊
1159␉{␊
1160␉␉if (entries[i].type != TYPE_GROUPED)␊
1161␉␉{␊
1162␉␉␉//printf("%d not grouped\n", i);␊
1163␉␉␉if (togroup)␊
1164␉␉␉{␊
1165␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊
1166␉␉␉}␊
1167␉␉␉entries[i].type = TYPE_GROUPED;␊
1168␉␉}␊
1169␉}␊
1170␉␊
1171␉if (channel1 > channel2)␊
1172␉{␊
1173␉␉uint8_t buff = channel1;␊
1174␉␉channel1 = channel2;␊
1175␉␉channel2 = buff;␊
1176␉}␊
1177␉␊
1178␉default_NVCAP[6] = channel1;␊
1179␉default_NVCAP[8] = channel2;␊
1180␉␊
1181␉// patching HEADS␊
1182␉for (i = 0; i < num_outputs; i++)␊
1183␉{␊
1184␉␉if (channel1 & (1 << i))␊
1185␉␉{␊
1186␉␉␉*entries[i].heads = 1;␊
1187␉␉}␊
1188␉␉else if(channel2 & (1 << i))␊
1189␉␉{␊
1190␉␉␉*entries[i].heads = 2;␊
1191␉␉}␊
1192␉}␊
1193␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊
1194}␊
1195␊
1196static char *get_nvidia_model(uint32_t id)␊
1197{␊
1198␉int i;␊
1199␉␊
1200␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊
1201␉␉if (NVKnownChipsets[i].device == id)␊
1202␉␉{␊
1203␉␉␉return NVKnownChipsets[i].name;␊
1204␉␉}␊
1205␉}␊
1206␉return NVKnownChipsets[0].name;␊
1207}␊
1208␊
1209static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊
1210{␊
1211␉int fd;␊
1212␉int size;␊
1213␉␊
1214␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊
1215␉{␊
1216␉␉return 0;␊
1217␉}␊
1218␉␊
1219␉size = file_size(fd);␊
1220␉␊
1221␉if (size > bufsize)␊
1222␉{␊
1223␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊
1224␉␉␉␉filename, bufsize);␊
1225␉␉size = bufsize;␊
1226␉}␊
1227␉size = read(fd, (char *)buf, size);␊
1228␉close(fd);␊
1229␉␊
1230␉return size > 0 ? size : 0;␊
1231}␊
1232␊
1233static int devprop_add_nvidia_template(struct DevPropDevice *device)␊
1234{␊
1235␉char tmp[16];␊
1236␉␊
1237␉if (!device)␊
1238␉␉return 0;␊
1239␉␊
1240␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊
1241␉␉return 0;␊
1242␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊
1243␉␉return 0;␊
1244␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊
1245␉␉return 0;␊
1246␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊
1247␉␉return 0;␊
1248␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊
1249␉␉return 0;␊
1250␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊
1251␉␉return 0;␊
1252␉if (devices_number == 1)␊
1253␉{␊
1254 if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
1255 return 0;␊
1256␉}␊
1257␉else␊
1258␉{␊
1259␉␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
1260␉␉␉return 0;␊
1261␉}␊
1262␉␊
1263␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
1264␉// len = sprintf(tmp, "Slot-%x", devices_number);␊
1265␉sprintf(tmp, "Slot-%x",devices_number);␊
1266␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊
1267␉devices_number++;␊
1268␉␊
1269␉return 1;␊
1270}␊
1271␊
1272int hex2bin(const char *hex, uint8_t *bin, int len)␊
1273{␊
1274␉char␉*p;␊
1275␉int␉␉i;␊
1276␉char␉buf[3];␊
1277␉␊
1278␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊
1279␉␉printf("[ERROR] bin2hex input error\n");␊
1280␉␉return -1;␊
1281␉}␊
1282␉␊
1283␉buf[2] = '\0';␊
1284␉p = (char *) hex;␊
1285␉␊
1286␉for (i = 0; i < len; i++)␊
1287␉{␊
1288␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊
1289␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊
1290␉␉␉return -2;␊
1291␉␉}␊
1292␉␉buf[0] = *p++;␊
1293␉␉buf[1] = *p++;␊
1294␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊
1295␉}␊
1296␉return 0;␊
1297}␊
1298␊
1299unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊
1300{␊
1301␉unsigned long long vram_size = 0;␊
1302␉␊
1303␉if (nvCardType < NV_ARCH_50)␊
1304␉{␊
1305␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1306␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊
1307␉}␊
1308␉else if (nvCardType < NV_ARCH_C0)␊
1309␉{␊
1310␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊
1311␉␉vram_size |= (vram_size & 0xff) << 32;␊
1312␉␉vram_size &= 0xffffffff00ll;␊
1313␉}␊
1314␉else // >= NV_ARCH_C0␊
1315␉{␊
1316␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊
1317␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊
1318␉}␊
1319␉␊
1320␉// Workaround for wrong RAM size detected␊
1321␉switch (nvda_dev->device_id)␊
1322␉{␊
1323␉␉case 0x0649: // 9600M GT␊
1324 vram_size = 512*1024*1024; // 512 MB␊
1325 break;␊
1326␉␉case 0x0DE0: // GT 440␊
1327␉␉case 0x0DE1: // GT 430␊
1328␉␉case 0x0DE2: // GT 420␊
1329␉␉case 0x0DEC: // GT 525M␊
1330␉␉case 0x0DF4: // GT 540M␊
1331␉␉case 0x0DF5: // GT 525M␊
1332 vram_size = 1024*1024*1024; // 1 GB␊
1333␉␉␉break;␊
1334␉␉default:␊
1335 break;␊
1336␉}␊
1337␉␊
1338␉return vram_size;␊
1339}␊
1340␊
1341bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
1342{␊
1343␉struct DevPropDevice␉*device;␊
1344␉char␉␉␉␉␉*devicepath;␊
1345␉option_rom_pci_header_t *rom_pci_header;␊
1346␉volatile uint8_t␉␉*regs;␊
1347␉uint8_t␉␉␉␉␉*rom;␊
1348␉uint8_t␉␉␉␉␉*nvRom;␊
1349␉uint8_t␉␉␉␉␉nvCardType;␊
1350␉unsigned long long␉␉videoRam;␊
1351␉uint32_t␉␉␉␉nvBiosOveride;␊
1352␉uint32_t␉␉␉␉bar[7];␊
1353␉uint32_t␉␉␉␉boot_display;␊
1354␉int␉␉␉␉␉␉nvPatch;␊
1355␉int␉␉␉␉␉␉len;␊
1356␉char␉␉␉␉␉biosVersion[32];␊
1357␉char␉␉␉␉␉nvFilename[32];␊
1358␉char␉␉␉␉␉kNVCAP[12];␊
1359␉char␉␉␉␉␉*model;␊
1360␉const char␉␉␉␉*value;␊
1361␉bool␉␉␉␉␉doit;␊
1362␉␊
1363␉devicepath = get_pci_dev_path(nvda_dev);␊
1364␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊
1365␉regs = (uint8_t *) (bar[0] & ~0x0f);␊
1366␉␊
1367␉// get card type␊
1368␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊
1369␉␊
1370␉// Amount of VRAM in kilobytes␊
1371␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊
1372␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊
1373␉␊
1374␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊
1375 model, (uint32_t)(videoRam / 1024 / 1024),␊
1376 (REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊
1377 devicepath);␊
1378␉␊
1379␉rom = malloc(NVIDIA_ROM_SIZE);␊
1380␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊
1381␉␉␉(uint16_t)nvda_dev->device_id);␊
1382␉␊
1383␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊
1384␉{␊
1385␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊
1386␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊
1387␉␉␊
1388␉␉if (nvBiosOveride > 0)␊
1389␉␉{␊
1390␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊
1391␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊
1392␉␉}␊
1393␉␉else␊
1394␉␉{␊
1395␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊
1396␉␉␉return false;␊
1397␉␉}␊
1398␉}␊
1399␉else␊
1400␉{␊
1401␉␉// Otherwise read bios from card␊
1402␉␉nvBiosOveride = 0;␊
1403␉␉␊
1404␉␉// TODO: we should really check for the signature before copying the rom, i think.␊
1405␉␉␊
1406␉␉// PRAMIN first␊
1407␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
1408␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1409␉␉␊
1410␉␉// Valid Signature ?␊
1411␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1412␉␉{␊
1413␉␉␉// PROM next␊
1414␉␉␉// Enable PROM access␊
1415␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
1416␉␉␉␊
1417␉␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
1418␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
1419␉␉␉␊
1420␉␉␉// disable PROM access␊
1421␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
1422␉␉␉␊
1423␉␉␉// Valid Signature ?␊
1424␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1425␉␉␉{␊
1426␉␉␉␉// 0xC0000 last␊
1427␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
1428␉␉␉␉␊
1429␉␉␉␉// Valid Signature ?␊
1430␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊
1431␉␉␉␉{␊
1432␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊
1433␉␉␉␉␉return false;␊
1434␉␉␉␉}␊
1435␉␉␉␉else␊
1436␉␉␉␉{␊
1437␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1438␉␉␉␉}␊
1439␉␉␉}␊
1440␉␉␉else␊
1441␉␉␉{␊
1442␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1443␉␉␉}␊
1444␉␉}␊
1445␉␉else␊
1446␉␉{␊
1447␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
1448␉␉}␊
1449␉}␊
1450␉␊
1451␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊
1452␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊
1453␉␉//return false;␊
1454␉}␊
1455␉␊
1456␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊
1457␉␊
1458␉// check for 'PCIR' sig␊
1459␉if (rom_pci_header->signature == 0x50434952)␊
1460␉{␊
1461␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊
1462␉␉{␊
1463␉␉␉// Get Model from the OpROM␊
1464␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊
1465␉␉}␊
1466␉␉else␊
1467␉␉{␊
1468␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊
1469␉␉}␊
1470␉}␊
1471␉␊
1472␉if (!string) {␊
1473␉␉string = devprop_create_string();␊
1474␉}␊
1475␉device = devprop_add_device(string, devicepath);␊
1476␉␊
1477␉/* FIXME: for primary graphics card only */␊
1478␉boot_display = 1;␊
1479␉if (devices_number == 1)␊
1480␉{␊
1481 devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊
1482␉}␊
1483␉␊
1484␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊
1485␉␉uint8_t built_in = 0x01;␊
1486␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊
1487␉}␊
1488␊
1489␉// get bios version␊
1490␉const int MAX_BIOS_VERSION_LENGTH = 32;␊
1491␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊
1492␉␊
1493␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊
1494␉␊
1495␉int i, version_start;␊
1496␉int crlf_count = 0;␊
1497␉␊
1498␉// only search the first 384 bytes␊
1499␉for (i = 0; i < 0x180; i++)␊
1500␉{␊
1501␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊
1502␉␉{␊
1503␉␉␉crlf_count++;␊
1504␉␉␉// second 0x0D0A was found, extract bios version␊
1505␉␉␉if (crlf_count == 2)␊
1506␉␉␉{␊
1507␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊
1508␉␉␉␉␊
1509␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊
1510␉␉␉␉{␊
1511␉␉␉␉␉// find start␊
1512␉␉␉␉␉if (rom[version_start] == 0x00)␊
1513␉␉␉␉␉{␊
1514␉␉␉␉␉␉version_start++;␊
1515␉␉␉␉␉␉␊
1516␉␉␉␉␉␉// strip "Version "␊
1517␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊
1518␉␉␉␉␉␉{␊
1519␉␉␉␉␉␉␉version_start += 8;␊
1520␉␉␉␉␉␉}␊
1521␉␉␉␉␉␉␊
1522␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊
1523␉␉␉␉␉␉break;␊
1524␉␉␉␉␉}␊
1525␉␉␉␉}␊
1526␉␉␉␉break;␊
1527␉␉␉}␊
1528␉␉}␊
1529␉}␊
1530␉␊
1531␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊
1532␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊
1533␉␊
1534␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊
1535␉{␊
1536␉␉uint8_t new_NVCAP[NVCAP_LEN];␊
1537␉␉␊
1538␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊
1539␉␉{␊
1540␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊
1541␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊
1542␉␉}␊
1543␉}␊
1544␉␊
1545␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊
1546␉{␊
1547␉␉uint8_t new_dcfg0[DCFG0_LEN];␊
1548␉␉␊
1549␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊
1550␉␉{␊
1551␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊
1552␉␉␉␊
1553␉␉␉verbose("Using user supplied @0,display-cfg\n");␊
1554␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊
1555␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊
1556␉␉}␊
1557␉}␊
1558␉␊
1559␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊
1560␉{␊
1561␉␉uint8_t new_dcfg1[DCFG1_LEN];␊
1562␉␉␊
1563␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊
1564␉␉{␊
1565␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊
1566␉␉␉␊
1567␉␉␉verbose("Using user supplied @1,display-cfg\n");␊
1568␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊
1569␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊
1570␉␉}␊
1571␉}␊
1572␉␊
1573#if DEBUG_NVCAP␊
1574␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊
1575␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊
1576␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊
1577␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊
1578␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
1579␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
1580#endif␊
1581␉␊
1582␉devprop_add_nvidia_template(device);␊
1583␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
1584␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊
1585␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊
1586␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊
1587␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊
1588␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊
1589␉␊
1590␉//add HDMI Audio back to nvidia␊
1591␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊
1592//␉uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊
1593//␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊
1594␉//end Nvidia HDMI Audio␊
1595␉␊
1596␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊
1597␉{␊
1598␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊
1599␉}␊
1600␉␊
1601␉stringdata = malloc(sizeof(uint8_t) * string->length);␊
1602␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊
1603␉stringlength = string->length;␊
1604␉␊
1605␉return true;␊
1606}␊
1607

Archive Download this file

Revision: 1982