1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "bootstruct.h"␊ |
9 | #include "pci.h"␊ |
10 | #include "modules.h"␊ |
11 | #include "device_inject.h"␊ |
12 | ␊ |
13 | #ifndef DEBUG_PCI␊ |
14 | #define DEBUG_PCI 0␊ |
15 | #endif␊ |
16 | ␊ |
17 | #if DEBUG_PCI␊ |
18 | #define DBG(x...)␉␉printf(x)␊ |
19 | #else␊ |
20 | #define DBG(x...)␊ |
21 | #endif␊ |
22 | ␊ |
23 | pci_dt_t␉*root_pci_dev;␊ |
24 | static char* dev_path;␉// TODO: Figure out what is going on here...␊ |
25 | ␊ |
26 | ␊ |
27 | uint8_t pci_config_read8(uint32_t pci_addr, uint8_t reg)␊ |
28 | {␊ |
29 | ␉pci_addr |= reg & ~3;␊ |
30 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
31 | ␉return inb(PCI_DATA_REG + (reg & 3));␊ |
32 | }␊ |
33 | ␊ |
34 | uint16_t pci_config_read16(uint32_t pci_addr, uint8_t reg)␊ |
35 | {␊ |
36 | ␉pci_addr |= reg & ~3;␊ |
37 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
38 | ␉return inw(PCI_DATA_REG + (reg & 2));␊ |
39 | }␊ |
40 | ␊ |
41 | uint32_t pci_config_read32(uint32_t pci_addr, uint8_t reg)␊ |
42 | {␊ |
43 | ␉pci_addr |= reg & ~3;␊ |
44 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
45 | ␉return inl(PCI_DATA_REG);␊ |
46 | }␊ |
47 | ␊ |
48 | void pci_config_write8(uint32_t pci_addr, uint8_t reg, uint8_t data)␊ |
49 | {␊ |
50 | ␉pci_addr |= reg & ~3;␊ |
51 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
52 | ␉outb(PCI_DATA_REG + (reg & 3), data);␊ |
53 | }␊ |
54 | ␊ |
55 | void pci_config_write16(uint32_t pci_addr, uint8_t reg, uint16_t data)␊ |
56 | {␊ |
57 | ␉pci_addr |= reg & ~3;␊ |
58 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
59 | ␉outw(PCI_DATA_REG + (reg & 2), data);␊ |
60 | }␊ |
61 | ␊ |
62 | void pci_config_write32(uint32_t pci_addr, uint8_t reg, uint32_t data)␊ |
63 | {␊ |
64 | ␉pci_addr |= reg & ~3;␊ |
65 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
66 | ␉outl(PCI_DATA_REG, data);␊ |
67 | }␊ |
68 | ␊ |
69 | void scan_pci_bus(pci_dt_t *start, uint8_t bus)␊ |
70 | {␊ |
71 | ␉pci_dt_t␉*new;␊ |
72 | ␉pci_dt_t␉**current = &start->children;␊ |
73 | ␉uint32_t␉id;␊ |
74 | ␉uint32_t␉pci_addr;␊ |
75 | ␉uint8_t␉␉dev;␊ |
76 | ␉uint8_t␉␉func;␊ |
77 | ␉uint8_t␉␉secondary_bus;␊ |
78 | ␉uint8_t␉␉header_type;␊ |
79 | ␉␊ |
80 | ␉for (dev = 0; dev < 32; dev++)␊ |
81 | ␉{␊ |
82 | ␉␉for (func = 0; func < 8; func++)␊ |
83 | ␉␉{␊ |
84 | ␉␉␉pci_addr = PCIADDR(bus, dev, func);␊ |
85 | ␉␉␉id = pci_config_read32(pci_addr, PCI_VENDOR_ID);␊ |
86 | ␉␉␉if (!id || id == 0xffffffff)␊ |
87 | ␉␉␉{␊ |
88 | ␉␉␉␉continue;␊ |
89 | ␉␉␉}␊ |
90 | ␉␉␉new = (pci_dt_t*)malloc(sizeof(pci_dt_t));␊ |
91 | if (!new) {␊ |
92 | continue;␊ |
93 | }␊ |
94 | ␉␉␉bzero(new, sizeof(pci_dt_t));␊ |
95 | ␉␉␉new->dev.addr␉= pci_addr;␊ |
96 | ␉␉␉new->vendor_id␉= id & 0xffff;␊ |
97 | ␉␉␉new->device_id␉= (id >> 16) & 0xffff;␊ |
98 | ␉␉␉new->subsys_id.subsys_id␉= pci_config_read32(pci_addr, PCI_SUBSYSTEM_VENDOR_ID);␊ |
99 | ␉␉␉new->class_id␉= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);␊ |
100 | ␉␉␉new->parent␉= start;␊ |
101 | ␉␉␉␊ |
102 | ␉␉␉header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);␊ |
103 | ␉␉␉switch (header_type & 0x7f)␊ |
104 | ␉␉␉{␊ |
105 | ␉␉␉␉case PCI_HEADER_TYPE_BRIDGE:␊ |
106 | ␉␉␉␉case PCI_HEADER_TYPE_CARDBUS:␊ |
107 | ␉␉␉␉␉secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS);␊ |
108 | ␉␉␉␉␉if (secondary_bus != 0)␊ |
109 | ␉␉␉␉␉{␊ |
110 | ␉␉␉␉␉␉scan_pci_bus(new, secondary_bus);␊ |
111 | ␉␉␉␉␉}␊ |
112 | ␉␉␉␉␉break;␊ |
113 | ␉␉␉␉default:␊ |
114 | ␉␉␉␉␉break;␊ |
115 | ␉␉␉}␊ |
116 | ␉␉␉*current = new;␊ |
117 | ␉␉␉current = &new->next;␊ |
118 | ␉␉␉␊ |
119 | ␉␉␉if ((func == 0) && ((header_type & 0x80) == 0))␊ |
120 | ␉␉␉{␊ |
121 | ␉␉␉␉break;␊ |
122 | ␉␉␉}␊ |
123 | ␉␉}␊ |
124 | ␉}␊ |
125 | }␊ |
126 | ␊ |
127 | void enable_pci_devs(void)␊ |
128 | {␊ |
129 | ␉uint16_t id;␊ |
130 | ␉uint32_t rcba, *fd;␊ |
131 | ␉␊ |
132 | ␉id = pci_config_read16(PCIADDR(0, 0x00, 0), 0x00);␊ |
133 | ␉/* make sure we're on Intel chipset */␊ |
134 | ␉if (id != 0x8086)␊ |
135 | ␉␉return;␊ |
136 | ␉rcba = pci_config_read32(PCIADDR(0, 0x1f, 0), 0xf0) & ~1;␊ |
137 | ␉fd = (uint32_t *)(rcba + 0x3418);␊ |
138 | ␉/* set SMBus Disable (SD) to 0 */␊ |
139 | ␉*fd &= ~0x8;␊ |
140 | ␉/* and all devices? */␊ |
141 | ␉//*fd = 0x1;␊ |
142 | }␊ |
143 | ␊ |
144 | ␊ |
145 | void build_pci_dt(void)␊ |
146 | {␊ |
147 | ␉dev_path = malloc(sizeof(char) * 256);␉// TODO: remove␊ |
148 | ␉␊ |
149 | ␉root_pci_dev = malloc(sizeof(pci_dt_t));␊ |
150 | ␊ |
151 | if (!dev_path || !root_pci_dev) {␊ |
152 | stop("Couldn't allocate memory for the pci root device\n");␊ |
153 | return ;␊ |
154 | }␊ |
155 | ␉bzero(root_pci_dev, sizeof(pci_dt_t));␊ |
156 | ␉enable_pci_devs();␊ |
157 | ␉scan_pci_bus(root_pci_dev, 0);␊ |
158 | #if DEBUG_PCI␊ |
159 | #ifndef OPTION_ROM␊ |
160 | ␉dump_pci_dt(root_pci_dev->children);␊ |
161 | ␉pause();␊ |
162 | #endif␊ |
163 | #endif␊ |
164 | }␊ |
165 | ␊ |
166 | #if 0␊ |
167 | char *get_pci_dev_path(pci_dt_t *pci_dt)␊ |
168 | {␊ |
169 | ␉char* buffer = malloc(sizeof(char) * 256);␊ |
170 | ␉␊ |
171 | if (!buffer) {␊ |
172 | return NULL;␊ |
173 | }␊ |
174 | ␊ |
175 | ␉pci_dt_t␉*current;␊ |
176 | ␉pci_dt_t␉*end;␊ |
177 | ␉char␉␉tmp[64];␊ |
178 | ␉␊ |
179 | ␉buffer[0] = 0;␉␊ |
180 | ␉end = root_pci_dev;␊ |
181 | ␉␊ |
182 | ␉int uid = getPciRootUID();␊ |
183 | ␉while (end != pci_dt)␊ |
184 | ␉{␊ |
185 | ␉␉current = pci_dt;␊ |
186 | ␉␉while (current->parent != end)␊ |
187 | ␉␉␉current = current->parent;␉␉␉␊ |
188 | ␉␉end = current;␊ |
189 | ␉␉if (current->parent == root_pci_dev)␊ |
190 | ␉␉{␊ |
191 | ␉␉␉snprintf(tmp, sizeof(tmp),"PciRoot(0x%x)/Pci(0x%x,0x%x)", uid,␊ |
192 | ␉␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
193 | ␉␉} ␊ |
194 | ␉␉else ␊ |
195 | ␉␉{␊ |
196 | ␉␉␉snprintf(tmp, sizeof(tmp) ,"/Pci(0x%x,0x%x)",␊ |
197 | ␉␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
198 | ␉␉}␊ |
199 | ␉␉snprintf(buffer, sizeof(char) * 256,"%s%s", buffer, tmp);␊ |
200 | ␉}␊ |
201 | ␉return buffer;␊ |
202 | }␊ |
203 | #endif␊ |
204 | ␊ |
205 | void setup_pci_devs(pci_dt_t *pci_dt)␊ |
206 | {␊ |
207 | ␉pci_dt_t *current = pci_dt;␊ |
208 | ␉␊ |
209 | ␉while (current)␊ |
210 | ␉{␉␉␊ |
211 | ␉␉execute_hook("PCIDevice", (void*)current, NULL, NULL, NULL, NULL, NULL);␊ |
212 | ␉␉␊ |
213 | ␉␉setup_pci_devs(current->children);␊ |
214 | ␉␉current = current->next;␊ |
215 | ␉}␊ |
216 | }␊ |
217 | ␊ |
218 | #ifndef OPTION_ROM␊ |
219 | void dump_pci_dt(pci_dt_t *pci_dt)␊ |
220 | {␊ |
221 | ␉pci_dt_t␉*current;␊ |
222 | ␉␊ |
223 | ␉current = pci_dt;␊ |
224 | ␉while (current) ␊ |
225 | ␉{␊ |
226 | ␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] \n", ␊ |
227 | ␉␉␉ current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊ |
228 | ␉␉␉ current->class_id, current->vendor_id, current->device_id);␊ |
229 | ␉␉dump_pci_dt(current->children);␊ |
230 | ␉␉current = current->next;␊ |
231 | ␉}␊ |
232 | }␊ |
233 | #endif␊ |
234 | ␊ |
235 | static int rootuid = 10; //value means function wasnt ran yet␊ |
236 | ␊ |
237 | /*␊ |
238 | * getPciRootUID: Copyright 2009 netkas␊ |
239 | */␊ |
240 | int getPciRootUID(void)␊ |
241 | {␊ |
242 | ␉const char *val;␊ |
243 | ␉int len;␊ |
244 | ␉␊ |
245 | ␉if (rootuid < 10) return rootuid;␊ |
246 | ␉rootuid = 0;␉/* default uid = 0 */␊ |
247 | ␉␊ |
248 | ␉if (getValueForKey(kPCIRootUID, &val, &len, DEFAULT_BOOT_CONFIG))␊ |
249 | ␉{␊ |
250 | ␉␉if (isdigit(val[0])) rootuid = val[0] - '0';␊ |
251 | ␉␉␊ |
252 | ␉␉if ( (rootuid >= 0) && (rootuid < 10) ) ␊ |
253 | ␉␉␉goto out;␊ |
254 | ␉␉else␊ |
255 | ␉␉␉rootuid = 0;␊ |
256 | ␉}␉␊ |
257 | ␉␊ |
258 | ␉/* PCEFI compatibility */␊ |
259 | ␉if (getValueForKey("-pci0", &val, &len, DEFAULT_BOOT_CONFIG))␊ |
260 | ␉{␊ |
261 | ␉␉rootuid = 0;␊ |
262 | ␉}␊ |
263 | ␉else if (getValueForKey("-pci1", &val, &len, DEFAULT_BOOT_CONFIG))␊ |
264 | ␉{␊ |
265 | ␉␉rootuid = 1;␊ |
266 | ␉}␊ |
267 | out:␊ |
268 | ␉verbose("Using PCI-Root-UID value: %d\n", rootuid);␊ |
269 | ␉return rootuid;␊ |
270 | } |