1 | /*␊ |
2 | * platform.h␊ |
3 | * AsereBLN: reworked and extended␊ |
4 | *␉valv: further additions␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
8 | #define __LIBSAIO_PLATFORM_H␊ |
9 | ␊ |
10 | #include "libsaio.h"␊ |
11 | ␊ |
12 | extern bool platformCPUFeature(uint32_t);␊ |
13 | extern void scan_platform(void);␊ |
14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
15 | ␊ |
16 | #define bit(n)␉␉␉(1UL << (n))␊ |
17 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
18 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
19 | ␊ |
20 | ␊ |
21 | /* CPUID index into cpuid_raw */␊ |
22 | #define CPUID_0␉␉␉␉0␊ |
23 | #define CPUID_1␉␉␉␉1␊ |
24 | #define CPUID_2␉␉␉␉2␊ |
25 | #define CPUID_3␉␉␉␉3␊ |
26 | #define CPUID_4␉␉␉␉4␊ |
27 | #define CPUID_80␉␉␉5␊ |
28 | #define CPUID_81␉␉␉6␊ |
29 | #define CPUID_MAX␉␉␉7␊ |
30 | ␊ |
31 | /* CPU Features */␊ |
32 | // NOTE: These are currently mapped to the actual bit in the cpuid value␊ |
33 | #define CPU_FEATURE_MMX␉␉␉bit(23)␉␉// MMX Instruction Set␊ |
34 | #define CPU_FEATURE_SSE␉␉␉bit(25)␉␉// SSE Instruction Set␊ |
35 | #define CPU_FEATURE_SSE2␉␉bit(26)␉␉// SSE2 Instruction Set␊ |
36 | #define CPU_FEATURE_SSE3␉␉bit(0)␉␉// SSE3 Instruction Set␊ |
37 | #define CPU_FEATURE_SSE41␉␉bit(19)␉␉// SSE41 Instruction Set␊ |
38 | #define CPU_FEATURE_SSE42␉␉bit(20)␉␉// SSE42 Instruction Set␊ |
39 | #define CPU_FEATURE_EM64T␉␉bit(29)␉␉// 64Bit Support␊ |
40 | #define CPU_FEATURE_HTT␉␉␉bit(28)␉␉// HyperThreading␊ |
41 | #define CPU_FEATURE_MSR␉␉␉bit(5)␉␉// MSR Support␊ |
42 | #define CPU_FEATURE_APIC␉␉bit(9)␉␉// On-chip APIC Hardware␊ |
43 | #define CPU_FEATURE_EST␉␉␉bit(7)␉␉// Enhanced Intel SpeedStep␊ |
44 | #define CPU_FEATURE_TM2␉␉␉bit(8)␉␉// Thermal Monitor 2␊ |
45 | #define CPU_FEATURE_TM1␉␉␉bit(29)␉␉// Thermal Monitor 1␊ |
46 | #define CPU_FEATURE_SSSE3␉␉bit(9)␉␉// Supplemental SSE3 Instruction Set␊ |
47 | #define CPU_FEATURE_xAPIC␉␉bit(21)␉␉// Extended APIC Mode␊ |
48 | #define CPU_FEATURE_ACPI␉␉bit(22)␉␉// Thermal Monitor and Software Controlled Clock␊ |
49 | #define CPU_FEATURE_LAHF␉␉bit(20)␉␉// LAHF/SAHF Instructions␊ |
50 | #define CPU_FEATURE_XD␉␉␉bit(20)␉␉// Execute Disable␊ |
51 | ␊ |
52 | // NOTE: Determine correct bit for below (28 is already in use)␊ |
53 | #define CPU_FEATURE_MOBILE␉␉bit(1)␉␉// Mobile CPU␊ |
54 | ␊ |
55 | ␊ |
56 | /* SMBIOS Memory Types */ ␊ |
57 | #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
58 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
59 | #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
60 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
61 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
62 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
63 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
64 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
65 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
66 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
67 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
68 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
69 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
70 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
71 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
72 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
73 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
74 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
75 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
76 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
77 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
78 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
79 | ␊ |
80 | /* Memory Configuration Types */ ␊ |
81 | #define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊ |
82 | #define SMB_MEM_CHANNEL_SINGLE␉␉1␊ |
83 | #define SMB_MEM_CHANNEL_DUAL␉␉2␊ |
84 | #define SMB_MEM_CHANNEL_TRIPLE␉␉3␊ |
85 | ␊ |
86 | /* Maximum number of ram slots */␊ |
87 | #define MAX_RAM_SLOTS␉␉␉8␊ |
88 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
89 | ␊ |
90 | /* Maximum number of SPD bytes */␊ |
91 | #define MAX_SPD_SIZE␉␉␉256␊ |
92 | ␊ |
93 | /* Size of SMBIOS UUID in bytes */␊ |
94 | #define UUID_LEN␉␉␉16␊ |
95 | ␊ |
96 | typedef struct _RamSlotInfo_t {␊ |
97 | uint32_t␉␉ModuleSize;␉␉␉␉␉␉// Size of Module in MB␊ |
98 | uint32_t␉␉Frequency; // in Mhz␊ |
99 | const char*␉␉Vendor;␊ |
100 | const char*␉␉PartNo;␊ |
101 | const char*␉␉SerialNo;␊ |
102 | char*␉␉␉spd;␉␉␉␉␉␉␉// SPD Dump␊ |
103 | bool␉␉␉InUse;␊ |
104 | uint8_t␉␉␉Type;␊ |
105 | uint8_t␉␉␉BankConnections; // table type 6, see (3.3.7)␊ |
106 | uint8_t␉␉␉BankConnCnt;␊ |
107 | ␊ |
108 | } RamSlotInfo_t;␊ |
109 | ␊ |
110 | typedef struct _PlatformInfo_t {␊ |
111 | ␉struct CPU {␊ |
112 | ␉␉uint32_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
113 | ␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊ |
114 | ␉␉uint32_t␉␉Signature;␉␉␉␉// Signature␊ |
115 | ␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊ |
116 | ␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊ |
117 | ␉␉uint32_t␉␉Type;␉␉␉␉␉// Processor Type␊ |
118 | ␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊ |
119 | ␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊ |
120 | ␉␉uint32_t␉␉ExtFamily;␉␉␉␉// Extended Family␊ |
121 | ␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊ |
122 | ␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊ |
123 | ␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Max Halving ID␊ |
124 | ␉␉uint8_t␉␉␉CurrDiv;␉␉␉␉// Current Halving ID␊ |
125 | ␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊ |
126 | ␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊ |
127 | ␉␉uint64_t␉␉FSBIFrequency;␉␉␉// FSB Frequency Hz (initial)␊ |
128 | ␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊ |
129 | ␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊ |
130 | ␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊ |
131 | ␉␉uint8_t␉␉␉Tone;␉␉␉␉␉// Turbo Ratio limit (1 core)␊ |
132 | ␉␉uint8_t␉␉␉Ttwo;␉␉␉␉␉// Turbo Ratio limit (2 cores)␊ |
133 | ␉␉uint8_t␉␉␉Tthr;␉␉␉␉␉// Turbo Ratio limit (3 cores)␊ |
134 | ␉␉uint8_t␉␉␉Tfor;␉␉␉␉␉// Turbo Ratio limit (4 cores)␊ |
135 | ␉␉bool␉␉␉ISerie;␉␉␉␉␉// Intel's Core-i model␊ |
136 | ␉␉bool␉␉␉Turbo;␉␉␉␉␉// Intel's Turbo Boost support␊ |
137 | ␉␉uint8_t␉␉␉SLFM;␉␉␉␉␉// Dynamic FSB␊ |
138 | ␉␉uint8_t␉␉␉EST;␉␉␉␉␉// Enhanced SpeedStep␊ |
139 | ␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊ |
140 | ␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
141 | ␉} CPU;␊ |
142 | ␊ |
143 | ␉struct RAM {␊ |
144 | ␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊ |
145 | ␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊ |
146 | ␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
147 | ␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊ |
148 | ␉␉uint8_t␉␉␉TRP;␊ |
149 | ␉␉uint8_t␉␉␉RAS;␊ |
150 | ␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊ |
151 | ␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊ |
152 | ␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
153 | ␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊ |
154 | ␉} RAM;␊ |
155 | ␊ |
156 | ␉struct DMI {␊ |
157 | ␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots polulated by SMBIOS␊ |
158 | ␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊ |
159 | ␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊ |
160 | ␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
161 | ␉} DMI;␊ |
162 | ␊ |
163 | ␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊ |
164 | ␊ |
165 | } PlatformInfo_t;␊ |
166 | ␊ |
167 | extern PlatformInfo_t Platform;␊ |
168 | ␊ |
169 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
170 | |