1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #ifndef __LIBSAIO_CPU_H␊ |
7 | #define __LIBSAIO_CPU_H␊ |
8 | ␊ |
9 | //#include "libsaio.h"␊ |
10 | ␊ |
11 | extern void scan_cpu(PlatformInfo_t *);␊ |
12 | ␊ |
13 | #define bit(n)␉␉␉(1ULL << (n))␊ |
14 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
15 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
16 | ␊ |
17 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
18 | ␊ |
19 | #define MSR_CORE_THREAD_COUNT␉0x35␉// Undocumented. Nehalem and newer only ␊ |
20 | #define MSR_FLEX_RATIO␉␉␉0x194␉// Undocumented. ␊ |
21 | #define MSR_IA32_EXT_CONFIG␉␉0xEE␉// Undocumented. Core Solo and Core Duo only␊ |
22 | #define MSR_PKG_CST_CONFIG_CTL␉0xE2␊ |
23 | #define␉MSR_IA32_PERF_STATUS␉0x198␊ |
24 | #define MSR_IA32_PERF_CONTROL␉0x199␊ |
25 | #define MSR_IA32_PLATFORM_ID␉0x17␊ |
26 | #define␉MSR_PLATFORM_INFO␉␉0xCE␊ |
27 | #define MSR_TURBO_RATIO_LIMIT␉0x1AD␊ |
28 | ␊ |
29 | ␊ |
30 | #define K8_FIDVID_STATUS␉␉0xC0010042␊ |
31 | #define K10_COFVID_STATUS␉␉0xC0010071␊ |
32 | ␊ |
33 | #define MSR_AMD_MPERF 0x000000E7␊ |
34 | #define MSR_AMD_APERF 0x000000E8␊ |
35 | ␊ |
36 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
37 | ␊ |
38 | // DFE: This constant comes from older xnu:␊ |
39 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
40 | ␊ |
41 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
42 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
43 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
44 | ␊ |
45 | ␊ |
46 | static inline uint64_t rdtsc64(void)␊ |
47 | {␊ |
48 | ␉uint64_t ret;␊ |
49 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
50 | ␉return ret;␊ |
51 | }␊ |
52 | ␊ |
53 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
54 | {␊ |
55 | uint64_t ret;␊ |
56 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
57 | return ret;␊ |
58 | }␊ |
59 | ␊ |
60 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
61 | {␊ |
62 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
63 | }␊ |
64 | ␊ |
65 | static inline void intel_waitforsts(void) {␊ |
66 | ␉uint32_t inline_timeout = 100000;␊ |
67 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
68 | }␊ |
69 | ␊ |
70 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
71 | {␊ |
72 | ␉asm volatile ("cpuid"␊ |
73 | ␉␉␉␉ : "=a" (data[0]),␊ |
74 | ␉␉␉␉ "=b" (data[1]),␊ |
75 | ␉␉␉␉ "=c" (data[2]),␊ |
76 | ␉␉␉␉ "=d" (data[3])␊ |
77 | ␉␉␉␉ : "a" (selector));␊ |
78 | }␊ |
79 | ␊ |
80 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
81 | {␊ |
82 | ␉asm volatile ("cpuid"␊ |
83 | ␉␉␉␉ : "=a" (data[0]),␊ |
84 | ␉␉␉␉ "=b" (data[1]),␊ |
85 | ␉␉␉␉ "=c" (data[2]),␊ |
86 | ␉␉␉␉ "=d" (data[3])␊ |
87 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
88 | }␊ |
89 | ␊ |
90 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
91 | ␊ |
92 | /*␊ |
93 | * Enable or disable timer 2.␊ |
94 | * Port 0x61 controls timer 2:␊ |
95 | * bit 0 gates the clock,␊ |
96 | * bit 1 gates output to speaker.␊ |
97 | */␊ |
98 | static inline void enable_PIT2(void)␊ |
99 | {␊ |
100 | /* Enable gate, disable speaker */␊ |
101 | __asm__ volatile(␊ |
102 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
103 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
104 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
105 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
106 | ␉␉␉␉␉ : : : "%al" );␊ |
107 | }␊ |
108 | ␊ |
109 | static inline void disable_PIT2(void)␊ |
110 | {␊ |
111 | /* Disable gate and output to speaker */␊ |
112 | __asm__ volatile(␊ |
113 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
114 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
115 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
116 | ␉␉␉␉␉ : : : "%al" );␊ |
117 | }␊ |
118 | ␊ |
119 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
120 | // roughly based on Linux code␊ |
121 | ␊ |
122 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
123 | In mode 0, the counter will initially set its gate low when the␊ |
124 | timer expires. For this to be useful, you ought to set it high␊ |
125 | before calling this function. The enable_PIT2 function does this.␊ |
126 | */␊ |
127 | static inline void set_PIT2_mode0(uint16_t value)␊ |
128 | {␊ |
129 | __asm__ volatile(␊ |
130 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
131 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
132 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
133 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
134 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
135 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
136 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
137 | }␊ |
138 | ␊ |
139 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
140 | static inline unsigned long poll_PIT2_gate(void)␊ |
141 | {␊ |
142 | unsigned long count = 0;␊ |
143 | unsigned char nmi_sc_val;␊ |
144 | do {␊ |
145 | ++count;␊ |
146 | __asm__ volatile(␊ |
147 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
148 | ␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
149 | } while( (nmi_sc_val & 0x20) == 0);␊ |
150 | return count;␊ |
151 | }␊ |
152 | ␊ |
153 | #endif /* !__LIBSAIO_CPU_H */␊ |
154 | |