1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | #include "cpu.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "boot.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␉␉msglog(x)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * timeRDTSC()␊ |
24 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
25 | * It pauses until the value is latched in the counter␊ |
26 | * and then reads the time stamp counter to return to the caller.␊ |
27 | */␊ |
28 | uint64_t timeRDTSC(void)␊ |
29 | {␊ |
30 | ␉int␉␉attempts = 0;␊ |
31 | ␉uint64_t latchTime;␊ |
32 | ␉uint64_t␉saveTime,intermediate;␊ |
33 | ␉unsigned int timerValue, lastValue;␊ |
34 | ␉//boolean_t␉int_enabled;␊ |
35 | ␉/*␊ |
36 | ␉ * Table of correction factors to account for␊ |
37 | ␉ *␉ - timer counter quantization errors, and␊ |
38 | ␉ *␉ - undercounts 0..5␊ |
39 | ␉ */␊ |
40 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
41 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
42 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
43 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
44 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
45 | ␉uint64_t␉scale[6] = {␊ |
46 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
47 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
48 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
49 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
50 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
51 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
52 | ␉};␊ |
53 | ␊ |
54 | //int_enabled = ml_set_interrupts_enabled(FALSE);␊ |
55 | ␊ |
56 | restart:␊ |
57 | ␉if (attempts >= 9) // increase to up to 9 attempts.␊ |
58 | ␉{␊ |
59 | ␉ // This will flash-reboot. TODO: Use tscPanic instead.␊ |
60 | ␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
61 | ␉}␊ |
62 | ␉attempts++;␊ |
63 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
64 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
65 | ␉latchTime = rdtsc64();␉// get the time stamp to time ␊ |
66 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
67 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
68 | ␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
69 | ␉get_PIT2(&lastValue);␊ |
70 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
71 | ␉do {␊ |
72 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
73 | ␉␉if (timerValue > lastValue)␊ |
74 | ␉␉{␊ |
75 | ␉␉␉// Timer wrapped␊ |
76 | ␉␉␉set_PIT2(0);␊ |
77 | ␉␉␉disable_PIT2();␊ |
78 | ␉␉␉goto restart;␊ |
79 | ␉␉}␊ |
80 | ␉␉lastValue = timerValue;␊ |
81 | ␉} while (timerValue > 5);␊ |
82 | ␉printf("timerValue␉ %d\n",timerValue);␊ |
83 | ␉printf("intermediate 0x%016llx\n",intermediate);␊ |
84 | ␉printf("saveTime␉ 0x%016llx\n",saveTime);␊ |
85 | ␊ |
86 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
87 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
88 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
89 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
90 | ␊ |
91 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
92 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
93 | ␉␊ |
94 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
95 | ␉return intermediate;␊ |
96 | }␊ |
97 | ␊ |
98 | /*␊ |
99 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
100 | */␊ |
101 | static uint64_t measure_tsc_frequency(void)␊ |
102 | {␊ |
103 | ␉uint64_t tscStart;␊ |
104 | ␉uint64_t tscEnd;␊ |
105 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
106 | ␉unsigned long pollCount;␊ |
107 | ␉uint64_t retval = 0;␊ |
108 | ␉int i;␊ |
109 | ␉␊ |
110 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
111 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
112 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
113 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
114 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
115 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
116 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
117 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
118 | ␉ */␊ |
119 | ␉for(i = 0; i < 10; ++i)␊ |
120 | ␉{␊ |
121 | ␉␉enable_PIT2();␊ |
122 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
123 | ␉␉tscStart = rdtsc64();␊ |
124 | ␉␉pollCount = poll_PIT2_gate();␊ |
125 | ␉␉tscEnd = rdtsc64();␊ |
126 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
127 | ␉␉if (pollCount <= 1)␊ |
128 | ␉␉{␊ |
129 | ␉␉␉continue;␊ |
130 | ␉␉}␊ |
131 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
132 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
133 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
134 | ␉␉ */␊ |
135 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
136 | ␉␉{␊ |
137 | ␉␉␉continue;␊ |
138 | ␉␉}␊ |
139 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
140 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
141 | ␉␉{␊ |
142 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
143 | ␉␉}␊ |
144 | ␉}␊ |
145 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
146 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
147 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
148 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
149 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
150 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
151 | ␉ */␊ |
152 | ␊ |
153 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
154 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
155 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
156 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
157 | ␉ */␊ |
158 | ␉if (tscDelta > (1ULL<<32))␊ |
159 | ␉{␊ |
160 | ␉␉retval = 0;␊ |
161 | ␉}␊ |
162 | ␉else␊ |
163 | ␉{␊ |
164 | ␉␉retval = tscDelta * 1000 / 30;␊ |
165 | ␉}␊ |
166 | ␉disable_PIT2();␊ |
167 | ␉return retval;␊ |
168 | }␊ |
169 | ␊ |
170 | /*␊ |
171 | * Original comment/code:␊ |
172 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
173 | *␊ |
174 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
175 | * (just a naming change, mperf --> aperf )␊ |
176 | */␊ |
177 | static uint64_t measure_aperf_frequency(void)␊ |
178 | {␊ |
179 | ␉uint64_t aperfStart;␊ |
180 | ␉uint64_t aperfEnd;␊ |
181 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
182 | ␉unsigned long pollCount;␊ |
183 | ␉uint64_t retval = 0;␊ |
184 | ␉int i;␊ |
185 | ␉␊ |
186 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
187 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
188 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
189 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
190 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
191 | ␉ * expire.␊ |
192 | ␉ */␊ |
193 | ␉for(i = 0; i < 10; ++i)␊ |
194 | ␉{␊ |
195 | ␉␉enable_PIT2();␊ |
196 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
197 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
198 | ␉␉pollCount = poll_PIT2_gate();␊ |
199 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
200 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
201 | ␉␉if (pollCount <= 1)␊ |
202 | ␉␉{␊ |
203 | ␉␉␉continue;␊ |
204 | ␉␉}␊ |
205 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
206 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
207 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
208 | ␉␉ */␊ |
209 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
210 | ␉␉{␊ |
211 | ␉␉␉continue;␊ |
212 | ␉␉}␊ |
213 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
214 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
215 | ␉␉{␊ |
216 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
217 | ␉␉}␊ |
218 | ␉}␊ |
219 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
220 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
221 | ␉ */␊ |
222 | ␉␊ |
223 | ␉if (aperfDelta > (1ULL<<32))␊ |
224 | ␉{␊ |
225 | ␉␉retval = 0;␊ |
226 | ␉}␊ |
227 | ␉else␊ |
228 | ␉{␊ |
229 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
230 | ␉}␊ |
231 | ␉disable_PIT2();␊ |
232 | ␉return retval;␊ |
233 | }␊ |
234 | ␊ |
235 | /*␊ |
236 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
237 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
238 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
239 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
240 | * - fsbFrequency = tscFrequency / multi␊ |
241 | * - cpuFrequency = fsbFrequency * multi␊ |
242 | */␊ |
243 | void scan_cpu(PlatformInfo_t *p)␊ |
244 | {␊ |
245 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊ |
246 | ␉uint64_t␉msr, flex_ratio;␊ |
247 | ␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊ |
248 | ␉const char␉*newratio;␊ |
249 | ␉int␉␉len, myfsb;␊ |
250 | ␉uint8_t␉␉bus_ratio_min;␊ |
251 | ␉uint32_t␉max_ratio, min_ratio;␊ |
252 | ␊ |
253 | ␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊ |
254 | ␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊ |
255 | ␊ |
256 | ␉/* get cpuid values */␊ |
257 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
258 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
259 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊ |
260 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊ |
261 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
262 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
263 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊ |
264 | ␉{␊ |
265 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
266 | ␉}␊ |
267 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊ |
268 | ␉{␊ |
269 | ␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
270 | ␉}␊ |
271 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
272 | ␉{␊ |
273 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
274 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
275 | ␉}␊ |
276 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
277 | ␉{␊ |
278 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
279 | ␉}␊ |
280 | ␊ |
281 | #if DEBUG_CPU␊ |
282 | ␉{␊ |
283 | ␉␉int␉␉i;␊ |
284 | ␉␉printf("CPUID Raw Values:\n");␊ |
285 | ␉␉for (i=0; i<CPUID_MAX; i++)␊ |
286 | ␉␉{␊ |
287 | ␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
288 | ␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
289 | ␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
290 | ␉␉}␊ |
291 | ␉}␊ |
292 | #endif␊ |
293 | ␊ |
294 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
295 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
296 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
297 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
298 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
299 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
300 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
301 | ␊ |
302 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
303 | ␊ |
304 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊ |
305 | ␉␉p->CPU.Family == 0x06 &&␊ |
306 | ␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊ |
307 | ␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
308 | ␉␉)␊ |
309 | ␉{␊ |
310 | ␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊ |
311 | ␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊ |
312 | ␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊ |
313 | ␉}␊ |
314 | ␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊ |
315 | ␉{␊ |
316 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
317 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
318 | ␉}␊ |
319 | ␉else␊ |
320 | ␉{␊ |
321 | ␉␉// Use previous method for Cores and Threads␊ |
322 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
323 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
324 | ␉}␊ |
325 | ␊ |
326 | ␉/* get brand string (if supported) */␊ |
327 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
328 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
329 | ␉{␊ |
330 | ␉␉uint32_t␉reg[4];␊ |
331 | ␉␉char␉␉str[128], *s;␊ |
332 | ␉␉/*␊ |
333 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
334 | ␉␉ * be NULL terminated.␊ |
335 | ␉␉ */␊ |
336 | ␉␉do_cpuid(0x80000002, reg);␊ |
337 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
338 | ␉␉do_cpuid(0x80000003, reg);␊ |
339 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
340 | ␉␉do_cpuid(0x80000004, reg);␊ |
341 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
342 | ␉␉for (s = str; *s != '\0'; s++)␊ |
343 | ␉␉{␊ |
344 | ␉␉␉if (*s != ' ')␊ |
345 | ␉␉␉{␊ |
346 | ␉␉␉␉break;␊ |
347 | ␉␉␉}␊ |
348 | ␉␉}␊ |
349 | ␉␉␊ |
350 | ␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊ |
351 | ␉␉␊ |
352 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
353 | ␉␉{␊ |
354 | ␉␉␉/*␊ |
355 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
356 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
357 | ␉␉␉ */␊ |
358 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
359 | ␉␉}␊ |
360 | ␉}␊ |
361 | ␉␊ |
362 | ␉/* setup features */␊ |
363 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
364 | ␉{␊ |
365 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
366 | ␉}␊ |
367 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
368 | ␉{␊ |
369 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
370 | ␉}␊ |
371 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
372 | ␉{␊ |
373 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
374 | ␉}␊ |
375 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
376 | ␉{␊ |
377 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
378 | ␉}␊ |
379 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
380 | ␉{␊ |
381 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
382 | ␉}␊ |
383 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
384 | ␉{␊ |
385 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
386 | ␉}␊ |
387 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
388 | ␉{␊ |
389 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
390 | ␉}␊ |
391 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
392 | ␉{␊ |
393 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
394 | ␉}␊ |
395 | ␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
396 | ␉if (p->CPU.NoThreads > p->CPU.NoCores)␊ |
397 | ␉{␊ |
398 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
399 | ␉}␊ |
400 | ␊ |
401 | ␉tscFrequency = measure_tsc_frequency();␊ |
402 | ␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊ |
403 | ␉/* if usual method failed */␊ |
404 | ␉if ( tscFrequency < 1000 )//TEST␊ |
405 | ␉{␊ |
406 | ␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊ |
407 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
408 | ␉}␊ |
409 | ␉else␊ |
410 | ␉{␊ |
411 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊ |
412 | ␉}␊ |
413 | ␉fsbFrequency = 0;␊ |
414 | ␉cpuFrequency = 0;␊ |
415 | ␊ |
416 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊ |
417 | ␉{␊ |
418 | ␉␉int intelCPU = p->CPU.Model;␊ |
419 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊ |
420 | ␉␉{␊ |
421 | ␉␉␉/* Nehalem CPU model */␊ |
422 | ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊ |
423 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉||␊ |
424 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉||␊ |
425 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_CLARKDALE␉||␊ |
426 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊ |
427 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊ |
428 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊ |
429 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊ |
430 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN␉||␊ |
431 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE␉))␊ |
432 | ␉␉␉{␊ |
433 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
434 | ␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
435 | ␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊ |
436 | ␉␉␉␉bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊ |
437 | ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
438 | ␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
439 | ␉␉␉␉if (bitfield(msr, 16, 16))␊ |
440 | ␉␉␉␉{␊ |
441 | ␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊ |
442 | ␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
443 | ␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
444 | ␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
445 | ␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
446 | ␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
447 | ␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
448 | ␉␉␉␉␉ is inadvertently set to 0.␊ |
449 | ␉␉␉␉␉ */␊ |
450 | ␉␉␉␉␉if (flex_ratio == 0)␊ |
451 | ␉␉␉␉␉{␊ |
452 | ␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
453 | ␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
454 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
455 | ␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
456 | ␉␉␉␉␉}␊ |
457 | ␉␉␉␉␉else␊ |
458 | ␉␉␉␉␉{␊ |
459 | ␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
460 | ␉␉␉␉␉␉{␊ |
461 | ␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
462 | ␉␉␉␉␉␉}␊ |
463 | ␉␉␉␉␉}␊ |
464 | ␉␉␉␉}␊ |
465 | ␊ |
466 | ␉␉␉␉if (bus_ratio_max)␊ |
467 | ␉␉␉␉{␊ |
468 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
469 | ␉␉␉␉}␊ |
470 | ␉␉␉␉//valv: Turbo Ratio Limit␊ |
471 | ␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
472 | ␉␉␉␉{␊ |
473 | ␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
474 | ␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
475 | ␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
476 | ␉␉␉␉}␊ |
477 | ␉␉␉␉else␊ |
478 | ␉␉␉␉{␊ |
479 | ␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
480 | ␉␉␉␉}␊ |
481 | ␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
482 | ␉␉␉␉{␊ |
483 | ␉␉␉␉␉max_ratio = atoi(newratio);␊ |
484 | ␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
485 | ␉␉␉␉␉if (len >= 3)␊ |
486 | ␉␉␉␉␉{␊ |
487 | ␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
488 | ␉␉␉␉␉}␊ |
489 | ␊ |
490 | ␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
491 | ␊ |
492 | ␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
493 | ␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
494 | ␉␉␉␉␉{␊ |
495 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
496 | ␉␉␉␉␉␉if (len >= 3)␊ |
497 | ␉␉␉␉␉␉{␊ |
498 | ␉␉␉␉␉␉␉maxdiv = 1;␊ |
499 | ␉␉␉␉␉␉}␊ |
500 | ␉␉␉␉␉␉else␊ |
501 | ␉␉␉␉␉␉{␊ |
502 | ␉␉␉␉␉␉␉maxdiv = 0;␊ |
503 | ␉␉␉␉␉␉}␊ |
504 | ␉␉␉␉␉}␊ |
505 | ␉␉␉␉␉else␊ |
506 | ␉␉␉␉␉{␊ |
507 | ␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
508 | ␉␉␉␉␉}␊ |
509 | ␉␉␉␉}␊ |
510 | ␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
511 | ␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
512 | ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
513 | ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
514 | ␊ |
515 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
516 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊ |
517 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
518 | ␉␉␉}␊ |
519 | ␉␉␉else␊ |
520 | ␉␉␉{␊ |
521 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
522 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
523 | ␉␉␉␉currcoef = bitfield(msr, 12, 8);␊ |
524 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
525 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
526 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
527 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
528 | ␊ |
529 | ␉␉␉␉// This will always be model >= 3␊ |
530 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
531 | ␉␉␉␉{␊ |
532 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
533 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
534 | ␉␉␉␉}␊ |
535 | ␉␉␉␉else␊ |
536 | ␉␉␉␉{␊ |
537 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
538 | ␉␉␉␉␉/* XXX */␊ |
539 | ␉␉␉␉␉maxcoef = currcoef;␊ |
540 | ␉␉␉␉}␊ |
541 | ␊ |
542 | ␉␉␉␉if (maxcoef)␊ |
543 | ␉␉␉␉{␊ |
544 | ␉␉␉␉␉if (maxdiv)␊ |
545 | ␉␉␉␉␉{␊ |
546 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
547 | ␉␉␉␉␉}␊ |
548 | ␉␉␉␉␉else␊ |
549 | ␉␉␉␉␉{␊ |
550 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
551 | ␉␉␉␉␉}␊ |
552 | ␉␉␉␉␉if (currdiv)␊ |
553 | ␉␉␉␉␉{␊ |
554 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
555 | ␉␉␉␉␉}␊ |
556 | ␉␉␉␉␉else␊ |
557 | ␉␉␉␉␉{␊ |
558 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
559 | ␉␉␉␉␉}␊ |
560 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
561 | ␉␉␉␉}␊ |
562 | ␉␉␉}␊ |
563 | ␉␉}␊ |
564 | ␉␉/* Mobile CPU */␊ |
565 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
566 | ␉␉{␊ |
567 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
568 | ␉␉}␊ |
569 | ␉}␊ |
570 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
571 | ␉{␊ |
572 | ␉␉switch(p->CPU.ExtFamily)␊ |
573 | ␉␉{␊ |
574 | ␉␉␉case 0x00: /* K8 */␊ |
575 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
576 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
577 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
578 | ␉␉␉␉break;␊ |
579 | ␊ |
580 | ␉␉␉case 0x01: /* K10 */␊ |
581 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
582 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
583 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
584 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
585 | ␉␉␉␉{␊ |
586 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
587 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
588 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
589 | ␉␉␉␉}␊ |
590 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
591 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
592 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
593 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
594 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
595 | ␊ |
596 | ␉␉␉␉break;␊ |
597 | ␊ |
598 | ␉␉␉case 0x05: /* K14 */␊ |
599 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
600 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
601 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
602 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
603 | ␊ |
604 | ␉␉␉␉break;␊ |
605 | ␊ |
606 | ␉␉␉case 0x02: /* K11 */␊ |
607 | ␉␉␉␉// not implimented␊ |
608 | ␉␉␉␉break;␊ |
609 | ␉␉}␊ |
610 | ␊ |
611 | ␉␉if (maxcoef)␊ |
612 | ␉␉{␊ |
613 | ␉␉␉if (currdiv)␊ |
614 | ␉␉␉{␊ |
615 | ␉␉␉␉if (!currcoef)␊ |
616 | ␉␉␉␉{␊ |
617 | ␉␉␉␉␉currcoef = maxcoef;␊ |
618 | ␉␉␉␉}␊ |
619 | ␊ |
620 | ␉␉␉␉if (!cpuFrequency)␊ |
621 | ␉␉␉␉{␊ |
622 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
623 | ␉␉␉␉}␊ |
624 | ␉␉␉␉else␊ |
625 | ␉␉␉␉{␊ |
626 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
627 | ␉␉␉␉}␊ |
628 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
629 | ␉␉␉}␊ |
630 | ␉␉␉else␊ |
631 | ␉␉␉{␊ |
632 | ␉␉␉␉if (!cpuFrequency)␊ |
633 | ␉␉␉␉{␊ |
634 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
635 | ␉␉␉␉}␊ |
636 | ␉␉␉␉else ␊ |
637 | ␉␉␉␉{␊ |
638 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
639 | ␉␉␉␉}␊ |
640 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
641 | ␉␉␉}␊ |
642 | ␉␉}␊ |
643 | ␉␉else if (currcoef)␊ |
644 | ␉␉{␊ |
645 | ␉␉␉if (currdiv)␊ |
646 | ␉␉␉{␊ |
647 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
648 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
649 | ␉␉␉}␊ |
650 | ␉␉␉else␊ |
651 | ␉␉␉{␊ |
652 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
653 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
654 | ␉␉␉}␊ |
655 | ␉␉}␊ |
656 | ␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊ |
657 | ␉}␊ |
658 | ␉␊ |
659 | #if 0␊ |
660 | ␉if (!fsbFrequency)␊ |
661 | ␉{␊ |
662 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
663 | ␉␉cpuFrequency = tscFrequency;␊ |
664 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
665 | ␉}␊ |
666 | ␊ |
667 | ␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
668 | ␊ |
669 | #endif␊ |
670 | ␊ |
671 | ␉p->CPU.MaxCoef = maxcoef;␊ |
672 | ␉p->CPU.MaxDiv = maxdiv;␊ |
673 | ␉p->CPU.CurrCoef = currcoef;␊ |
674 | ␉p->CPU.CurrDiv = currdiv;␊ |
675 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
676 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
677 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
678 | ␊ |
679 | ␉// keep formatted with spaces instead of tabs␊ |
680 | ␉DBG("\n---------------------------------------------\n");␊ |
681 | ␉DBG("CPU: Brand String:\t\t\t\t %s\n", p->CPU.BrandString);␊ |
682 | ␉DBG("CPU: Vendor/Family/ExtFamily:\t 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊ |
683 | ␉DBG("CPU: Model/ExtModel/Stepping:\t 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊ |
684 | ␉DBG("CPU: MaxCoef/CurrCoef:\t\t\t 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊ |
685 | ␉DBG("CPU: MaxDiv/CurrDiv:\t\t\t 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊ |
686 | ␉DBG("CPU: TSCFreq:\t\t\t\t %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
687 | ␉DBG("CPU: FSBFreq:\t\t\t\t\t %dMHz\n", (p->CPU.FSBFrequency + 500000) / 1000000);␊ |
688 | ␉DBG("CPU: CPUFreq:\t\t\t\t %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
689 | ␉DBG("CPU: Number of CPU Cores:\t\t %d\n", p->CPU.NoCores);␊ |
690 | ␉DBG("CPU: Number of CPU Threads:\t %d\n", p->CPU.NoThreads);␊ |
691 | ␉DBG("CPU: Features:\t\t\t\t\t 0x%08x\n", p->CPU.Features);␊ |
692 | ␉DBG("---------------------------------------------\n");␊ |
693 | #if DEBUG_CPU␊ |
694 | ␉pause();␊ |
695 | #endif␊ |
696 | }␊ |
697 | |