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Source at commit 2054 created 11 years 10 months ago. By zef, Fixed source indent. | |
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1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
25 | ␉return true;␊ |
26 | }␊ |
27 | ␊ |
28 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
29 | {␊ |
30 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
31 | ␉return true;␊ |
32 | }␊ |
33 | ␊ |
34 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
35 | {␊ |
36 | ␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊ |
37 | ␉{␉␉␊ |
38 | ␉␉switch (Platform.CPU.Family) ␊ |
39 | ␉␉{␊ |
40 | ␉␉␉case 0x06:␊ |
41 | ␉␉␉{␊ |
42 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
43 | ␉␉␉␉{␊ |
44 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
45 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
46 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
47 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
48 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
49 | ␉␉␉␉␉␉return false;␊ |
50 | ␊ |
51 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
52 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
53 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
54 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
55 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
56 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
57 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
58 | ␉␉␉␉␉{␊ |
59 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
60 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
61 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
62 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
63 | ␉␉␉␉␉␉int i;␊ |
64 | ␉␉␉␉␉␉␊ |
65 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
66 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
67 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
68 | ␉␉␉␉␉␉{␊ |
69 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
70 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
71 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
72 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
73 | ␉␉␉␉␉␉␉␊ |
74 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
75 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
76 | ␉␉␉␉␉␉}␊ |
77 | ␉␉␉␉␉␉␊ |
78 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
79 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
80 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
81 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
82 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
83 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
84 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
85 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
86 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
87 | ␉␉␉␉␉␉return true;␊ |
88 | ␉␉␉␉␉}␊ |
89 | ␉␉␉␉}␊ |
90 | ␉␉␉}␊ |
91 | ␉␉}␊ |
92 | ␉}␊ |
93 | ␉return false;␊ |
94 | }␊ |
95 | ␊ |
96 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
97 | {␊ |
98 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
99 | ␉{␊ |
100 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
101 | ␉}␊ |
102 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
103 | ␉{␊ |
104 | ␉␉return 0x0201;␉// Core Solo␊ |
105 | ␉};␊ |
106 | ␉␊ |
107 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
108 | }␊ |
109 | ␊ |
110 | bool getSMBOemProcessorType(returnType *value)␊ |
111 | {␊ |
112 | ␉static bool done = false;␉␉␊ |
113 | ␉␉␊ |
114 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
115 | ␊ |
116 | ␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊ |
117 | ␉{␊ |
118 | ␉␉if (!done)␊ |
119 | ␉␉{␊ |
120 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
121 | ␉␉␉done = true;␊ |
122 | ␉␉}␊ |
123 | ␉␉␊ |
124 | ␉␉switch (Platform.CPU.Family) ␊ |
125 | ␉␉{␊ |
126 | ␉␉␉case 0x06:␊ |
127 | ␉␉␉{␊ |
128 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
129 | ␉␉␉␉{␊ |
130 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊ |
131 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
132 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
133 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
134 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
135 | ␉␉␉␉␉␉return true;␊ |
136 | ␊ |
137 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
138 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
139 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊ |
140 | ␉␉␉␉␉␉else␊ |
141 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
142 | ␉␉␉␉␉␉return true;␊ |
143 | ␊ |
144 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
145 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
146 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
147 | ␉␉␉␉␉␉else␊ |
148 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
149 | ␉␉␉␉␉␉return true;␊ |
150 | ␊ |
151 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
152 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
153 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
154 | ␉␉␉␉␉␉else␊ |
155 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
156 | ␉␉␉␉␉␉return true;␊ |
157 | ␊ |
158 | ␉␉␉␉␉case CPU_MODEL_SANDY:␉␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
159 | case CPU_MODEL_SANDY_XEON:␉␉␉// Intel Xeon E3␊ |
160 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
161 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
162 | ␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊ |
163 | ␉␉␉␉␉␉else␊ |
164 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
165 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊ |
166 | ␉␉␉␉␉␉␉else␊ |
167 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
168 | ␉␉␉␉␉␉return true;␊ |
169 | ␊ |
170 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
171 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
172 | ␉␉␉␉␉␉value->word = 0x0501;␉␉␉␉// Core i7␊ |
173 | ␉␉␉␉␉␉return true;␊ |
174 | ␉␉␉␉}␊ |
175 | ␉␉␉}␊ |
176 | ␉␉}␊ |
177 | ␉}␊ |
178 | ␉␊ |
179 | ␉return false;␊ |
180 | }␊ |
181 | ␊ |
182 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
183 | {␊ |
184 | ␉static int idx = -1;␊ |
185 | ␉int␉map;␊ |
186 | ␊ |
187 | ␉idx++;␊ |
188 | ␉if (idx < MAX_RAM_SLOTS)␊ |
189 | ␉{␊ |
190 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
191 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
192 | ␉␉{␊ |
193 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
194 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
195 | ␉␉␉return true;␊ |
196 | ␉␉}␊ |
197 | ␉}␊ |
198 | ␉␊ |
199 | ␉return false;␊ |
200 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
201 | //␉return true;␊ |
202 | }␊ |
203 | ␊ |
204 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
205 | {␊ |
206 | ␉static int idx = -1;␊ |
207 | ␉int␉map;␊ |
208 | ␊ |
209 | ␉idx++;␊ |
210 | ␉if (idx < MAX_RAM_SLOTS)␊ |
211 | ␉{␊ |
212 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
213 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
214 | ␉␉{␊ |
215 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
216 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
217 | ␉␉␉return true;␊ |
218 | ␉␉}␊ |
219 | ␉}␊ |
220 | ␊ |
221 | ␉return false;␊ |
222 | //␉value->dword = 800;␊ |
223 | //␉return true;␊ |
224 | }␊ |
225 | ␊ |
226 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
227 | {␊ |
228 | ␉static int idx = -1;␊ |
229 | ␉int␉map;␊ |
230 | ␊ |
231 | ␉idx++;␊ |
232 | ␉if (idx < MAX_RAM_SLOTS)␊ |
233 | ␉{␊ |
234 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
235 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
236 | ␉␉{␊ |
237 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
238 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
239 | ␉␉␉return true;␊ |
240 | ␉␉}␊ |
241 | ␉}␊ |
242 | ␊ |
243 | ␉if (!bootInfo->memDetect)␊ |
244 | ␉␉return false;␊ |
245 | ␉value->string = NOT_AVAILABLE;␊ |
246 | ␉return true;␊ |
247 | }␊ |
248 | ␉␊ |
249 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
250 | {␊ |
251 | ␉static int idx = -1;␊ |
252 | ␉int␉map;␊ |
253 | ␊ |
254 | ␉idx++;␊ |
255 | ␊ |
256 | DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
257 | ␊ |
258 | ␉if (idx < MAX_RAM_SLOTS)␊ |
259 | ␉{␊ |
260 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
261 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
262 | ␉␉{␊ |
263 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
264 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
265 | ␉␉␉return true;␊ |
266 | ␉␉}␊ |
267 | ␉}␊ |
268 | ␊ |
269 | ␉if (!bootInfo->memDetect)␊ |
270 | ␉␉return false;␊ |
271 | ␉value->string = NOT_AVAILABLE;␊ |
272 | ␉return true;␊ |
273 | }␊ |
274 | ␊ |
275 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
276 | {␊ |
277 | ␉static int idx = -1;␊ |
278 | ␉int␉map;␊ |
279 | ␊ |
280 | ␉idx++;␊ |
281 | ␉if (idx < MAX_RAM_SLOTS)␊ |
282 | ␉{␊ |
283 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
284 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
285 | ␉␉{␊ |
286 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
287 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
288 | ␉␉␉return true;␊ |
289 | ␉␉}␊ |
290 | ␉}␊ |
291 | ␊ |
292 | ␉if (!bootInfo->memDetect)␊ |
293 | ␉␉return false;␊ |
294 | ␉value->string = NOT_AVAILABLE;␊ |
295 | ␉return true;␊ |
296 | }␊ |
297 | ␊ |
298 | ␊ |
299 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
300 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
301 | static const char * const SMTAG = "_SM_";␊ |
302 | static const char* const DMITAG = "_DMI_";␊ |
303 | ␊ |
304 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
305 | {␊ |
306 | ␉SMBEntryPoint␉*smbios;␊ |
307 | ␉/* ␊ |
308 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
309 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
310 | ␉ */␊ |
311 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
312 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
313 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
314 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
315 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
316 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
317 | ␉ {␊ |
318 | ␉␉␉return smbios;␊ |
319 | ␉ }␊ |
320 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
321 | ␉}␊ |
322 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
323 | ␉pause();␊ |
324 | ␉return NULL;␊ |
325 | }␊ |
326 | ␊ |
327 |