1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "modules.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | static uint16_t simpleGetSMBOemProcessorType(void);␊ |
21 | ␊ |
22 | ␊ |
23 | bool getProcessorInformationExternalClock(returnType *value)␊ |
24 | {␊ |
25 | ␉value->word = (uint16_t)(get_env(envFSBFreq)/1000000);␊ |
26 | ␉return true;␊ |
27 | }␊ |
28 | ␊ |
29 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
30 | {␊ |
31 | ␉// Note: it seems that AppleSMBIOS use the maximum clock to set the cpu clock␊ |
32 | ␉// that is showed in "About this mac" or in the System Information. ␊ |
33 | ␉// in my opinion the current clock should be used for this.␊ |
34 | ␉// value->word = get_env(envTSCFreq)/1000000;␊ |
35 | ␉␊ |
36 | ␉value->word = (uint16_t)(get_env(envCPUFreq)/1000000);␊ |
37 | ␉return true;␊ |
38 | }␊ |
39 | ␊ |
40 | bool getProcessorInformationCurrentClock(returnType *value)␊ |
41 | {␊ |
42 | ␉value->word = (uint16_t)(get_env(envCPUFreq)/1000000);␊ |
43 | ␉return true;␊ |
44 | }␊ |
45 | ␊ |
46 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
47 | {␊ |
48 | ␉if (get_env(envVendor) == CPUID_VENDOR_INTEL) ␊ |
49 | ␉{␉␉␊ |
50 | ␉␉switch (get_env(envFamily)) ␊ |
51 | ␉␉{␊ |
52 | ␉␉␉case 0x06:␊ |
53 | ␉␉␉{␊ |
54 | ␉␉␉␉switch (get_env(envModel))␊ |
55 | ␉␉␉␉{␊ |
56 | case CPUID_MODEL_BANIAS:␉// Banias␉␉0x09␊ |
57 | case CPUID_MODEL_DOTHAN:␉// Dothan␉␉0x0D␊ |
58 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊ |
59 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Merom␉␉0x0F␊ |
60 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊ |
61 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊ |
62 | ␉␉␉␉␉␉return false;␊ |
63 | ␊ |
64 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
65 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊ |
66 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊ |
67 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊ |
68 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊ |
69 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊ |
70 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
71 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
72 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
73 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
74 | ␉␉␉␉␉{␊ |
75 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
76 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
77 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
78 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
79 | ␉␉␉␉␉␉unsigned int i;␊ |
80 | ␉␉␉␉␉␉␊ |
81 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
82 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
83 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
84 | ␉␉␉␉␉␉{␊ |
85 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
86 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
87 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
88 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
89 | ␉␉␉␉␉␉␉␊ |
90 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
91 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
92 | ␉␉␉␉␉␉}␊ |
93 | ␉␉␉␉␉␉␊ |
94 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
95 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
96 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
97 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
98 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (get_env(envFSBFreq)/1000000));␊ |
99 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
100 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
101 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
102 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
103 | ␉␉␉␉␉␉return true;␊ |
104 | ␉␉␉␉␉}␊ |
105 | ␉␉␉␉␉default:␊ |
106 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
107 | ␉␉␉␉}␊ |
108 | ␉␉␉}␊ |
109 | ␉␉␉default:␊ |
110 | ␉␉␉␉break; ␊ |
111 | ␉␉}␊ |
112 | ␉}␊ |
113 | ␉return false;␊ |
114 | }␊ |
115 | ␊ |
116 | static uint16_t simpleGetSMBOemProcessorType(void)␊ |
117 | {␊ |
118 | uint8_t ncores = (uint8_t)get_env(envNoCores);␊ |
119 | ␉if (ncores >= 4) ␊ |
120 | ␉{␊ |
121 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
122 | ␉}␊ |
123 | ␉if (((ncores == 1) || (ncores == 2)) && !(get_env(envExtFeatures)& CPUID_EXTFEATURE_EM64T)) ␊ |
124 | ␉{␊ |
125 | ␉␉return 0x0201;␉// Core Solo / Duo␊ |
126 | ␉};␊ |
127 | ␉␊ |
128 | ␉return 0x0301;␉␉// Core 2 Solo / Duo␊ |
129 | }␊ |
130 | ␊ |
131 | bool getSMBOemProcessorType(returnType *value)␊ |
132 | {␊ |
133 | ␉static bool done = false;␉␉␊ |
134 | ␊ |
135 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
136 | ␊ |
137 | char * BrandString = (char*)get_env_ptr(envBrandString);␊ |
138 | ␊ |
139 | ␉if (get_env(envVendor) == CPUID_VENDOR_INTEL) ␊ |
140 | ␉{␊ |
141 | ␉␉if (!done)␊ |
142 | ␉␉{␊ |
143 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", BrandString, (uint32_t)get_env(envFamily), (uint32_t)get_env(envModel));␊ |
144 | ␉␉␉done = true;␊ |
145 | ␉␉}␊ |
146 | ␉␉␊ |
147 | ␉␉switch (get_env(envFamily)) ␊ |
148 | ␉␉{␊ |
149 | ␉␉␉case 0x06:␊ |
150 | ␉␉␉{␊ |
151 | ␉␉␉␉switch (get_env(envModel))␊ |
152 | ␉␉␉␉{␊ |
153 | case CPUID_MODEL_BANIAS:␉// Banias␉␉␊ |
154 | case CPUID_MODEL_DOTHAN:␉// Dothan␉␉␊ |
155 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// Yonah␊ |
156 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// Merom␊ |
157 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉␉// Penryn␊ |
158 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
159 | ␉␉␉␉␉␉return true;␊ |
160 | ␊ |
161 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊ |
162 | ␉␉␉␉␉␉if (strstr(BrandString, "Core(TM) i7"))␊ |
163 | value->word = 0x0701;␉// Core i7 ␊ |
164 | ␉␉␉␉␉␉return true;␊ |
165 | ␊ |
166 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊ |
167 | ␉␉␉␉␉␉if (strstr(BrandString, "Core(TM) i5"))␊ |
168 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
169 | ␉␉␉␉␉␉else␊ |
170 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊ |
171 | ␉␉␉␉␉␉return true;␊ |
172 | ␊ |
173 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
174 | ␉␉␉␉␉␉if (strstr(BrandString, "Core(TM) i5"))␊ |
175 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
176 | ␉␉␉␉␉␉else␊ |
177 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
178 | ␉␉␉␉␉␉return true;␊ |
179 | ␊ |
180 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
181 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
182 | ␉␉␉␉␉␉if (strstr(BrandString, "Core(TM) i3"))␊ |
183 | value->word = 0x901;␉// Core i3␊ |
184 | ␉␉␉␉␉␉else if (strstr(BrandString, "Core(TM) i5"))␊ |
185 | value->word = 0x601;␉// Core i5␊ |
186 | ␉␉␉␉␉␉else if (strstr(BrandString, "Core(TM) i7"))␊ |
187 | value->word = 0x0701;␉// Core i7␊ |
188 | ␉␉␉␉␉␉/*else ␊ |
189 | value->word = simpleGetSMBOemProcessorType();*/␊ |
190 | ␉␉␉␉␉␉return true;␊ |
191 | ␊ |
192 | case CPUID_MODEL_JAKETOWN:␊ |
193 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊ |
194 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
195 | ␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Core i7␊ |
196 | ␉␉␉␉␉␉return true;␊ |
197 | ␊ |
198 | ␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
199 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
200 | ␉␉␉␉␉␉return true;␊ |
201 | ␉␉␉␉␉default:␊ |
202 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
203 | ␉␉␉␉}␊ |
204 | ␉␉␉}␊ |
205 | ␉␉␉default:␊ |
206 | ␉␉␉␉break; ␊ |
207 | ␉␉}␊ |
208 | ␉}␊ |
209 | ␉␊ |
210 | ␉return false;␊ |
211 | }␊ |
212 | ␊ |
213 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
214 | {␊ |
215 | ␉static int idx = -1;␊ |
216 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
217 | ␉␉int␉map;␊ |
218 | ␊ |
219 | int * DmiDimm = (int*)get_env_ptr(envDmiDimm);␊ |
220 | RamSlotInfo_t * RamDimm = (RamSlotInfo_t*)get_env_ptr(envRamDimm);␊ |
221 | ␊ |
222 | ␉␉idx++;␊ |
223 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
224 | ␉␉{␊ |
225 | ␉␉␉map = DmiDimm[idx];␊ |
226 | ␉␉␉if (RamDimm[map].InUse && RamDimm[map].Type != 0)␊ |
227 | ␉␉␉{␊ |
228 | ␉␉␉␉DBG("RAM Detected Type = %d\n", RamDimm[map].Type);␊ |
229 | ␉␉␉␉value->byte = RamDimm[map].Type;␊ |
230 | ␉␉␉␉return true;␊ |
231 | ␉␉␉}␊ |
232 | ␉␉}␊ |
233 | ␉}␊ |
234 | ␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
235 | ␉return true;␊ |
236 | }␊ |
237 | ␊ |
238 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
239 | {␊ |
240 | ␉static int idx = -1;␊ |
241 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
242 | ␉␉int␉map;␊ |
243 | ␊ |
244 | int * DmiDimm = (int*)get_env_ptr(envDmiDimm);␊ |
245 | RamSlotInfo_t * RamDimm = (RamSlotInfo_t*)get_env_ptr(envRamDimm);␊ |
246 | ␊ |
247 | ␉␉idx++;␊ |
248 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
249 | ␉␉{␊ |
250 | ␉␉␉map = DmiDimm[idx];␊ |
251 | ␉␉␉if (RamDimm[map].InUse && RamDimm[map].Frequency != 0)␊ |
252 | ␉␉␉{␊ |
253 | ␉␉␉␉DBG("RAM Detected Freq = %d Mhz\n", RamDimm[map].Frequency);␊ |
254 | ␉␉␉␉value->dword = RamDimm[map].Frequency;␊ |
255 | ␉␉␉␉return true;␊ |
256 | ␉␉␉}␊ |
257 | ␉␉}␊ |
258 | ␉}␊ |
259 | ␉value->dword = 800;␊ |
260 | ␉return true;␊ |
261 | }␊ |
262 | ␊ |
263 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
264 | {␊ |
265 | ␉static int idx = -1;␊ |
266 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
267 | ␉␉int␉map;␊ |
268 | ␊ |
269 | int * DmiDimm = (int*)get_env_ptr(envDmiDimm);␊ |
270 | RamSlotInfo_t * RamDimm = (RamSlotInfo_t*)get_env_ptr(envRamDimm);␊ |
271 | ␊ |
272 | ␉␉idx++;␊ |
273 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
274 | ␉␉{␊ |
275 | ␉␉␉map = DmiDimm[idx];␊ |
276 | ␉␉␉if (RamDimm[map].InUse && strlen(RamDimm[map].Vendor) > 0)␊ |
277 | ␉␉␉{␊ |
278 | ␉␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, RamDimm[map].Vendor);␊ |
279 | ␉␉␉␉value->string = RamDimm[map].Vendor;␊ |
280 | ␉␉␉␉return true;␊ |
281 | ␉␉␉}␊ |
282 | ␉␉}␊ |
283 | ␉}␊ |
284 | ␉value->string = "N/A";␊ |
285 | ␉return true;␊ |
286 | }␊ |
287 | ␊ |
288 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
289 | {␊ |
290 | ␉static int idx = -1;␊ |
291 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
292 | ␉␉int␉map;␊ |
293 | ␊ |
294 | int * DmiDimm = (int*)get_env_ptr(envDmiDimm);␊ |
295 | RamSlotInfo_t * RamDimm = (RamSlotInfo_t*)get_env_ptr(envRamDimm);␊ |
296 | ␊ |
297 | ␉␉idx++;␊ |
298 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
299 | ␉␉{␊ |
300 | ␉␉␉map = DmiDimm[idx];␊ |
301 | ␉␉␉if (RamDimm[map].InUse && strlen(RamDimm[map].SerialNo) > 0)␊ |
302 | ␉␉␉{␊ |
303 | ␉␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊ |
304 | map, idx, RamDimm[map].SerialNo);␊ |
305 | ␉␉␉␉value->string = RamDimm[map].SerialNo;␊ |
306 | ␉␉␉␉return true;␊ |
307 | ␉␉␉}␊ |
308 | ␉␉}␊ |
309 | ␉}␊ |
310 | ␉value->string = "N/A";␊ |
311 | ␉return true;␊ |
312 | }␊ |
313 | ␊ |
314 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
315 | {␊ |
316 | ␉static int idx = -1;␊ |
317 | ␉if (execute_hook("isMemoryRegistred", NULL, NULL, NULL, NULL, NULL, NULL) == EFI_SUCCESS) {␊ |
318 | ␉␉int␉map;␊ |
319 | ␊ |
320 | int * DmiDimm = (int*)get_env_ptr(envDmiDimm);␊ |
321 | RamSlotInfo_t * RamDimm = (RamSlotInfo_t*)get_env_ptr(envRamDimm);␊ |
322 | ␊ |
323 | ␉␉idx++;␊ |
324 | ␉␉if (idx < MAX_RAM_SLOTS)␊ |
325 | ␉␉{␊ |
326 | ␉␉␉map = DmiDimm[idx];␊ |
327 | ␉␉␉if (RamDimm[map].InUse && strlen(RamDimm[map].PartNo) > 0)␊ |
328 | ␉␉␉{␊ |
329 | ␉␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, RamDimm[map].PartNo);␊ |
330 | ␉␉␉␉value->string = RamDimm[map].PartNo;␊ |
331 | ␉␉␉␉return true;␊ |
332 | ␉␉␉}␊ |
333 | ␉␉}␊ |
334 | ␉}␊ |
335 | ␉value->string = "N/A";␊ |
336 | ␉return true;␊ |
337 | }␊ |
338 | |