1 | /*␊ |
2 | * resolution.h␊ |
3 | * ␊ |
4 | *␉NOTE: I don't beleive this code is production ready / should be in trunk␊ |
5 | * Atleast, not in it's current state. ␊ |
6 | *␊ |
7 | * Created by Evan Lojewski on 3/4/10.␊ |
8 | * Copyright 2009. All rights reserved.␊ |
9 | *␊ |
10 | */␊ |
11 | #ifndef _RESOLUTION_H_␊ |
12 | #define _RESOLUTION_H_␊ |
13 | ␊ |
14 | //#include "libsaio.h"␊ |
15 | //#include "edid.h" //included␊ |
16 | #include "915resolution.h"␊ |
17 | ␊ |
18 | ␊ |
19 | void patchVideoBios()␊ |
20 | {␉␉␊ |
21 | ␉UInt32 x = 0, y = 0, bp = 0;␊ |
22 | ␉␊ |
23 | ␉verbose("Resolution:\n");␊ |
24 | ␉getResolution(&x, &y, &bp);␊ |
25 | ␉␊ |
26 | ␉if (x != 0 &&␊ |
27 | ␉␉y != 0 && ␊ |
28 | ␉␉bp != 0)␊ |
29 | ␉{␊ |
30 | ␉␉vbios_map * map;␊ |
31 | ␉␉␊ |
32 | ␉␉map = open_vbios(CT_UNKNOWN);␊ |
33 | ␉␉if(map)␊ |
34 | ␉␉{␊ |
35 | ␉␉␉unlock_vbios(map);␊ |
36 | ␉␉␉␊ |
37 | ␉␉␉set_mode(map, x, y, bp, 0, 0);␊ |
38 | ␉␉␉␊ |
39 | ␉␉␉relock_vbios(map);␊ |
40 | ␉␉␉␊ |
41 | ␉␉␉close_vbios(map);␊ |
42 | ␉␉}␊ |
43 | ␉}␊ |
44 | }␊ |
45 | ␊ |
46 | ␊ |
47 | /* Copied from 915 resolution created by steve tomljenovic␊ |
48 | *␊ |
49 | * This code is based on the techniques used in :␊ |
50 | *␊ |
51 | * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊ |
52 | * for demonstrating how to shadow the VBIOS into system RAM␊ |
53 | * and then modify it.␊ |
54 | *␊ |
55 | * - 1280patch by Andrew Tipton (andrewtipton null li).␊ |
56 | *␊ |
57 | * - 855resolution by Alain Poirier␊ |
58 | *␊ |
59 | * This source code is into the public domain.␊ |
60 | */␊ |
61 | ␊ |
62 | /**␊ |
63 | **␊ |
64 | **/␊ |
65 | ␊ |
66 | #define CONFIG_MECH_ONE_ADDR␉0xCF8␊ |
67 | #define CONFIG_MECH_ONE_DATA␉0xCFC␊ |
68 | ␊ |
69 | int freqs[] = { 60, 75, 85 };␊ |
70 | ␊ |
71 | UInt32 get_chipset_id(void)␊ |
72 | {␊ |
73 | ␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊ |
74 | ␉return inl(CONFIG_MECH_ONE_DATA);␊ |
75 | }␊ |
76 | ␊ |
77 | chipset_type get_chipset(UInt32 id)␊ |
78 | {␊ |
79 | ␉chipset_type type;␊ |
80 | ␉␉␊ |
81 | ␉switch (id) {␊ |
82 | ␉␉case 0x35758086:␊ |
83 | ␉␉␉type = CT_830;␊ |
84 | ␉␉␉break;␊ |
85 | ␉␉␉␊ |
86 | ␉␉case 0x25608086:␊ |
87 | ␉␉␉type = CT_845G;␊ |
88 | ␉␉␉break;␊ |
89 | ␉␉␉␊ |
90 | ␉␉case 0x35808086:␊ |
91 | ␉␉␉type = CT_855GM;␊ |
92 | ␉␉␉break;␊ |
93 | ␉␉␉␊ |
94 | ␉␉case 0x25708086:␊ |
95 | ␉␉␉type = CT_865G;␊ |
96 | ␉␉␉break;␊ |
97 | ␉␉␉␊ |
98 | ␉␉case 0x25808086:␊ |
99 | ␉␉␉type = CT_915G;␊ |
100 | ␉␉␉break;␊ |
101 | ␉␉␉␊ |
102 | ␉␉case 0x25908086:␊ |
103 | ␉␉␉type = CT_915GM;␊ |
104 | ␉␉␉break;␊ |
105 | ␉␉␉␊ |
106 | ␉␉case 0x27708086:␊ |
107 | ␉␉␉type = CT_945G;␊ |
108 | ␉␉␉break;␊ |
109 | ␉␉␉␊ |
110 | ␉␉case 0x27a08086:␊ |
111 | ␉␉␉type = CT_945GM;␊ |
112 | ␉␉␉break;␊ |
113 | ␉␉␉␊ |
114 | ␉␉case 0x27ac8086:␊ |
115 | ␉␉␉type = CT_945GME;␊ |
116 | ␉␉␉break;␊ |
117 | ␉␉␉␊ |
118 | ␉␉case 0x29708086:␊ |
119 | ␉␉␉type = CT_946GZ;␊ |
120 | ␉␉␉break;␊ |
121 | ␉␉␉␊ |
122 | ␉␉case 0x27748086:␊ |
123 | ␉␉␉type = CT_955X;␊ |
124 | ␉␉␉break;␊ |
125 | ␉␉␉␊ |
126 | ␉␉case 0x277c8086:␊ |
127 | ␉␉␉type = CT_975X;␊ |
128 | ␉␉␉break;␊ |
129 | ␊ |
130 | ␉␉case 0x29a08086:␊ |
131 | ␉␉␉type = CT_G965;␊ |
132 | ␉␉␉break;␊ |
133 | ␉␉␉␊ |
134 | ␉␉case 0x29908086:␊ |
135 | ␉␉␉type = CT_Q965;␊ |
136 | ␉␉␉break;␊ |
137 | ␉␉␉␊ |
138 | ␉␉case 0x81008086:␊ |
139 | ␉␉␉type = CT_500;␊ |
140 | ␉␉␉break;␊ |
141 | ␉␉␉␊ |
142 | ␉␉case 0x2e108086:␊ |
143 | ␉␉case 0X2e908086:␊ |
144 | ␉␉␉type = CT_B43;␊ |
145 | ␉␉␉break;␊ |
146 | ␊ |
147 | ␉␉case 0x2e208086:␊ |
148 | ␉␉␉type = CT_P45;␊ |
149 | ␉␉␉break;␊ |
150 | ␊ |
151 | ␉␉case 0x2e308086:␊ |
152 | ␉␉␉type = CT_G41;␊ |
153 | ␉␉␉break;␊ |
154 | ␉␉␉␉␉␊ |
155 | ␉␉case 0x29c08086:␊ |
156 | ␉␉␉type = CT_G31;␊ |
157 | ␉␉␉break;␊ |
158 | ␉␉␉␊ |
159 | ␉␉case 0x29208086:␊ |
160 | ␉␉␉type = CT_G45;␊ |
161 | ␉␉␉break;␊ |
162 | ␉␉␉␊ |
163 | ␉␉case 0xA0108086:␉// mobile␊ |
164 | ␉␉case 0xA0008086:␉// desktop␊ |
165 | ␉␉␉type = CT_3150;␊ |
166 | ␉␉␉break;␊ |
167 | ␉␉␉␊ |
168 | ␉␉case 0x2a008086:␊ |
169 | ␉␉␉type = CT_965GM;␊ |
170 | ␉␉␉break;␊ |
171 | ␉␉␉␊ |
172 | ␉␉case 0x29e08086:␊ |
173 | ␉␉␉type = CT_X48;␊ |
174 | ␉␉␉break;␉␉␉␊ |
175 | ␉␉␉␉␊ |
176 | ␉␉case 0x2a408086:␊ |
177 | ␉␉␉type = CT_GM45;␊ |
178 | ␉␉␉break;␊ |
179 | ␉␉␉␊ |
180 | ␉␉␉//␊ |
181 | ␉␉␉// Core processors␊ |
182 | ␉␉␉// http://pci-ids.ucw.cz/read/PC/8086␊ |
183 | ␉␉␉//␊ |
184 | ␉␉case 0x00408086: // Core Processor DRAM Controller␊ |
185 | ␉␉case 0x00448086: // Core Processor DRAM Controller␊ |
186 | ␉␉case 0x00488086: // Core Processor DRAM Controller␊ |
187 | ␉␉case 0x00698086: // Core Processor DRAM Controller␊ |
188 | ␉␉␉␊ |
189 | ␉␉case 0x01008086: // 2nd Generation Core Processor Family DRAM Controller␊ |
190 | ␉␉case 0x01048086: // 2nd Generation Core Processor Family DRAM Controller␊ |
191 | ␉␉case 0x01088086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊ |
192 | ␉␉case 0x010c8086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊ |
193 | ␉␉␉␊ |
194 | ␉␉case 0x01508086: // 3rd Generation Core Processor Family DRAM Controller␊ |
195 | ␉␉case 0x01548086: // 3rd Generation Core Processor Family DRAM Controller␊ |
196 | ␉␉case 0x01588086: // 3rd Generation Core Processor Family DRAM Controller␊ |
197 | ␉␉case 0x015c8086: // 3rd Generation Core Processor Family DRAM Controller␊ |
198 | ␉␉␉verbose(" core proc identified\n");␊ |
199 | ␉␉␉type = CT_CORE_PROC;␊ |
200 | ␉␉␉break;␊ |
201 | ␉␉␉␊ |
202 | ␉␉␉␊ |
203 | ␉␉default:␊ |
204 | ␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊ |
205 | ␉␉␉{␊ |
206 | ␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊ |
207 | ␉␉␉␉//getc();␊ |
208 | ␉␉␉␉type = CT_UNKNOWN_INTEL;␊ |
209 | ␉␉␉␉//type = CT_UNKNOWN;␊ |
210 | ␊ |
211 | ␉␉␉}␊ |
212 | ␉␉␉else␊ |
213 | ␉␉␉{␊ |
214 | ␉␉␉␉type = CT_UNKNOWN;␊ |
215 | ␉␉␉}␊ |
216 | ␉␉␉break;␊ |
217 | ␉}␊ |
218 | ␉return type;␊ |
219 | }␊ |
220 | ␊ |
221 | vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊ |
222 | {␊ |
223 | ␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊ |
224 | ␉return ptr;␊ |
225 | }␊ |
226 | ␊ |
227 | vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊ |
228 | {␊ |
229 | ␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊ |
230 | ␉return ptr;␊ |
231 | }␊ |
232 | ␊ |
233 | vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊ |
234 | {␊ |
235 | ␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊ |
236 | ␉return ptr;␊ |
237 | }␊ |
238 | ␊ |
239 | char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊ |
240 | {␊ |
241 | ␉UInt32 i;␊ |
242 | ␉UInt16 r1, r2;␊ |
243 | ␉␊ |
244 | ␉r1 = r2 = 32000;␊ |
245 | ␉␊ |
246 | ␉for (i=0; i < map->mode_table_size; i++)␊ |
247 | ␉{␊ |
248 | ␉␉if (map->mode_table[i].resolution <= r1)␊ |
249 | ␉␉{␊ |
250 | ␉␉␉r1 = map->mode_table[i].resolution;␊ |
251 | ␉␉}␊ |
252 | ␉␉else␊ |
253 | ␉␉{␊ |
254 | ␉␉␉if (map->mode_table[i].resolution <= r2)␊ |
255 | ␉␉␉{␊ |
256 | ␉␉␉␉r2 = map->mode_table[i].resolution;␊ |
257 | ␉␉␉}␊ |
258 | ␉␉}␊ |
259 | ␉␉␊ |
260 | ␉␉/*printf("r1 = %d r2 = %d\n", r1, r2);*/␊ |
261 | ␉}␊ |
262 | ␉␊ |
263 | ␉return (r2-r1-6) % entry_size == 0;␊ |
264 | }␊ |
265 | ␊ |
266 | void close_vbios(vbios_map * map);␊ |
267 | ␊ |
268 | char detect_ati_bios_type(vbios_map * map)␊ |
269 | {␉␊ |
270 | ␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊ |
271 | }␊ |
272 | ␊ |
273 | ␊ |
274 | vbios_map * open_vbios(chipset_type forced_chipset)␊ |
275 | {␊ |
276 | ␉UInt32 z;␊ |
277 | ␉vbios_map * map = malloc(sizeof(vbios_map));␊ |
278 | ␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊ |
279 | ␉/*␊ |
280 | ␉ * Determine chipset␊ |
281 | ␉ */␊ |
282 | ␉␊ |
283 | ␉if (forced_chipset == CT_UNKNOWN)␊ |
284 | ␉{␊ |
285 | ␉␉map->chipset_id = get_chipset_id();␊ |
286 | ␉␉map->chipset = get_chipset(map->chipset_id);␊ |
287 | ␉}␊ |
288 | ␉else if (forced_chipset != CT_UNKNOWN)␊ |
289 | ␉{␊ |
290 | ␉␉map->chipset = forced_chipset;␊ |
291 | ␉}␊ |
292 | ␉␊ |
293 | ␉␊ |
294 | ␉if (map->chipset == CT_UNKNOWN)␊ |
295 | ␉{␊ |
296 | ␉␉verbose(" Unknown chipset type: %08x.\n", map->chipset_id);␊ |
297 | ␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊ |
298 | ␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊ |
299 | ␉␉close_vbios(map);␊ |
300 | ␉␉return 0;␊ |
301 | ␉} else {␊ |
302 | ␉␉verbose(" Detected chipset/proc id (DRAM controller): %08x\n", map->chipset_id);␊ |
303 | ␉}␊ |
304 | ␉␊ |
305 | ␉␊ |
306 | ␉verbose(" VBios: ");␊ |
307 | ␉/*␊ |
308 | ␉ * Map the video bios to memory␊ |
309 | ␉ */␊ |
310 | ␉map->bios_ptr=(char*)VBIOS_START;␊ |
311 | ␉␊ |
312 | ␉/*␊ |
313 | ␉ * check if we have ATI Radeon␊ |
314 | ␉ */␊ |
315 | ␉map->ati_tables.base = map->bios_ptr;␊ |
316 | ␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊ |
317 | ␉if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)␊ |
318 | ␉{␊ |
319 | ␉␉verbose("ATI");␊ |
320 | ␉␉// ATI Radeon Card␊ |
321 | ␉␉map->bios = BT_ATI_1;␊ |
322 | ␉␉␊ |
323 | ␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊ |
324 | ␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊ |
325 | ␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊ |
326 | ␉␉␊ |
327 | ␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊ |
328 | ␉␉if (map->ati_mode_table == 0)␊ |
329 | ␉␉{␊ |
330 | ␉␉␉printf("Unable to locate the mode table.\n");␊ |
331 | ␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
332 | ␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
333 | ␉␉␉printf("Chipset: %d\n", map->chipset);␊ |
334 | ␉␉␉close_vbios(map);␊ |
335 | ␉␉␉return 0;␊ |
336 | ␉␉}␊ |
337 | ␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊ |
338 | ␉␉␊ |
339 | ␉␉if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;␊ |
340 | ␉␉␊ |
341 | ␉␉if (map->bios == BT_ATI_1) {␊ |
342 | ␉␉␉verbose(", BT_ATI_1\n");␊ |
343 | ␉␉} else {␊ |
344 | ␉␉␉verbose(", BT_ATI_2\n");␊ |
345 | ␉␉}␊ |
346 | ␉}␊ |
347 | ␉else {␊ |
348 | ␉␉␊ |
349 | ␉␉/*␊ |
350 | ␉␉ * check if we have NVIDIA␊ |
351 | ␉␉ */␊ |
352 | ␊ |
353 | ␉␉int i = 0;␊ |
354 | ␉␉while (i < 512)␊ |
355 | ␉␉{ // we don't need to look through the whole bios, just the first 512 bytes␊ |
356 | ␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊ |
357 | ␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊ |
358 | ␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊ |
359 | ␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊ |
360 | ␉␉␉{␊ |
361 | ␉␉␉␉verbose("nVidia\n");␊ |
362 | ␉␉␉␉map->bios = BT_NVDA;␊ |
363 | ␉␉␉␉unsigned short nv_data_table_offset = 0;␊ |
364 | ␉␉␉␉unsigned short * nv_data_table;␊ |
365 | ␉␉␉␉NV_VESA_TABLE * std_vesa;␊ |
366 | ␉␉␉␉␊ |
367 | ␉␉␉␉int i = 0;␊ |
368 | ␉␉␉␉␊ |
369 | ␉␉␉␉while (i < 0x300)␊ |
370 | ␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊ |
371 | ␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊ |
372 | ␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊ |
373 | ␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊ |
374 | ␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊ |
375 | ␉␉␉␉␉{␊ |
376 | ␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊ |
377 | ␉␉␉␉␉␉break;␊ |
378 | ␉␉␉␉␉}␊ |
379 | ␉␉␉␉␉i++;␊ |
380 | ␉␉␉␉}␊ |
381 | ␉␉␉␉␊ |
382 | ␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊ |
383 | ␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊ |
384 | ␉␉␉␉␊ |
385 | ␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊ |
386 | ␉␉␉␉if (map->nv_mode_table == 0)␊ |
387 | ␉␉␉␉{␊ |
388 | ␉␉␉␉␉printf("Unable to locate the mode table.\n");␊ |
389 | ␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
390 | ␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
391 | ␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊ |
392 | ␉␉␉␉␉close_vbios(map);␊ |
393 | ␉␉␉␉␉return 0;␊ |
394 | ␉␉␉␉}␊ |
395 | ␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊ |
396 | ␉␉␉␉␊ |
397 | ␉␉␉␉break;␊ |
398 | ␉␉␉}␊ |
399 | ␉␉␉i++;␊ |
400 | ␉␉}␊ |
401 | ␉}␊ |
402 | ␉␊ |
403 | ␉␊ |
404 | ␉/*␊ |
405 | ␉ * check if we have Intel␊ |
406 | ␉ */␊ |
407 | ␉␊ |
408 | ␉/*if (map->chipset == CT_UNKNOWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊ |
409 | ␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊ |
410 | ␉ ␊ |
411 | ␉ printf("Chipset Id: %x\n", map->chipset_id);␊ |
412 | ␉ ␊ |
413 | ␉ printf("Please report this problem to stomljen@yahoo.com\n");␊ |
414 | ␉ ␊ |
415 | ␉ close_vbios(map);␊ |
416 | ␉ return 0;␊ |
417 | ␉ }*/␊ |
418 | ␉␊ |
419 | ␉/*␊ |
420 | ␉ * check for others␊ |
421 | ␉ */␊ |
422 | ␉␊ |
423 | ␊ |
424 | ␉␊ |
425 | ␉/*␊ |
426 | ␉ * Figure out where the mode table is ␊ |
427 | ␉ */␊ |
428 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA)) ␊ |
429 | ␉{␊ |
430 | ␉␉char* p = map->bios_ptr + 16;␊ |
431 | ␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊ |
432 | ␉␉␊ |
433 | ␉␉verbose("Other");␊ |
434 | ␉␉while (p < limit && map->mode_table == 0)␊ |
435 | ␉␉{␊ |
436 | ␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊ |
437 | ␉␉␉␊ |
438 | ␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊ |
439 | ␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊ |
440 | ␉␉␉{␊ |
441 | ␉␉␉␉map->mode_table = mode_ptr;␊ |
442 | ␉␉␉}␊ |
443 | ␉␉␉␊ |
444 | ␉␉␉p++;␊ |
445 | ␉␉}␊ |
446 | ␉␉␊ |
447 | ␉␉if (map->mode_table == 0) ␊ |
448 | ␉␉{␊ |
449 | ␉␉␉close_vbios(map);␊ |
450 | ␉␉␉return 0;␊ |
451 | ␉␉}␊ |
452 | ␉}␊ |
453 | ␉␊ |
454 | ␉␊ |
455 | ␉/*␊ |
456 | ␉ * Determine size of mode table␊ |
457 | ␉ */␊ |
458 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
459 | ␉{␊ |
460 | ␉␉vbios_mode * mode_ptr = map->mode_table;␊ |
461 | ␉␉␊ |
462 | ␉␉while (mode_ptr->mode != 0xff)␊ |
463 | ␉␉{␊ |
464 | ␉␉␉map->mode_table_size++;␊ |
465 | ␉␉␉mode_ptr++;␊ |
466 | ␉␉}␊ |
467 | ␉}␊ |
468 | ␉␊ |
469 | ␉/*␊ |
470 | ␉ * Figure out what type of bios we have␊ |
471 | ␉ * order of detection is important␊ |
472 | ␉ */␊ |
473 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
474 | ␉{␊ |
475 | ␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊ |
476 | ␉␉{␊ |
477 | ␉␉␉map->bios = BT_3;␊ |
478 | ␉␉␉verbose(", BT_3\n");␊ |
479 | ␉␉}␊ |
480 | ␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊ |
481 | ␉␉{␊ |
482 | ␉␉␉map->bios = BT_2;␊ |
483 | ␉␉␉verbose(", BT_2\n");␊ |
484 | ␉␉}␊ |
485 | ␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊ |
486 | ␉␉{␊ |
487 | ␉␉␉map->bios = BT_1;␊ |
488 | ␉␉␉verbose(", BT_1\n");␊ |
489 | ␉␉}␊ |
490 | ␉␉else {␊ |
491 | ␉␉␉verbose(" - unknown\n");␊ |
492 | ␉␉␉return 0;␊ |
493 | ␉␉}␊ |
494 | ␉}␊ |
495 | ␉␊ |
496 | ␉return map;␊ |
497 | }␊ |
498 | ␊ |
499 | void close_vbios(vbios_map * map)␊ |
500 | {␊ |
501 | ␉free(map);␊ |
502 | }␊ |
503 | ␊ |
504 | void unlock_vbios(vbios_map * map)␊ |
505 | {␊ |
506 | ␉␊ |
507 | ␉map->unlocked = TRUE;␊ |
508 | ␊ |
509 | ␉switch (map->chipset) {␊ |
510 | ␉␉case CT_UNKNOWN:␊ |
511 | ␉␉␉break;␊ |
512 | ␉␉case CT_830:␊ |
513 | ␉␉case CT_855GM:␊ |
514 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
515 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
516 | ␉␉␉␊ |
517 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
518 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
519 | ␉␉␉break;␊ |
520 | ␉␉case CT_845G:␊ |
521 | ␉␉case CT_865G:␊ |
522 | ␉␉case CT_915G:␊ |
523 | ␉␉case CT_915GM:␊ |
524 | ␉␉case CT_945G:␊ |
525 | ␉␉case CT_945GM:␊ |
526 | ␉␉case CT_945GME:␊ |
527 | ␉␉case CT_946GZ:␊ |
528 | ␉␉case CT_G965:␊ |
529 | ␉␉case CT_Q965:␊ |
530 | ␉␉case CT_965GM:␊ |
531 | ␉␉case CT_975X:␊ |
532 | ␉␉case CT_P35:␊ |
533 | ␉␉case CT_955X:␊ |
534 | ␉␉case CT_X48:␊ |
535 | ␉␉case CT_B43:␊ |
536 | ␉␉case CT_Q45:␊ |
537 | ␉␉case CT_P45:␊ |
538 | ␉␉case CT_GM45:␊ |
539 | ␉␉case CT_G45:␊ |
540 | ␉␉case CT_G41:␊ |
541 | ␉␉case CT_G31:␊ |
542 | ␉␉case CT_500:␊ |
543 | ␉␉case CT_3150:␊ |
544 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
545 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
546 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
547 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
548 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
549 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
550 | ␉␉␉break;␊ |
551 | ␉␉case CT_CORE_PROC:␉ // Core procs - PAM regs are 80h - 86h␊ |
552 | ␉␉case CT_UNKNOWN_INTEL:␉// Assume newer intel chipset is the same as before␊ |
553 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
554 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
555 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
556 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
557 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
558 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
559 | ␉␉␉break;␊ |
560 | ␉}␊ |
561 | ␉␊ |
562 | #if DEBUG␊ |
563 | ␉{␊ |
564 | ␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
565 | ␉␉verbose("unlock PAM: (0x%08x)\n", t);␊ |
566 | ␉}␊ |
567 | #endif␊ |
568 | }␊ |
569 | ␊ |
570 | void relock_vbios(vbios_map * map)␊ |
571 | {␊ |
572 | ␉␊ |
573 | ␉map->unlocked = FALSE;␊ |
574 | ␉␊ |
575 | ␉switch (map->chipset)␊ |
576 | ␉{␊ |
577 | ␉␉case CT_UNKNOWN:␊ |
578 | ␉␉␉break;␊ |
579 | ␉␉case CT_830:␊ |
580 | ␉␉case CT_855GM:␊ |
581 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
582 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊ |
583 | ␉␉␉break;␊ |
584 | ␉␉case CT_845G:␊ |
585 | ␉␉case CT_865G:␊ |
586 | ␉␉case CT_915G:␊ |
587 | ␉␉case CT_915GM:␊ |
588 | ␉␉case CT_945G:␊ |
589 | ␉␉case CT_945GM:␊ |
590 | ␉␉case CT_945GME:␊ |
591 | ␉␉case CT_946GZ:␊ |
592 | ␉␉case CT_G965:␊ |
593 | ␉␉case CT_955X:␊ |
594 | ␉␉case CT_G45:␊ |
595 | ␉␉case CT_Q965:␊ |
596 | ␉␉case CT_965GM:␊ |
597 | ␉␉case CT_975X:␊ |
598 | ␉␉case CT_P35:␊ |
599 | ␉␉case CT_X48:␊ |
600 | ␉␉case CT_B43:␊ |
601 | ␉␉case CT_Q45:␊ |
602 | ␉␉case CT_P45:␊ |
603 | ␉␉case CT_GM45:␊ |
604 | ␉␉case CT_G41:␊ |
605 | ␉␉case CT_G31:␊ |
606 | ␉␉case CT_500:␊ |
607 | ␉␉case CT_3150:␊ |
608 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
609 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
610 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
611 | ␉␉␉break;␊ |
612 | ␉␉case CT_CORE_PROC:␊ |
613 | ␉␉case CT_UNKNOWN_INTEL:␊ |
614 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
615 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
616 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
617 | ␉␉␉break;␊ |
618 | ␉}␊ |
619 | ␉␊ |
620 | #if DEBUG␊ |
621 | ␉{␊ |
622 | UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
623 | ␉␉verbose("relock PAM: (0x%08x)\n", t);␊ |
624 | ␉}␊ |
625 | #endif␊ |
626 | }␊ |
627 | ␊ |
628 | ␊ |
629 | int getMode(edid_mode *mode)␊ |
630 | {␊ |
631 | ␉char* edidInfo = readEDID();␊ |
632 | ␉␉␉␊ |
633 | ␉if(!edidInfo) return 1;␊ |
634 | //Slice␊ |
635 | ␉if(!fb_parse_edid((struct EDID *)edidInfo, mode) || !mode->h_active) ␊ |
636 | ␉{␊ |
637 | ␉␉free( edidInfo );␊ |
638 | ␉␉return 1;␊ |
639 | ␉}␊ |
640 | /*␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊ |
641 | ␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊ |
642 | ␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊ |
643 | ␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊ |
644 | ␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊ |
645 | ␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊ |
646 | ␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊ |
647 | ␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊ |
648 | ␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊ |
649 | */␉␉␊ |
650 | ␉␉␊ |
651 | ␉free( edidInfo );␊ |
652 | ␉␉␊ |
653 | ␉return 0;␊ |
654 | ␉␉␊ |
655 | }␊ |
656 | ␊ |
657 | ␊ |
658 | static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊ |
659 | ␉␉␉␉␉␉unsigned long *clock,␊ |
660 | ␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊ |
661 | ␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊ |
662 | {␊ |
663 | ␉UInt32 hbl, vbl, vfreq;␊ |
664 | ␉␊ |
665 | ␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊ |
666 | ␉vfreq = vbl * freq;␊ |
667 | ␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊ |
668 | ␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊ |
669 | ␉␊ |
670 | ␉*vsyncstart = y;␊ |
671 | ␉*vsyncend = y + 3;␊ |
672 | ␉*vblank = vbl - 1;␊ |
673 | ␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊ |
674 | ␉*hsyncend = x + hbl / 2 - 1;␊ |
675 | ␉*hblank = x + hbl - 1;␊ |
676 | ␉*clock = (x + hbl) * vfreq / 1000;␊ |
677 | }␊ |
678 | ␊ |
679 | void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊ |
680 | ␉UInt32 xprev, yprev;␊ |
681 | ␉UInt32 i = 0, j;␊ |
682 | ␉// patch first available mode␊ |
683 | ␉␊ |
684 | ␉//␉for (i=0; i < map->mode_table_size; i++) {␊ |
685 | ␉//␉␉if (map->mode_table[0].mode == mode) {␊ |
686 | ␉verbose(" Patching: ");␊ |
687 | ␉switch(map->bios) {␊ |
688 | ␉␉case BT_INTEL:␊ |
689 | ␉␉␉verbose("BT_INTEL - not supported\n");␊ |
690 | ␉␉␉return;␊ |
691 | ␊ |
692 | ␉␉case BT_1:␊ |
693 | ␉␉{␊ |
694 | ␉␉␉verbose("BT_1 patched.\n");␊ |
695 | ␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊ |
696 | ␉␉␉␊ |
697 | ␉␉␉if (bp) {␊ |
698 | ␉␉␉␉map->mode_table[i].bits_per_pixel = bp;␊ |
699 | ␉␉␉}␊ |
700 | ␉␉␉␊ |
701 | ␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊ |
702 | ␉␉␉res->x1 = (x & 0xff);␊ |
703 | ␉␉␉␊ |
704 | ␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊ |
705 | ␉␉␉res->y1 = (y & 0xff);␊ |
706 | ␉␉␉if (htotal)␊ |
707 | ␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊ |
708 | ␉␉␉␊ |
709 | ␉␉␉if (vtotal)␊ |
710 | ␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊ |
711 | ␉␉␉␊ |
712 | ␉␉␉break;␊ |
713 | ␉␉}␊ |
714 | ␉␉case BT_2:␊ |
715 | ␉␉{␊ |
716 | ␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊ |
717 | ␉␉␉␊ |
718 | ␉␉␉res->xchars = x / 8;␊ |
719 | ␉␉␉res->ychars = y / 16 - 1;␊ |
720 | ␉␉␉xprev = res->modelines[0].x1;␊ |
721 | ␉␉␉yprev = res->modelines[0].y1;␊ |
722 | ␉␉␉␊ |
723 | ␉␉␉for(j=0; j < 3; j++) {␊ |
724 | ␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊ |
725 | ␉␉␉␉␊ |
726 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊ |
727 | ␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊ |
728 | ␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊ |
729 | ␉␉␉␉␉␊ |
730 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
731 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
732 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
733 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
734 | ␉␉␉␉␉␊ |
735 | ␉␉␉␉␉if (htotal)␊ |
736 | ␉␉␉␉␉␉modeline->htotal = htotal;␊ |
737 | ␉␉␉␉␉else␊ |
738 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
739 | ␉␉␉␉␉␊ |
740 | ␉␉␉␉␉if (vtotal)␊ |
741 | ␉␉␉␉␉␉modeline->vtotal = vtotal;␊ |
742 | ␉␉␉␉␉else␊ |
743 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
744 | ␉␉␉␉}␊ |
745 | ␉␉␉}␊ |
746 | ␉␉␉verbose("BT_1 patched.\n");␊ |
747 | ␉␉␉break;␊ |
748 | ␉␉}␊ |
749 | ␉␉case BT_3:␊ |
750 | ␉␉{␊ |
751 | ␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊ |
752 | ␉␉␉␊ |
753 | ␉␉␉xprev = res->modelines[0].x1;␊ |
754 | ␉␉␉yprev = res->modelines[0].y1;␊ |
755 | ␉␉␉␊ |
756 | ␉␉␉for (j=0; j < 3; j++) {␊ |
757 | ␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊ |
758 | ␉␉␉␉␊ |
759 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev) {␊ |
760 | ␉␉␉␉␉modeline->x1 = modeline->x2 = x-1;␊ |
761 | ␉␉␉␉␉modeline->y1 = modeline->y2 = y-1;␊ |
762 | ␉␉␉␉␉␊ |
763 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
764 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
765 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
766 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
767 | ␉␉␉␉␉if (htotal)␊ |
768 | ␉␉␉␉␉␉modeline->htotal = htotal;␊ |
769 | ␉␉␉␉␉else␊ |
770 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
771 | ␉␉␉␉␉if (vtotal)␊ |
772 | ␉␉␉␉␉␉modeline->vtotal = vtotal;␊ |
773 | ␉␉␉␉␉else␊ |
774 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
775 | ␉␉␉␉␉␊ |
776 | ␉␉␉␉␉modeline->timing_h = y-1;␊ |
777 | ␉␉␉␉␉modeline->timing_v = x-1;␊ |
778 | ␉␉␉␉}␊ |
779 | ␉␉␉}␊ |
780 | ␉␉␉verbose("BT_3 patched.\n");␊ |
781 | ␉␉␉break;␊ |
782 | ␉␉}␊ |
783 | ␉␉case BT_ATI_1:␊ |
784 | ␉␉{␊ |
785 | ␉␉␉verbose("BT_ATI_1");␊ |
786 | ␉␉␉edid_mode mode;␊ |
787 | ␉␉␉␉␊ |
788 | ␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊ |
789 | ␊ |
790 | ␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {␊ |
791 | ␉␉␉if (!getMode(&mode)) {␊ |
792 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊ |
793 | ␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊ |
794 | ␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊ |
795 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
796 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊ |
797 | ␉␉␉␉␉␊ |
798 | ␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊ |
799 | ␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊ |
800 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
801 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊ |
802 | ␊ |
803 | ␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊ |
804 | ␉␉␉} else {␊ |
805 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
806 | ␉␉␉}␊ |
807 | ␉␉␉/*else␊ |
808 | ␉␉␉{␊ |
809 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
810 | ␊ |
811 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
812 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
813 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
814 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
815 | ␊ |
816 | ␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊ |
817 | ␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊ |
818 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊ |
819 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
820 | ␊ |
821 | ␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊ |
822 | ␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊ |
823 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊ |
824 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊ |
825 | ␉␉␉␉␉␉␉␉␉␉␉␉␊ |
826 | ␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊ |
827 | ␉␉␉ }*/␊ |
828 | ␉␊ |
829 | ␉␉␉break;␊ |
830 | ␉␉}␊ |
831 | ␉␉case BT_ATI_2:␊ |
832 | ␉␉{␊ |
833 | ␉␉␉verbose("BT_ATI_2");␊ |
834 | ␉␉␉edid_mode mode;␊ |
835 | ␉␉␉␉␉␉␊ |
836 | ␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊ |
837 | ␉␉␉␊ |
838 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
839 | ␉␉␉if (!getMode(&mode)) {␊ |
840 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊ |
841 | ␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊ |
842 | ␉␉␉␉mode_timing->usHActive = mode.h_active;␊ |
843 | ␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊ |
844 | ␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊ |
845 | ␉␉␉␉␉␉␉␉␉␉␊ |
846 | ␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊ |
847 | ␉␉␉␉mode_timing->usVActive = mode.v_active;␊ |
848 | ␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊ |
849 | ␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊ |
850 | ␉␉␉␉␉␉␉␉␉␉␊ |
851 | ␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊ |
852 | ␉␉␉} else {␊ |
853 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
854 | ␉␉␉}␊ |
855 | ␉␉␉/*else␊ |
856 | ␉␉␉{␊ |
857 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
858 | ␉␉␉␊ |
859 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
860 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
861 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
862 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
863 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
864 | ␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊ |
865 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHActive = x;␊ |
866 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊ |
867 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
868 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊ |
869 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊ |
870 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVActive = y;␊ |
871 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊ |
872 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
873 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉␊ |
874 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊ |
875 | ␉␉␉␉␉␉␉␉␉ +␉␉␉␉␉}*/␊ |
876 | ␉␉␉␉␊ |
877 | ␉␉␉␊ |
878 | ␉␉␉break;␊ |
879 | ␉␉}␊ |
880 | ␉␉case BT_NVDA:␊ |
881 | ␉␉{␊ |
882 | ␉␉␉verbose("BT_NVDA");␊ |
883 | ␉␉␉edid_mode mode;␊ |
884 | ␉␉␉␊ |
885 | ␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊ |
886 | ␉␉␉␊ |
887 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
888 | ␉␉␉if (!getMode(&mode)) {␊ |
889 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode %d patched!\n", mode.h_active, mode.v_active, i);␊ |
890 | ␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊ |
891 | ␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊ |
892 | ␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
893 | ␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊ |
894 | ␉␉␉␉␊ |
895 | ␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊ |
896 | ␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊ |
897 | ␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
898 | ␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊ |
899 | ␉␉␉␉␊ |
900 | ␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊ |
901 | ␉␉␉} else {␊ |
902 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
903 | ␉␉␉}␊ |
904 | ␉␉␉/*else␊ |
905 | ␉␉␉ {␊ |
906 | ␉␉␉ vbios_modeline_type2 modeline;␊ |
907 | ␉␉␉ ␊ |
908 | ␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
909 | ␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊ |
910 | ␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊ |
911 | ␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊ |
912 | ␉␉␉ ␊ |
913 | ␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊ |
914 | ␉␉␉ mode_timing[i].usH_Active = x;␊ |
915 | ␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊ |
916 | ␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊ |
917 | ␉␉␉ ␊ |
918 | ␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊ |
919 | ␉␉␉ mode_timing[i].usV_Active = y;␊ |
920 | ␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊ |
921 | ␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊ |
922 | ␉␉␉ ␊ |
923 | ␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊ |
924 | ␉␉␉ }*/␊ |
925 | ␉␉␉break;␊ |
926 | ␉␉}␊ |
927 | ␉␉case BT_UNKNOWN:␊ |
928 | ␉␉{␊ |
929 | ␉␉␉verbose(" Unknown - vbios not patched\n");␊ |
930 | ␉␉␉break;␊ |
931 | ␉␉}␊ |
932 | ␉}␊ |
933 | ␉//␉␉}␊ |
934 | ␉//␉}␊ |
935 | }␊ |
936 | ␊ |
937 | #endif // _RESOLUTION_H_ |