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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9#include "bootstruct.h"␊
10#include "boot.h"␊
11␊
12#ifndef DEBUG_CPU␊
13#define DEBUG_CPU 0␊
14#endif␊
15␊
16#if DEBUG_CPU␊
17#define DBG(x...)␉␉printf(x)␊
18#else␊
19#define DBG(x...)␉␉msglog(x)␊
20#endif␊
21␊
22/*␊
23 * timeRDTSC()␊
24 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
25 * It pauses until the value is latched in the counter␊
26 * and then reads the time stamp counter to return to the caller.␊
27 */␊
28uint64_t timeRDTSC(void)␊
29{␊
30 int␉␉attempts = 0;␊
31 uint64_t latchTime;␊
32 uint64_t␉saveTime,intermediate;␊
33 unsigned int timerValue, lastValue;␊
34 //boolean_t␉int_enabled;␊
35 /*␊
36 * Table of correction factors to account for␊
37 *␉ - timer counter quantization errors, and␊
38 *␉ - undercounts 0..5␊
39 */␊
40#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
41#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
42#define SAMPLE_NSECS␉␉(2000000000LL)␊
43#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
44#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
45 uint64_t␉scale[6] = {␊
46␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
47␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
48␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
49␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
50␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
51␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
52 };␊
53 ␊
54restart:␊
55 if (attempts >= 9) // increase to up to 9 attempts.␊
56 // This will flash-reboot. TODO: Use tscPanic instead.␊
57 printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
58 attempts++;␊
59 enable_PIT2();␉␉// turn on PIT2␊
60 set_PIT2(0);␉␉// reset timer 2 to be zero␊
61 latchTime = rdtsc64();␉// get the time stamp to time ␊
62 latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
63 set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
64 saveTime = rdtsc64();␉// now time how long a 20th a second is...␊
65 get_PIT2(&lastValue);␊
66 get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
67 do {␊
68␉␉intermediate = get_PIT2(&timerValue);␊
69␉␉if (timerValue > lastValue) {␊
70␉␉␉// Timer wrapped␊
71␉␉␉set_PIT2(0);␊
72␉␉␉disable_PIT2();␊
73␉␉␉goto restart;␊
74␉␉}␊
75␉␉lastValue = timerValue;␊
76 } while (timerValue > 5);␊
77 printf("timerValue␉ %d\n",timerValue);␊
78 printf("intermediate 0x%016llx\n",intermediate);␊
79 printf("saveTime␉ 0x%016llx\n",saveTime);␊
80 ␊
81 intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
82 intermediate *= scale[timerValue];␉// rescale measured time spent␊
83 intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
84 intermediate += latchTime;␉␉// add on our save fudge␊
85 ␊
86 set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
87 disable_PIT2();␉␉␉// turn off PIT 2␊
88␉␊
89 return intermediate;␊
90}␊
91␊
92/*␊
93 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
94 */␊
95static uint64_t measure_tsc_frequency(void)␊
96{␊
97␉uint64_t tscStart;␊
98␉uint64_t tscEnd;␊
99␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
100␉unsigned long pollCount;␊
101␉uint64_t retval = 0;␊
102␉int i;␊
103␉␊
104␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
105␉ * counter 2. We run this loop 3 times to make sure the cache␊
106␉ * is hot and we take the minimum delta from all of the runs.␊
107␉ * That is to say that we're biased towards measuring the minimum␊
108␉ * number of TSC ticks that occur while waiting for the timer to␊
109␉ * expire. That theoretically helps avoid inconsistencies when␊
110␉ * running under a VM if the TSC is not virtualized and the host␊
111␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
112␉ */␊
113␉for(i = 0; i < 10; ++i)␊
114␉{␊
115␉␉enable_PIT2();␊
116␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
117␉␉tscStart = rdtsc64();␊
118␉␉pollCount = poll_PIT2_gate();␊
119␉␉tscEnd = rdtsc64();␊
120␉␉/* The poll loop must have run at least a few times for accuracy */␊
121␉␉if (pollCount <= 1)␊
122␉␉␉continue;␊
123␉␉/* The TSC must increment at LEAST once every millisecond.␊
124␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
125␉␉ * be >= 30. Anything less and the processor is way too slow.␊
126␉␉ */␊
127␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
128␉␉␉continue;␊
129␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
130␉␉if ( (tscEnd - tscStart) < tscDelta )␊
131␉␉␉tscDelta = tscEnd - tscStart;␊
132␉}␊
133␉/* tscDelta is now the least number of TSC ticks the processor made in␊
134␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
135␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
136␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
137␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
138␉ * dividing by the milliseconds, we simply multiply by 1000.␊
139␉ */␊
140␉␊
141␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
142␉ * that we're going to multiply by 1000 first so we do need at least some␊
143␉ * arithmetic headroom. For now, 32-bit should be enough.␊
144␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
145␉ */␊
146␉if (tscDelta > (1ULL<<32))␊
147␉␉retval = 0;␊
148␉else␊
149␉{␊
150␉␉retval = tscDelta * 1000 / 30;␊
151␉}␊
152␉disable_PIT2();␊
153␉return retval;␊
154}␊
155␊
156/*␊
157 * Original comment/code:␊
158 * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊
159 *␊
160 * Measures the Actual Performance Frequency in Hz (64-bit)␊
161 * (just a naming change, mperf --> aperf )␊
162 */␊
163static uint64_t measure_aperf_frequency(void)␊
164{␊
165␉uint64_t aperfStart;␊
166␉uint64_t aperfEnd;␊
167␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊
168␉unsigned long pollCount;␊
169␉uint64_t retval = 0;␊
170␉int i;␊
171␉␊
172␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊
173␉ * counter 2. We run this loop 3 times to make sure the cache␊
174␉ * is hot and we take the minimum delta from all of the runs.␊
175␉ * That is to say that we're biased towards measuring the minimum␊
176␉ * number of APERF ticks that occur while waiting for the timer to␊
177␉ * expire.␊
178␉ */␊
179␉for(i = 0; i < 10; ++i)␊
180␉{␊
181␉␉enable_PIT2();␊
182␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
183␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊
184␉␉pollCount = poll_PIT2_gate();␊
185␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊
186␉␉/* The poll loop must have run at least a few times for accuracy */␊
187␉␉if (pollCount <= 1)␊
188␉␉␉continue;␊
189␉␉/* The TSC must increment at LEAST once every millisecond.␊
190␉␉ * We should have waited exactly 30 msec so the APERF delta should␊
191␉␉ * be >= 30. Anything less and the processor is way too slow.␊
192␉␉ */␊
193␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊
194␉␉␉continue;␊
195␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
196␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊
197␉␉␉aperfDelta = aperfEnd - aperfStart;␊
198␉}␊
199␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊
200␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
201␉ */␊
202␉␊
203␉if (aperfDelta > (1ULL<<32))␊
204␉␉retval = 0;␊
205␉else␊
206␉{␊
207␉␉retval = aperfDelta * 1000 / 30;␊
208␉}␊
209␉disable_PIT2();␊
210␉return retval;␊
211}␊
212␊
213/*␊
214 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
215 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
216 *␉ a max multi. (used to calculate the FSB freq.),␊
217 *␉ and a current multi. (used to calculate the CPU freq.)␊
218 * - fsbFrequency = tscFrequency / multi␊
219 * - cpuFrequency = fsbFrequency * multi␊
220 */␊
221void scan_cpu(PlatformInfo_t *p)␊
222{␊
223␉uint64_t␉tscFrequency = 0;␊
224␉uint64_t␉fsbFrequency = 0;␊
225␉uint64_t␉cpuFrequency =0;␊
226␉uint64_t␉msr = 0;␊
227␉uint64_t␉flex_ratio = 0;␊
228␉uint32_t␉max_ratio = 0;␊
229␉uint32_t␉min_ratio = 0;␊
230␉uint8_t␉␉bus_ratio_max = 0;␊
231␉uint8_t␉␉bus_ratio_min = 0;␊
232␉uint8_t␉␉currdiv = 0;␊
233␉uint8_t␉␉currcoef = 0;␊
234␉uint8_t␉␉maxdiv = 0;␊
235␉uint8_t␉␉maxcoef = 0;␊
236␊
237␉const char␉*newratio;␊
238␉int␉␉len = 0;␊
239␉␊
240␉/* get cpuid values */␊
241␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
242␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
243␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
244␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
245␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
246␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
247␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5) {␉␉␊
248␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); ␉␊
249␉}␉␊
250␉if (p->CPU.CPUID[CPUID_0][0] >= 6) {␊
251␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␉␉␊
252␉}␊
253␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊
254␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
255␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
256␉}␊
257␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
258␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
259␉}␊
260␉␊
261#if DEBUG_CPU␊
262␉{␊
263␉␉int␉␉i;␊
264␉␉printf("CPUID Raw Values:\n");␊
265␉␉for (i=0; i<CPUID_MAX; i++) {␊
266␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
267␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
268␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
269␉␉}␊
270␉}␊
271#endif␊
272␉␊
273␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
274␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
275␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
276␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
277␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
278␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
279␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
280␉␊
281␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
282␉␊
283␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
284␉␉p->CPU.Family == 0x06 &&␊
285␉␉p->CPU.Model >= CPU_MODEL_NEHALEM &&␊
286␉␉p->CPU.Model != CPU_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
287␉␉)␊
288␉{␊
289␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
290␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊
291␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊
292␉}␊
293␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊
294␉{␊
295␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
296␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊
297␉}␊
298␉else␊
299␉{␊
300␉␉// Use previous method for Cores and Threads␊
301␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊
302␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
303␉}␊
304␉␊
305␉/* get brand string (if supported) */␊
306␉/* Copyright: from Apple's XNU cpuid.c */␊
307␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
308␉␉uint32_t␉reg[4];␊
309␉␉char␉␉str[128], *s;␊
310␉␉/*␊
311␉␉ * The brand string 48 bytes (max), guaranteed to␊
312␉␉ * be NULL terminated.␊
313␉␉ */␊
314␉␉do_cpuid(0x80000002, reg);␊
315␉␉bcopy((char *)reg, &str[0], 16);␊
316␉␉do_cpuid(0x80000003, reg);␊
317␉␉bcopy((char *)reg, &str[16], 16);␊
318␉␉do_cpuid(0x80000004, reg);␊
319␉␉bcopy((char *)reg, &str[32], 16);␊
320␉␉for (s = str; *s != '\0'; s++) {␊
321␉␉␉if (*s != ' ') break;␊
322␉␉}␊
323␉␉␊
324␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊
325␉␉␊
326␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
327␉␉␉/*␊
328␉␉␉ * This string means we have a firmware-programmable brand string,␊
329␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
330␉␉␉ */␊
331␉␉␉p->CPU.BrandString[0] = '\0';␊
332␉␉}␊
333␉}␊
334␉␊
335␉/* setup features */␊
336␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
337␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
338␉}␊
339␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
340␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
341␉}␊
342␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
343␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
344␉}␊
345␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
346␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
347␉}␊
348␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
349␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
350␉}␊
351␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊
352␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
353␉}␊
354␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊
355␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
356␉}␊
357␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
358␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
359␉}␊
360␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊
361␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
362␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
363␉}␊
364␉␊
365␉tscFrequency = measure_tsc_frequency();␊
366//␉/* if usual method failed */␊
367//␉if ( tscFrequency < 1000 )␊
368//␉{␊
369//␉tscFrequency = timeRDTSC() * 20;␊
370//␉}␊
371//␉fsbFrequency = 0;␊
372//␉cpuFrequency = 0;␊
373␉␊
374␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
375␉␉int intelCPU = p->CPU.Model;␊
376␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
377␉␉␉/* Nehalem CPU model */␊
378␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM ||␊
379␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS ||␊
380␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES ||␊
381␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM ||␊
382␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE ||␊
383␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX ||␊
384␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
385␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
386␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN ||␊
387␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE )) {␊
388␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
389//␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
390␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
391␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40);␉//MacMan: Changed bitfield to match Apple tsc.c␊
392␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
393//␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
394␉␉␉␉if (bitfield(msr, 16, 16)) {␊
395␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␉//MacMan: Changed bitfield to match Apple tsc.c␊
396␉␉␉␉␉if (flex_ratio == 0) {␊
397␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊
398␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
399␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
400//␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
401␉␉␉␉␉} else {␊
402␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊
403␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
404␉␉␉␉␉␉}␊
405␉␉␉␉␉}␊
406␉␉␉␉}␊
407␉␉␉␉␊
408␉␉␉␉if (bus_ratio_max) {␊
409␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊
410␉␉␉␉}␊
411␉␉␉␉//MacMan: Turbo Ratio Limit␊
412␉␉␉␉switch (intelCPU) ␊
413␉␉␉␉{␊
414␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
415␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
416␉␉␉␉␉{␊
417␉␉␉␉␉␉cpuFrequency = tscFrequency;␊
418␉␉␉␉␉␉DBG("cpu.c (%d)CPU_MODEL_NEHALEM_EX or CPU_MODEL_WESTMERE_EX Found\n", __LINE__);␊
419␉␉␉␉␉␉break;␊
420␉␉␉␉␉}␊
421␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
422␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
423␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
424␉␉␉␉␉{␊
425␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
426␉␉␉␉␉␉currcoef = bitfield(msr, 15, 8);␊
427␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
428␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
429␉␉␉␉␉␉break;␊
430␉␉␉␉␉}␊
431␉␉␉␉␉default:␊
432␉␉␉␉␉{␊
433␉␉␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
434␉␉␉␉␉␉currcoef = bitfield(msr, 7, 0);␊
435␉␉␉␉␉␉cpuFrequency = currcoef * fsbFrequency;␊
436␉␉␉␉␉␉maxcoef = bus_ratio_max;␊
437␉␉␉␉␉␉break;␊
438␉␉␉␉␉}␊
439␉␉␉␉}␊
440␊
441␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊
442␉␉␉␉␉max_ratio = atoi(newratio);␊
443␉␉␉␉␉max_ratio = (max_ratio * 10);␊
444␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊
445␉␉␉␉␉␊
446␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
447␉␉␉␉␉␊
448␉␉␉␉␉// extreme overclockers may love 320 ;)␊
449␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊
450␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊
451␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊
452␉␉␉␉␉␉else maxdiv = 0;␊
453␉␉␉␉␉} else {␊
454␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
455␉␉␉␉␉}␊
456␉␉␉␉}␊
457␉␉␉␉p->CPU.MaxRatio = bus_ratio_max;␊
458␉␉␉␉p->CPU.MinRatio = bus_ratio_min;␊
459␉␉␉} else {␊
460␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
461␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
462␉␉␉␉currcoef = bitfield(msr, 12, 8);␊
463␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
464␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
465␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
466␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
467␉␉␉␉␊
468␉␉␉␉// This will always be model >= 3␊
469␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
470␉␉␉␉{␊
471␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
472␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
473␉␉␉␉} else {␊
474␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
475␉␉␉␉␉/* XXX */␊
476␉␉␉␉␉maxcoef = currcoef;␊
477␉␉␉␉}␊
478␉␉␉␉␊
479␉␉␉␉if (maxcoef) {␊
480␉␉␉␉␉if (maxdiv) {␊
481␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
482␉␉␉␉␉} else {␊
483␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
484␉␉␉␉␉}␊
485␉␉␉␉␉if (currdiv) {␊
486␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
487␉␉␉␉␉} else {␊
488␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
489␉␉␉␉␉}␊
490␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
491␉␉␉␉}␊
492␉␉␉}␊
493␉␉}␊
494␉␉/* Mobile CPU */␊
495␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊
496␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
497␉␉}␊
498␉}␊
499␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊
500␉{␊
501␉␉switch(p->CPU.ExtFamily)␊
502␉␉{␊
503␉␉␉case 0x00: /* K8 */␊
504␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
505␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊
506␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊
507␉␉␉␉break;␊
508␉␉␉␉␊
509␉␉␉case 0x01: /* K10 */␊
510␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
511␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊
512␉␉␉␉// EffFreq: effective frequency interface␊
513␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊
514␉␉␉␉{␊
515␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊
516␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊
517␉␉␉␉␉cpuFrequency = aperf;␊
518␉␉␉␉}␊
519␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊
520␉␉␉␉//␉␉␉*not* at the turbo frequency.␊
521␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊
522␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊
523␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊
524␉␉␉␉␊
525␉␉␉␉break;␊
526␉␉␉␉␊
527␉␉␉case 0x05: /* K14 */␊
528␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
529␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊
530␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊
531␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
532␉␉␉␉␊
533␉␉␉␉break;␊
534␉␉␉␉␊
535␉␉␉case 0x02: /* K11 */␊
536␉␉␉␉// not implimented␊
537␉␉␉␉break;␊
538␉␉}␊
539␉␉␊
540␉␉if (maxcoef)␊
541␉␉{␊
542␉␉␉if (currdiv)␊
543␉␉␉{␊
544␉␉␉␉if (!currcoef) currcoef = maxcoef;␊
545␉␉␉␉if (!cpuFrequency)␊
546␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
547␉␉␉␉else␊
548␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊
549␉␉␉␉␊
550␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
551␉␉␉} else {␊
552␉␉␉␉if (!cpuFrequency)␊
553␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
554␉␉␉␉else ␊
555␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊
556␉␉␉␉DBG("%d\n", currcoef);␊
557␉␉␉}␊
558␉␉}␊
559␉␉else if (currcoef)␊
560␉␉{␊
561␉␉␉if (currdiv)␊
562␉␉␉{␊
563␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
564␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
565␉␉␉} else {␊
566␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
567␉␉␉␉DBG("%d\n", currcoef);␊
568␉␉␉}␊
569␉␉}␊
570␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊
571␉}␊
572␉␊
573#if 0␊
574␉if (!fsbFrequency) {␊
575␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
576␉␉cpuFrequency = tscFrequency;␊
577␉␉DBG("0 ! using the default value for FSB !\n");␊
578␉}␊
579#endif␊
580␉␊
581␉p->CPU.MaxCoef = maxcoef;␊
582␉if (maxdiv == 0){␊
583␉␉p->CPU.MaxDiv = bus_ratio_max;␊
584␉}␊
585␉else {␊
586␉␉p->CPU.MaxDiv = maxdiv;␊
587␉}␊
588␉p->CPU.CurrCoef = currcoef;␊
589␉if (currdiv == 0){␊
590␉␉p->CPU.CurrDiv = currcoef;␊
591␉}␊
592␉else {␊
593␉␉p->CPU.CurrDiv = currdiv;␊
594␉}␊
595␉p->CPU.TSCFrequency = tscFrequency;␊
596␉p->CPU.FSBFrequency = fsbFrequency;␊
597␉p->CPU.CPUFrequency = cpuFrequency;␊
598␉␊
599␉// keep formatted with spaces instead of tabs␊
600␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊
601␉DBG("CPU: Vendor: 0x%x\n",␉␉␉␉ p->CPU.Vendor);␊
602␉DBG("CPU: Family / ExtFamily: 0x%x / 0x%x\n",␉␉ p->CPU.Family, p->CPU.ExtFamily);␊
603␉DBG("CPU: Model / ExtModel / Stepping: 0x%x / 0x%x / 0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
604␉DBG("CPU: Number of Cores / Threads: %d / %d\n", p->CPU.NoCores, p->CPU.NoThreads);␊
605␉DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊
606␉DBG("CPU: TSC Frequency: %d MHz\n", p->CPU.TSCFrequency / 1000000);␊
607␉DBG("CPU: FSB Frequency: %d MHz\n", p->CPU.FSBFrequency / 1000000);␊
608␉DBG("CPU: CPU Frequency: %d MHz\n", p->CPU.CPUFrequency / 1000000);␊
609␉DBG("CPU: Minimum Bus Ratio: %d\n", p->CPU.MinRatio);␊
610␉DBG("CPU: Maximum Bus Ratio: %d\n", p->CPU.MaxRatio);␊
611␉DBG("CPU: Current Bus Ratio: %d\n", p->CPU.CurrCoef);␊
612//␉DBG("CPU: Maximum Multiplier: %d\n",␉␉␉␉ p->CPU.MaxCoef);␊
613//␉DBG("CPU: Maximum Divider: %d\n",␉␉␉␉ p->CPU.MaxDiv);␊
614//␉DBG("CPU: Current Divider: %d\n",␉␉␉␉ p->CPU.CurrDiv);␊
615␊
616#if DEBUG_CPU␊
617␉pause();␊
618#endif␊
619}␊
620

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