1 | /*␊ |
2 | *␉NVidia injector␊ |
3 | *␊ |
4 | *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊ |
5 | *␊ |
6 | *␉NVidia injector modified by Fabio (ErmaC) on May 2012,␊ |
7 | *␉for allow the cosmetics injection also based on SubVendorID and SubDeviceID.␊ |
8 | *␊ |
9 | *␉NVidia injector is free software: you can redistribute it and/or modify␊ |
10 | *␉it under the terms of the GNU General Public License as published by␊ |
11 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
12 | *␉(at your option) any later version.␊ |
13 | *␊ |
14 | *␉NVidia driver and injector is distributed in the hope that it will be useful,␊ |
15 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
16 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
17 | *␉GNU General Public License for more details.␊ |
18 | *␊ |
19 | *␉You should have received a copy of the GNU General Public License␊ |
20 | *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊ |
21 | *␊ |
22 | *␉Alternatively you can choose to comply with APSL␊ |
23 | *␊ |
24 | *␉DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊ |
25 | *␊ |
26 | *␊ |
27 | *␉Copyright 2005-2006 Erik Waling␊ |
28 | *␉Copyright 2006 Stephane Marchesin␊ |
29 | *␉Copyright 2007-2009 Stuart Bennett␊ |
30 | *␊ |
31 | *␉Permission is hereby granted, free of charge, to any person obtaining a␊ |
32 | *␉copy of this software and associated documentation files (the "Software"),␊ |
33 | *␉to deal in the Software without restriction, including without limitation␊ |
34 | *␉the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
35 | *␉and/or sell copies of the Software, and to permit persons to whom the␊ |
36 | *␉Software is furnished to do so, subject to the following conditions:␊ |
37 | *␊ |
38 | *␉The above copyright notice and this permission notice shall be included in␊ |
39 | *␉all copies or substantial portions of the Software.␊ |
40 | *␊ |
41 | *␉THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊ |
42 | *␉IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊ |
43 | *␉FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊ |
44 | *␉THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊ |
45 | *␉WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊ |
46 | *␉OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊ |
47 | *␉SOFTWARE.␊ |
48 | */␊ |
49 | ␊ |
50 | #include "boot.h"␊ |
51 | #include "bootstruct.h"␊ |
52 | #include "pci.h"␊ |
53 | #include "platform.h"␊ |
54 | #include "device_inject.h"␊ |
55 | #include "nvidia.h"␊ |
56 | #include "nvidia_helper.h"␊ |
57 | ␊ |
58 | #ifndef DEBUG_NVIDIA␊ |
59 | #define DEBUG_NVIDIA 0␊ |
60 | #endif␊ |
61 | ␊ |
62 | #if DEBUG_NVIDIA␊ |
63 | #define DBG(x...)␉printf(x)␊ |
64 | #else␊ |
65 | #define DBG(x...)␊ |
66 | #endif␊ |
67 | ␊ |
68 | #define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊ |
69 | #define PATCH_ROM_SUCCESS␉␉␉1␊ |
70 | #define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊ |
71 | #define PATCH_ROM_FAILED␉␉␉0␊ |
72 | #define MAX_NUM_DCB_ENTRIES␉␉␉16␊ |
73 | #define TYPE_GROUPED␉␉␉␉0xff␊ |
74 | #define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))␊ |
75 | #define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))␊ |
76 | #define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))␊ |
77 | #define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))␊ |
78 | #define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))␊ |
79 | ␊ |
80 | extern uint32_t devices_number;␊ |
81 | ␊ |
82 | const char *nvidia_compatible_0[] =␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊ |
83 | const char *nvidia_compatible_1[] =␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊ |
84 | const char *nvidia_device_type_0[] =␉{ "@0,device_type",␉"display"␉ };␊ |
85 | const char *nvidia_device_type_1[] =␉{ "@1,device_type",␉"display"␉ };␊ |
86 | const char *nvidia_device_type[] =␉{ "device_type",␉"NVDA,Parent"␉ };␊ |
87 | const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊ |
88 | const char *nvidia_name_0[] =␉{ "@0,name",␉␉"NVDA,Display-A" };␊ |
89 | const char *nvidia_name_1[] =␉{ "@1,name",␉␉"NVDA,Display-B" };␊ |
90 | const char *nvidia_slot_name[] =␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊ |
91 | ␊ |
92 | static uint8_t default_NVCAP[]= {␊ |
93 | ␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊ |
94 | ␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊ |
95 | ␉0x00, 0x00, 0x00, 0x00␊ |
96 | };␊ |
97 | ␊ |
98 | #define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊ |
99 | ␊ |
100 | static uint8_t default_dcfg_0[]␉␉=␉{0x03, 0x01, 0x03, 0x00};␊ |
101 | static uint8_t default_dcfg_1[]␉␉=␉{0xff, 0xff, 0x00, 0x01};␊ |
102 | ␊ |
103 | #define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )␊ |
104 | #define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )␊ |
105 | ␊ |
106 | static uint8_t default_NVPM[]= {␊ |
107 | ␉0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
108 | ␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
109 | ␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,␊ |
110 | ␉0x00, 0x00, 0x00, 0x00␊ |
111 | };␊ |
112 | ␊ |
113 | #define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )␊ |
114 | ␊ |
115 | static nvidia_card_info_t nvidia_cards[] = {␊ |
116 | /* ========================================================================================␊ |
117 | * Layout is device(VendorId + DeviceId), subdev (SubvendorId + SubdeviceId), display name.␊ |
118 | * ========================================================================================␊ |
119 | */␊ |
120 | ␉/*Unknown*/␉{ 0x10DE0000,␉NV_SUB_IDS,␉"Unknown" },␊ |
121 | /* ------ Specific DeviceID and SubDevID. ------ */␊ |
122 | ␉// 0000 - 0040␊ |
123 | ␉// 0040 - 004F␊ |
124 | ␉{ 0x10DE0040, NV_SUB_IDS, "GeForce 6800 Ultra" },␊ |
125 | ␉{ 0x10DE0041,␉NV_SUB_IDS, "GeForce 6800" },␊ |
126 | ␉{ 0x10DE0042,␉NV_SUB_IDS, "GeForce 6800 LE" },␊ |
127 | ␉{ 0x10DE0043,␉NV_SUB_IDS, "GeForce 6800 XE" },␊ |
128 | ␉{ 0x10DE0044,␉NV_SUB_IDS, "GeForce 6800 XT" },␊ |
129 | ␉{ 0x10DE0045,␉NV_SUB_IDS, "GeForce 6800 GT" },␊ |
130 | ␉{ 0x10DE0046,␉NV_SUB_IDS, "GeForce 6800 GT" },␊ |
131 | ␉{ 0x10DE0047,␉NV_SUB_IDS, "GeForce 6800 GS" },␊ |
132 | ␉{ 0x10DE0048,␉NV_SUB_IDS, "GeForce 6800 XT" },␊ |
133 | ␉{ 0x10DE004D,␉NV_SUB_IDS, "Quadro FX 3400" },␊ |
134 | ␉{ 0x10DE004E,␉NV_SUB_IDS, "Quadro FX 4000" },␊ |
135 | ␉// 0050 - 005F␊ |
136 | ␉// 0060 - 006F␊ |
137 | ␉// 0070 - 007F␊ |
138 | ␉// 0080 - 008F␊ |
139 | ␉// 0090 - 009F␊ |
140 | ␉{ 0x10DE0090,␉NV_SUB_IDS, "GeForce 7800 GTX" },␊ |
141 | ␉{ 0x10DE0091,␉NV_SUB_IDS, "GeForce 7800 GTX" },␊ |
142 | ␉{ 0x10DE0092,␉NV_SUB_IDS, "GeForce 7800 GT" },␊ |
143 | ␉{ 0x10DE0093,␉NV_SUB_IDS, "GeForce 7800 GS" },␊ |
144 | ␉{ 0x10DE0095,␉NV_SUB_IDS, "GeForce 7800 SLI" },␊ |
145 | ␉{ 0x10DE0098,␉NV_SUB_IDS, "GeForce Go 7800" },␊ |
146 | ␉{ 0x10DE0099,␉NV_SUB_IDS, "GeForce Go 7800 GTX" },␊ |
147 | ␉{ 0x10DE009D,␉NV_SUB_IDS, "Quadro FX 4500" },␊ |
148 | ␉// 00A0 - 00AF␊ |
149 | ␉// 00B0 - 00BF␊ |
150 | ␉// 00C0 - 00CF␊ |
151 | ␉{ 0x10DE00C0,␉NV_SUB_IDS, "GeForce 6800 GS" },␊ |
152 | ␉{ 0x10DE00C1,␉NV_SUB_IDS, "GeForce 6800" },␊ |
153 | ␉{ 0x10DE00C2,␉NV_SUB_IDS, "GeForce 6800 LE" },␊ |
154 | ␉{ 0x10DE00C3,␉NV_SUB_IDS, "GeForce 6800 XT" },␊ |
155 | ␉{ 0x10DE00C8,␉NV_SUB_IDS, "GeForce Go 6800" },␊ |
156 | ␉{ 0x10DE00C9,␉NV_SUB_IDS, "GeForce Go 6800 Ultra" },␊ |
157 | ␉{ 0x10DE00CC,␉NV_SUB_IDS, "Quadro FX Go1400" },␊ |
158 | ␉{ 0x10DE00CD,␉NV_SUB_IDS, "Quadro FX 3450/4000 SDI" },␊ |
159 | ␉{ 0x10DE00CE,␉NV_SUB_IDS, "Quadro FX 1400" },␊ |
160 | ␉// 00D0 - 00DF␊ |
161 | ␉// 00E0 - 00EF␊ |
162 | ␉// 00F0 - 00FF␊ |
163 | ␉{ 0x10DE00F1,␉NV_SUB_IDS, "GeForce 6600 GT" },␊ |
164 | ␉{ 0x10DE00F2,␉NV_SUB_IDS, "GeForce 6600" },␊ |
165 | ␉{ 0x10DE00F3,␉NV_SUB_IDS, "GeForce 6200" },␊ |
166 | ␉{ 0x10DE00F4,␉NV_SUB_IDS, "GeForce 6600 LE" },␊ |
167 | ␉{ 0x10DE00F5,␉NV_SUB_IDS, "GeForce 7800 GS" },␊ |
168 | ␉{ 0x10DE00F6,␉NV_SUB_IDS, "GeForce 6800 GS/XT" },␊ |
169 | ␉{ 0x10DE00F8,␉NV_SUB_IDS, "Quadro FX 3400/4400" },␊ |
170 | ␉{ 0x10DE00F9,␉NV_SUB_IDS, "GeForce 6800 Series GPU" },␊ |
171 | ␉// 0100 - 010F␊ |
172 | ␉// 0110 - 011F␊ |
173 | ␉// 0120 - 012F␊ |
174 | ␉// 0130 - 013F␊ |
175 | ␉// 0140 - 014F␊ |
176 | ␉{ 0x10DE0140, NV_SUB_IDS, "GeForce 6600 GT" },␊ |
177 | ␉{ 0x10DE0141,␉NV_SUB_IDS, "GeForce 6600" },␊ |
178 | ␉{ 0x10DE0142,␉NV_SUB_IDS, "GeForce 6600 LE" },␊ |
179 | ␉{ 0x10DE0143,␉NV_SUB_IDS, "GeForce 6600 VE" },␊ |
180 | ␉{ 0x10DE0144,␉NV_SUB_IDS, "GeForce Go 6600" },␊ |
181 | ␉{ 0x10DE0145,␉NV_SUB_IDS, "GeForce 6610 XL" },␊ |
182 | ␉{ 0x10DE0146,␉NV_SUB_IDS, "GeForce Go 6600 TE/6200 TE" },␊ |
183 | ␉{ 0x10DE0147,␉NV_SUB_IDS, "GeForce 6700 XL" },␊ |
184 | ␉{ 0x10DE0148,␉NV_SUB_IDS, "GeForce Go 6600" },␊ |
185 | ␉{ 0x10DE0149,␉NV_SUB_IDS, "GeForce Go 6600 GT" },␊ |
186 | ␉{ 0x10DE014A,␉NV_SUB_IDS, "Quadro NVS 440" },␊ |
187 | ␉{ 0x10DE014C,␉NV_SUB_IDS, "Quadro FX 550" },␊ |
188 | ␉{ 0x10DE014D,␉NV_SUB_IDS, "Quadro FX 550" },␊ |
189 | ␉{ 0x10DE014E,␉NV_SUB_IDS, "Quadro FX 540" },␊ |
190 | ␉{ 0x10DE014F,␉NV_SUB_IDS, "GeForce 6200" },␊ |
191 | ␉// 0150 - 015F␊ |
192 | ␉// 0160 - 016F␊ |
193 | ␉{ 0x10DE0160,␉NV_SUB_IDS, "GeForce 6500" },␊ |
194 | ␉{ 0x10DE0161,␉NV_SUB_IDS, "GeForce 6200 TurboCache(TM)" },␊ |
195 | ␉{ 0x10DE0162,␉NV_SUB_IDS, "GeForce 6200SE TurboCache(TM)" },␊ |
196 | ␉{ 0x10DE0163,␉NV_SUB_IDS, "GeForce 6200 LE" },␊ |
197 | ␉{ 0x10DE0164,␉NV_SUB_IDS, "GeForce Go 6200" },␊ |
198 | ␉{ 0x10DE0165,␉NV_SUB_IDS, "Quadro NVS 285" },␊ |
199 | ␉{ 0x10DE0166,␉NV_SUB_IDS, "GeForce Go 6400" },␊ |
200 | ␉{ 0x10DE0167,␉NV_SUB_IDS, "GeForce Go 6200" },␊ |
201 | ␉{ 0x10DE0168,␉NV_SUB_IDS, "GeForce Go 6400" },␊ |
202 | ␉{ 0x10DE0169,␉NV_SUB_IDS, "GeForce 6250" },␊ |
203 | ␉{ 0x10DE016A,␉NV_SUB_IDS, "GeForce 7100 GS" },␊ |
204 | ␉// 0170 - 017F␊ |
205 | ␉// 0180 - 018F␊ |
206 | ␉// 0190 - 019F␊ |
207 | ␉{ 0x10DE0191,␉NV_SUB_IDS, "GeForce 8800 GTX" },␊ |
208 | ␉{ 0x10DE0193,␉NV_SUB_IDS, "GeForce 8800 GTS" },␊ |
209 | ␉{ 0x10DE0194,␉NV_SUB_IDS, "GeForce 8800 Ultra" },␊ |
210 | ␉{ 0x10DE0197,␉NV_SUB_IDS, "Tesla C870" },␊ |
211 | ␉{ 0x10DE019D,␉NV_SUB_IDS, "Quadro FX 5600" },␊ |
212 | ␉{ 0x10DE019E,␉NV_SUB_IDS, "Quadro FX 4600" },␊ |
213 | ␉// 01A0 - 01AF␊ |
214 | ␉// 01B0 - 01BF␊ |
215 | ␉// 01C0 - 01CF␊ |
216 | ␉// 01D0 - 01DF␊ |
217 | ␉{ 0x10DE01D0,␉NV_SUB_IDS, "GeForce 7350 LE" },␊ |
218 | ␉{ 0x10DE01D1,␉NV_SUB_IDS, "GeForce 7300 LE" },␊ |
219 | ␉{ 0x10DE01D2,␉NV_SUB_IDS, "GeForce 7550 LE" },␊ |
220 | ␉{ 0x10DE01D3,␉NV_SUB_IDS, "GeForce 7300 SE/7200 GS" },␊ |
221 | ␉{ 0x10DE01D6,␉NV_SUB_IDS, "GeForce Go 7200" },␊ |
222 | ␉{ 0x10DE01D7,␉NV_SUB_IDS, "GeForce Go 7300" },␊ |
223 | ␉{ 0x10DE01D8,␉NV_SUB_IDS, "GeForce Go 7400" },␊ |
224 | ␉{ 0x10DE01D9,␉NV_SUB_IDS, "GeForce Go 7400 GS" },␊ |
225 | ␉{ 0x10DE01DA,␉NV_SUB_IDS, "Quadro NVS 110M" },␊ |
226 | ␉{ 0x10DE01DB,␉NV_SUB_IDS, "Quadro NVS 120M" },␊ |
227 | ␉{ 0x10DE01DC,␉NV_SUB_IDS, "Quadro FX 350M" },␊ |
228 | ␉{ 0x10DE01DD,␉NV_SUB_IDS, "GeForce 7500 LE" },␊ |
229 | ␉{ 0x10DE01DE,␉NV_SUB_IDS, "Quadro FX 350" },␊ |
230 | ␉{ 0x10DE01DF,␉NV_SUB_IDS, "GeForce 7300 GS" },␊ |
231 | ␉// 01E0 - 01EF␊ |
232 | ␉// 01F0 - 01FF␊ |
233 | ␉// 0200 - 020F␊ |
234 | ␉// 0210 - 021F␊ |
235 | ␉{ 0x10DE0211,␉NV_SUB_IDS, "GeForce 6800" },␊ |
236 | ␉{ 0x10DE0212,␉NV_SUB_IDS, "GeForce 6800 LE" },␊ |
237 | ␉{ 0x10DE0215,␉NV_SUB_IDS, "GeForce 6800 GT" },␊ |
238 | ␉{ 0x10DE0218,␉NV_SUB_IDS, "GeForce 6800 XT" },␊ |
239 | ␉// 0220 - 022F␊ |
240 | ␉{ 0x10DE0221,␉NV_SUB_IDS, "GeForce 6200" },␊ |
241 | ␉{ 0x10DE0222,␉NV_SUB_IDS, "GeForce 6200 A-LE" },␊ |
242 | ␉// 0230 - 023F␊ |
243 | ␉// 0240 - 024F␊ |
244 | ␉{ 0x10DE0240,␉NV_SUB_IDS, "GeForce 6150" },␊ |
245 | ␉{ 0x10DE0241,␉NV_SUB_IDS, "GeForce 6150 LE" },␊ |
246 | ␉{ 0x10DE0242,␉NV_SUB_IDS, "GeForce 6100" },␊ |
247 | ␉{ 0x10DE0244,␉NV_SUB_IDS, "GeForce Go 6150" },␊ |
248 | ␉{ 0x10DE0245,␉NV_SUB_IDS, "Quadro NVS 210S / GeForce 6150LE" },␊ |
249 | ␉{ 0x10DE0247,␉NV_SUB_IDS, "GeForce Go 6100" },␊ |
250 | ␉// 0250 - 025F␊ |
251 | ␉// 0260 - 026F␊ |
252 | ␉// 0270 - 027F␊ |
253 | ␉// 0280 - 028F␊ |
254 | ␉// 0290 - 029F␊ |
255 | ␉{ 0x10DE0290,␉NV_SUB_IDS, "GeForce 7900 GTX" },␊ |
256 | ␉{ 0x10DE0291,␉NV_SUB_IDS, "GeForce 7900 GT/GTO" },␊ |
257 | ␉{ 0x10DE0292,␉NV_SUB_IDS, "GeForce 7900 GS" },␊ |
258 | ␉{ 0x10DE0293,␉NV_SUB_IDS, "GeForce 7950 GX2" },␊ |
259 | ␉{ 0x10DE0294,␉NV_SUB_IDS, "GeForce 7950 GX2" },␊ |
260 | ␉{ 0x10DE0295,␉NV_SUB_IDS, "GeForce 7950 GT" },␊ |
261 | ␉{ 0x10DE0298,␉NV_SUB_IDS, "GeForce Go 7900 GS" },␊ |
262 | ␉{ 0x10DE0299,␉NV_SUB_IDS, "Quadro NVS 510M" },␊ |
263 | ␉{ 0x10DE029A,␉NV_SUB_IDS, "Quadro FX 2500M" },␊ |
264 | ␉{ 0x10DE029B,␉NV_SUB_IDS, "Quadro FX 1500M" },␊ |
265 | ␉{ 0x10DE029C,␉NV_SUB_IDS, "Quadro FX 5500" },␊ |
266 | ␉{ 0x10DE029D,␉NV_SUB_IDS, "Quadro FX 3500" },␊ |
267 | ␉{ 0x10DE029E,␉NV_SUB_IDS, "Quadro FX 1500" },␊ |
268 | ␉{ 0x10DE029F,␉NV_SUB_IDS, "Quadro FX 4500 X2" },␊ |
269 | ␉// 02A0 - 02AF␊ |
270 | ␉// 02B0 - 02BF␊ |
271 | ␉// 02C0 - 02CF␊ |
272 | ␉// 02D0 - 02DF␊ |
273 | ␉// 02E0 - 02EF␊ |
274 | ␉{ 0x10DE02E0,␉NV_SUB_IDS, "GeForce 7600 GT" },␊ |
275 | ␉{ 0x10DE02E1,␉NV_SUB_IDS, "GeForce 7600 GS" },␊ |
276 | ␉{ 0x10DE02E2,␉NV_SUB_IDS, "GeForce 7300 GT" },␊ |
277 | ␉{ 0x10DE02E3,␉NV_SUB_IDS, "GeForce 7900 GS" },␊ |
278 | ␉{ 0x10DE02E4,␉NV_SUB_IDS, "GeForce 7950 GT" },␊ |
279 | ␉// 02F0 - 02FF␊ |
280 | ␉// 0300 - 030F␊ |
281 | ␉{ 0x10DE0301,␉NV_SUB_IDS, "GeForce FX 5800 Ultra" },␊ |
282 | ␉{ 0x10DE0302,␉NV_SUB_IDS, "GeForce FX 5800" },␊ |
283 | ␉{ 0x10DE0308,␉NV_SUB_IDS, "Quadro FX 2000" },␊ |
284 | ␉{ 0x10DE0309,␉NV_SUB_IDS, "Quadro FX 1000" },␊ |
285 | ␉// 0310 - 031F␊ |
286 | ␉{ 0x10DE0311,␉NV_SUB_IDS, "GeForce FX 5600 Ultra" },␊ |
287 | ␉{ 0x10DE0312,␉NV_SUB_IDS, "GeForce FX 5600" },␊ |
288 | ␉{ 0x10DE0314,␉NV_SUB_IDS, "GeForce FX 5600XT" },␊ |
289 | ␉{ 0x10DE031A,␉NV_SUB_IDS, "GeForce FX Go5600" },␊ |
290 | ␉{ 0x10DE031B,␉NV_SUB_IDS, "GeForce FX Go5650" },␊ |
291 | ␉{ 0x10DE031C,␉NV_SUB_IDS, "Quadro FX Go700" },␊ |
292 | ␉// 0320 - 032F␊ |
293 | { 0x10DE0320,␉NV_SUB_IDS, "GeForce FX 5200" },␊ |
294 | ␉{ 0x10DE0321,␉NV_SUB_IDS, "GeForce FX 5200 Ultra" },␊ |
295 | ␉{ 0x10DE0322,␉NV_SUB_IDS, "GeForce FX 5200" },␊ |
296 | ␉{ 0x10DE0323,␉NV_SUB_IDS, "GeForce FX 5200 LE" },␊ |
297 | ␉{ 0x10DE0324,␉NV_SUB_IDS, "GeForce FX Go5200" },␊ |
298 | ␉{ 0x10DE0325,␉NV_SUB_IDS, "GeForce FX Go5250" },␊ |
299 | ␉{ 0x10DE0326,␉NV_SUB_IDS, "GeForce FX 5500" },␊ |
300 | ␉{ 0x10DE0328,␉NV_SUB_IDS, "GeForce FX Go5200 32M/64M" },␊ |
301 | { 0x10DE0329,␉NV_SUB_IDS, "GeForce FX Go5200" },␊ |
302 | ␉{ 0x10DE032A,␉NV_SUB_IDS, "Quadro NVS 55/280 PCI" },␊ |
303 | ␉{ 0x10DE032B,␉NV_SUB_IDS, "Quadro FX 500/600 PCI" },␊ |
304 | ␉{ 0x10DE032C,␉NV_SUB_IDS, "GeForce FX Go53xx Series" },␊ |
305 | ␉{ 0x10DE032D,␉NV_SUB_IDS, "GeForce FX Go5100" },␊ |
306 | ␉// 0330 - 033F␊ |
307 | ␉{ 0x10DE0330,␉NV_SUB_IDS, "GeForce FX 5900 Ultra" },␊ |
308 | ␉{ 0x10DE0331,␉NV_SUB_IDS, "GeForce FX 5900" },␊ |
309 | ␉{ 0x10DE0332,␉NV_SUB_IDS, "GeForce FX 5900XT" },␊ |
310 | ␉{ 0x10DE0333,␉NV_SUB_IDS, "GeForce FX 5950 Ultra" },␊ |
311 | ␉{ 0x10DE0334,␉NV_SUB_IDS, "GeForce FX 5900ZT" },␊ |
312 | ␉{ 0x10DE0338,␉NV_SUB_IDS, "Quadro FX 3000" },␊ |
313 | ␉{ 0x10DE033F,␉NV_SUB_IDS, "Quadro FX 700" },␊ |
314 | ␉// 0340 - 034F␊ |
315 | ␉{ 0x10DE0341,␉NV_SUB_IDS, "GeForce FX 5700 Ultra" },␊ |
316 | ␉{ 0x10DE0342,␉NV_SUB_IDS, "GeForce FX 5700" },␊ |
317 | ␉{ 0x10DE0343,␉NV_SUB_IDS, "GeForce FX 5700LE" },␊ |
318 | ␉{ 0x10DE0344,␉NV_SUB_IDS, "GeForce FX 5700VE" },␊ |
319 | ␉{ 0x10DE0347,␉NV_SUB_IDS, "GeForce FX Go5700" },␊ |
320 | ␉{ 0x10DE0348, ␉NV_SUB_IDS,␉"GeForce FX Go5700" },␊ |
321 | ␉{ 0x10DE034C,␉NV_SUB_IDS, "Quadro FX Go1000" },␊ |
322 | ␉{ 0x10DE034E,␉NV_SUB_IDS, "Quadro FX 1100" },␊ |
323 | ␉// 0350 - 035F␊ |
324 | ␉// 0360 - 036F␊ |
325 | ␉// 0370 - 037F␊ |
326 | ␉// 0380 - 038F␊ |
327 | ␉{ 0x10DE038B,␉NV_SUB_IDS, "GeForce 7650 GS" },␊ |
328 | ␉// 0390 - 039F␊ |
329 | ␉{ 0x10DE0390,␉NV_SUB_IDS, "GeForce 7650 GS" },␊ |
330 | ␉{ 0x10DE0391,␉NV_SUB_IDS, "GeForce 7600 GT" },␊ |
331 | ␉{ 0x10DE0392,␉NV_SUB_IDS, "GeForce 7600 GS" },␊ |
332 | ␉{ 0x10DE0393,␉NV_SUB_IDS, "GeForce 7300 GT" },␊ |
333 | ␉{ 0x10DE0394,␉NV_SUB_IDS, "GeForce 7600 LE" },␊ |
334 | ␉{ 0x10DE0395,␉NV_SUB_IDS, "GeForce 7300 GT" },␊ |
335 | ␉{ 0x10DE0397,␉NV_SUB_IDS, "GeForce Go 7700" },␊ |
336 | ␉{ 0x10DE0398,␉NV_SUB_IDS, "GeForce Go 7600" },␊ |
337 | ␉{ 0x10DE0399,␉NV_SUB_IDS, "GeForce Go 7600 GT"},␊ |
338 | ␉{ 0x10DE039A,␉NV_SUB_IDS, "Quadro NVS 300M" },␊ |
339 | ␉{ 0x10DE039B,␉NV_SUB_IDS, "GeForce Go 7900 SE" },␊ |
340 | ␉{ 0x10DE039C,␉NV_SUB_IDS, "Quadro FX 550M" },␊ |
341 | ␉{ 0x10DE039E,␉NV_SUB_IDS, "Quadro FX 560" },␊ |
342 | ␉// 03A0 - 03AF␊ |
343 | ␉// 03B0 - 03BF␊ |
344 | ␉// 03C0 - 03CF␊ |
345 | ␉// 03D0 - 03DF␊ |
346 | ␉{ 0x10DE03D0,␉NV_SUB_IDS, "GeForce 6150SE nForce 430" },␊ |
347 | ␉{ 0x10DE03D1,␉NV_SUB_IDS, "GeForce 6100 nForce 405" },␊ |
348 | ␉{ 0x10DE03D2,␉NV_SUB_IDS, "GeForce 6100 nForce 400" },␊ |
349 | ␉{ 0x10DE03D5,␉NV_SUB_IDS, "GeForce 6100 nForce 420" },␊ |
350 | ␉{ 0x10DE03D6,␉NV_SUB_IDS, "GeForce 7025 / nForce 630a" },␊ |
351 | ␉// 03E0 - 03EF␊ |
352 | ␉// 03F0 - 03FF␊ |
353 | ␉// 0400 - 040F␊ |
354 | ␉{ 0x10DE0400,␉NV_SUB_IDS, "GeForce 8600 GTS" },␊ |
355 | ␉{ 0x10DE0401,␉NV_SUB_IDS, "GeForce 8600 GT" },␊ |
356 | ␉{ 0x10DE0402,␉NV_SUB_IDS, "GeForce 8600 GT" },␊ |
357 | ␉{ 0x10DE0403,␉NV_SUB_IDS, "GeForce 8600 GS" },␊ |
358 | ␉{ 0x10DE0404,␉NV_SUB_IDS, "GeForce 8400 GS" },␊ |
359 | ␉{ 0x10DE0405,␉NV_SUB_IDS, "GeForce 9500M GS" },␊ |
360 | ␉{ 0x10DE0406,␉NV_SUB_IDS, "GeForce 8300 GS" },␊ |
361 | ␉{ 0x10DE0407,␉NV_SUB_IDS, "GeForce 8600M GT" },␊ |
362 | ␉{ 0x10DE0408,␉NV_SUB_IDS, "GeForce 9650M GS" },␊ |
363 | ␉{ 0x10DE0409,␉NV_SUB_IDS, "GeForce 8700M GT" },␊ |
364 | ␉{ 0x10DE040A,␉NV_SUB_IDS, "Quadro FX 370" },␊ |
365 | ␉{ 0x10DE040B,␉NV_SUB_IDS, "Quadro NVS 320M" },␊ |
366 | ␉{ 0x10DE040C,␉NV_SUB_IDS, "Quadro FX 570M" },␊ |
367 | ␉{ 0x10DE040D,␉NV_SUB_IDS, "Quadro FX 1600M" },␊ |
368 | ␉{ 0x10DE040E,␉NV_SUB_IDS, "Quadro FX 570" },␊ |
369 | ␉{ 0x10DE040F,␉NV_SUB_IDS, "Quadro FX 1700" },␊ |
370 | ␉// 0410 - 041F␊ |
371 | ␉{ 0x10DE0410,␉NV_SUB_IDS, "GeForce GT 330" },␊ |
372 | ␉// 0420 - 042F␊ |
373 | ␉{ 0x10DE0420,␉NV_SUB_IDS, "GeForce 8400 SE" },␊ |
374 | ␉{ 0x10DE0421,␉NV_SUB_IDS, "GeForce 8500 GT" },␊ |
375 | ␉{ 0x10DE0422,␉NV_SUB_IDS, "GeForce 8400 GS" },␊ |
376 | ␉{ 0x10DE0423,␉NV_SUB_IDS, "GeForce 8300 GS" },␊ |
377 | ␉{ 0x10DE0424,␉NV_SUB_IDS, "GeForce 8400 GS" },␊ |
378 | ␉{ 0x10DE0425,␉NV_SUB_IDS, "GeForce 8600M GS" },␊ |
379 | ␉{ 0x10DE0426,␉NV_SUB_IDS, "GeForce 8400M GT" },␊ |
380 | ␉{ 0x10DE0427,␉NV_SUB_IDS, "GeForce 8400M GS" },␊ |
381 | ␉{ 0x10DE0428,␉NV_SUB_IDS, "GeForce 8400M G" },␊ |
382 | ␉{ 0x10DE0429,␉NV_SUB_IDS, "Quadro NVS 140M" },␊ |
383 | ␉{ 0x10DE042A,␉NV_SUB_IDS, "Quadro NVS 130M" },␊ |
384 | ␉{ 0x10DE042B,␉NV_SUB_IDS, "Quadro NVS 135M" },␊ |
385 | ␉{ 0x10DE042C,␉NV_SUB_IDS, "GeForce 9400 GT" },␊ |
386 | ␉{ 0x10DE042D,␉NV_SUB_IDS, "Quadro FX 360M" },␊ |
387 | ␉{ 0x10DE042E,␉NV_SUB_IDS, "GeForce 9300M G" },␊ |
388 | ␉{ 0x10DE042F,␉NV_SUB_IDS, "Quadro NVS 290" },␊ |
389 | ␉// 0430 - 043F␊ |
390 | ␉// 0440 - 044F␊ |
391 | ␉// 0450 - 045F␊ |
392 | ␉// 0460 - 046F␊ |
393 | ␉// 0470 - 047F␊ |
394 | ␉// 0480 - 048F␊ |
395 | ␉// 0490 - 049F␊ |
396 | ␉// 04A0 - 04AF␊ |
397 | ␉// 04B0 - 04BF␊ |
398 | ␉// 04C0 - 04CF␊ |
399 | ␉// 04D0 - 04DF␊ |
400 | ␉// 04E0 - 04EF␊ |
401 | ␉// 04F0 - 04FF␊ |
402 | ␉// 0500 - 050F␊ |
403 | ␉// 0510 - 051F␊ |
404 | ␉// 0520 - 052F␊ |
405 | ␉// 0530 - 053F␊ |
406 | { 0x10DE0530,␉NV_SUB_IDS, "GeForce 7190M / nForce 650M" },␊ |
407 | ␉{ 0x10DE0531,␉NV_SUB_IDS, "GeForce 7150M / nForce 630M" },␊ |
408 | ␉{ 0x10DE0533,␉NV_SUB_IDS, "GeForce 7000M / nForce 610M" },␊ |
409 | ␉{ 0x10DE053A,␉NV_SUB_IDS, "GeForce 7050 PV / nForce 630a" },␊ |
410 | ␉{ 0x10DE053B,␉NV_SUB_IDS, "GeForce 7050 PV / nForce 630a" },␊ |
411 | ␉{ 0x10DE053E,␉NV_SUB_IDS, "GeForce 7025 / nForce 630a" },␊ |
412 | ␉// 0540 - 054F␊ |
413 | ␉// 0550 - 055F␊ |
414 | ␉// 0560 - 056F␊ |
415 | ␉// 0570 - 057F␊ |
416 | ␉// 0580 - 058F␊ |
417 | ␉// 0590 - 059F␊ |
418 | ␉// 05A0 - 05AF␊ |
419 | ␉// 05B0 - 05BF␊ |
420 | ␉// 05C0 - 05CF␊ |
421 | ␉// 05D0 - 05DF␊ |
422 | ␉// 05E0 - 05EF␊ |
423 | ␉{ 0x10DE05E0,␉NV_SUB_IDS, "GeForce GTX 295" },␊ |
424 | ␉{ 0x10DE05E1,␉NV_SUB_IDS, "GeForce GTX 280" },␊ |
425 | ␉{ 0x10DE05E2,␉NV_SUB_IDS, "GeForce GTX 260" },␊ |
426 | ␉{ 0x10DE05E3,␉NV_SUB_IDS, "GeForce GTX 285" },␊ |
427 | ␉{ 0x10DE05E6,␉NV_SUB_IDS, "GeForce GTX 275" },␊ |
428 | ␉{ 0x10DE05E7,␉0x10DE0595, "Tesla T10 Processor" },␊ |
429 | ␉{ 0x10DE05E7,␉0x10DE066A,␉"Tesla C1060" },␊ |
430 | ␉{ 0x10DE05E7,␉0x10DE068F,␉"Tesla T10 Processor" },␊ |
431 | ␉{ 0x10DE05E7,␉0x10DE0697,␉"Tesla M1060" },␊ |
432 | ␉{ 0x10DE05E7,␉0x10DE0714,␉"Tesla M1060" },␊ |
433 | ␉{ 0x10DE05E7,␉0x10DE0743,␉"Tesla M1060" },␊ |
434 | ␉{ 0x10DE05EA,␉NV_SUB_IDS, "GeForce GTX 260" },␊ |
435 | ␉{ 0x10DE05EB,␉NV_SUB_IDS, "GeForce GTX 295" },␊ |
436 | ␉{ 0x10DE05ED,␉NV_SUB_IDS, "Quadroplex 2200 D2" },␊ |
437 | ␉// 05F0 - 05FF␊ |
438 | ␉{ 0x10DE05F8,␉NV_SUB_IDS, "Quadroplex 2200 S4" },␊ |
439 | ␉{ 0x10DE05F9,␉NV_SUB_IDS, "Quadro CX" },␊ |
440 | ␉{ 0x10DE05FD,␉NV_SUB_IDS, "Quadro FX 5800" },␊ |
441 | ␉{ 0x10DE05FE,␉NV_SUB_IDS, "Quadro FX 4800" },␊ |
442 | ␉{ 0x10DE05FF,␉NV_SUB_IDS, "Quadro FX 3800" },␊ |
443 | ␉// 0600 - 060F␊ |
444 | ␉{ 0x10DE0600,␉NV_SUB_IDS, "GeForce 8800 GTS 512" },␊ |
445 | ␉{ 0x10DE0601,␉NV_SUB_IDS, "GeForce 9800 GT" },␊ |
446 | ␉{ 0x10DE0602,␉NV_SUB_IDS, "GeForce 8800 GT" },␊ |
447 | ␉{ 0x10DE0603,␉NV_SUB_IDS, "GeForce GT 230" },␊ |
448 | ␉{ 0x10DE0604,␉NV_SUB_IDS, "GeForce 9800 GX2" },␊ |
449 | ␉{ 0x10DE0605,␉NV_SUB_IDS, "GeForce 9800 GT" },␊ |
450 | ␉{ 0x10DE0606,␉NV_SUB_IDS, "GeForce 8800 GS" },␊ |
451 | ␉{ 0x10DE0607,␉NV_SUB_IDS, "GeForce GTS 240" },␊ |
452 | ␉{ 0x10DE0608,␉NV_SUB_IDS, "GeForce 9800M GTX" },␊ |
453 | ␉{ 0x10DE0609,␉NV_SUB_IDS, "GeForce 8800M GTS" },␊ |
454 | ␉{ 0x10DE060A,␉NV_SUB_IDS, "GeForce GTX 280M" },␊ |
455 | ␉{ 0x10DE060B,␉NV_SUB_IDS, "GeForce 9800M GT" },␊ |
456 | ␉{ 0x10DE060C,␉NV_SUB_IDS, "GeForce 8800M GTX" },␊ |
457 | ␉{ 0x10DE060D,␉NV_SUB_IDS, "GeForce 8800 GS" },␊ |
458 | ␉{ 0x10DE060F,␉NV_SUB_IDS, "GeForce GTX 285M" },␊ |
459 | ␉// 0610 - 061F␊ |
460 | ␉{ 0x10DE0610,␉NV_SUB_IDS, "GeForce 9600 GSO" },␊ |
461 | ␉{ 0x10DE0611,␉NV_SUB_IDS, "GeForce 8800 GT" },␊ |
462 | ␉{ 0x10DE0612,␉NV_SUB_IDS, "GeForce 9800 GTX" },␊ |
463 | ␉{ 0x10DE0613,␉NV_SUB_IDS, "GeForce 9800 GTX+" },␊ |
464 | ␉{ 0x10DE0614,␉NV_SUB_IDS, "GeForce 9800 GT" },␊ |
465 | ␉{ 0x10DE0615,␉NV_SUB_IDS, "GeForce GTS 250" },␊ |
466 | ␉{ 0x10DE0617,␉NV_SUB_IDS, "GeForce 9800M GTX" },␊ |
467 | ␉{ 0x10DE0618,␉NV_SUB_IDS, "GeForce GTX 260M" },␊ |
468 | ␉{ 0x10DE0619,␉NV_SUB_IDS, "Quadro FX 4700 X2" },␊ |
469 | ␉{ 0x10DE061A,␉NV_SUB_IDS, "Quadro FX 3700" },␊ |
470 | ␉{ 0x10DE061B,␉NV_SUB_IDS, "Quadro VX 200" },␊ |
471 | ␉{ 0x10DE061C,␉NV_SUB_IDS, "Quadro FX 3600M" },␊ |
472 | ␉{ 0x10DE061D,␉NV_SUB_IDS, "Quadro FX 2800M" },␊ |
473 | ␉{ 0x10DE061E,␉NV_SUB_IDS, "Quadro FX 3700M" },␊ |
474 | ␉{ 0x10DE061F,␉NV_SUB_IDS, "Quadro FX 3800M" },␊ |
475 | ␉// 0620 - 062F␊ |
476 | ␉{ 0x10DE0621,␉NV_SUB_IDS, "GeForce GT 230" },␊ |
477 | ␉{ 0x10DE0622,␉NV_SUB_IDS, "GeForce 9600 GT" },␊ |
478 | ␉{ 0x10DE0623,␉NV_SUB_IDS, "GeForce 9600 GS" },␊ |
479 | ␉{ 0x10DE0625,␉NV_SUB_IDS, "GeForce 9600 GSO 512"},␊ |
480 | ␉{ 0x10DE0626,␉NV_SUB_IDS, "GeForce GT 130" },␊ |
481 | ␉{ 0x10DE0627,␉NV_SUB_IDS, "GeForce GT 140" },␊ |
482 | ␉{ 0x10DE0628,␉NV_SUB_IDS, "GeForce 9800M GTS" },␊ |
483 | ␉{ 0x10DE062A,␉NV_SUB_IDS, "GeForce 9700M GTS" },␊ |
484 | ␉{ 0x10DE062B,␉NV_SUB_IDS, "GeForce 9800M GS" },␊ |
485 | ␉{ 0x10DE062C,␉NV_SUB_IDS, "GeForce 9800M GTS" },␊ |
486 | ␉{ 0x10DE062D,␉NV_SUB_IDS, "GeForce 9600 GT" },␊ |
487 | ␉{ 0x10DE062E,␉NV_SUB_IDS, "GeForce 9600 GT" },␊ |
488 | ␉// 0630 - 063F␊ |
489 | ␉{ 0x10DE0631,␉NV_SUB_IDS, "GeForce GTS 160M" },␊ |
490 | ␉{ 0x10DE0632,␉NV_SUB_IDS, "GeForce GTS 150M" },␊ |
491 | ␉{ 0x10DE0635,␉NV_SUB_IDS, "GeForce 9600 GSO" },␊ |
492 | ␉{ 0x10DE0637,␉NV_SUB_IDS, "GeForce 9600 GT" },␊ |
493 | ␉{ 0x10DE0638,␉NV_SUB_IDS, "Quadro FX 1800" },␊ |
494 | ␉{ 0x10DE063A,␉NV_SUB_IDS, "Quadro FX 2700M" },␊ |
495 | ␉// 0640 - 064F␊ |
496 | ␉{ 0x10DE0640,␉NV_SUB_IDS, "GeForce 9500 GT" },␊ |
497 | ␉{ 0x10DE0641,␉NV_SUB_IDS, "GeForce 9400 GT" },␊ |
498 | ␉{ 0x10DE0642,␉NV_SUB_IDS, "GeForce 8400 GS" },␊ |
499 | ␉{ 0x10DE0643,␉NV_SUB_IDS, "GeForce 9500 GT" },␊ |
500 | ␉{ 0x10DE0644,␉NV_SUB_IDS, "GeForce 9500 GS" },␊ |
501 | ␉{ 0x10DE0645,␉NV_SUB_IDS, "GeForce 9500 GS" },␊ |
502 | ␉{ 0x10DE0646,␉NV_SUB_IDS, "GeForce GT 120" },␊ |
503 | ␉{ 0x10DE0647,␉NV_SUB_IDS, "GeForce 9600M GT" },␊ |
504 | ␉{ 0x10DE0648,␉NV_SUB_IDS, "GeForce 9600M GS" },␊ |
505 | ␉{ 0x10DE0649,␉NV_SUB_IDS, "GeForce 9600M GT" },␊ |
506 | ␉{ 0x10DE064A,␉NV_SUB_IDS, "GeForce 9700M GT" },␊ |
507 | ␉{ 0x10DE064B,␉NV_SUB_IDS, "GeForce 9500M G" },␊ |
508 | ␉{ 0x10DE064C,␉NV_SUB_IDS, "GeForce 9650M GT" },␊ |
509 | ␉// 0650 - 065F␊ |
510 | ␉{ 0x10DE0651,␉NV_SUB_IDS, "GeForce G 110M" },␊ |
511 | ␉{ 0x10DE0652,␉NV_SUB_IDS, "GeForce GT 130M" },␊ |
512 | ␉{ 0x10DE0653,␉NV_SUB_IDS, "GeForce GT 120M" },␊ |
513 | ␉{ 0x10DE0654,␉NV_SUB_IDS, "GeForce GT 220M" },␊ |
514 | ␉{ 0x10DE0655,␉NV_SUB_IDS, "GeForce GT 120" },␊ |
515 | ␉{ 0x10DE0656,␉NV_SUB_IDS, "GeForce 9650 S" },␊ |
516 | ␉{ 0x10DE0658,␉NV_SUB_IDS, "Quadro FX 380" },␊ |
517 | ␉{ 0x10DE0659,␉NV_SUB_IDS, "Quadro FX 580" },␊ |
518 | ␉{ 0x10DE065A,␉NV_SUB_IDS, "Quadro FX 1700M" },␊ |
519 | ␉{ 0x10DE065B,␉NV_SUB_IDS, "GeForce 9400 GT" },␊ |
520 | ␉{ 0x10DE065C,␉NV_SUB_IDS, "Quadro FX 770M" },␊ |
521 | ␉{ 0x10DE065F,␉NV_SUB_IDS, "GeForce G210" },␊ |
522 | ␉// 0660 - 066F␊ |
523 | ␉// 0670 - 067F␊ |
524 | ␉// 0680 - 068F␊ |
525 | ␉// 0690 - 069F␊ |
526 | ␉// 06A0 - 06AF␊ |
527 | ␉// 06B0 - 06BF␊ |
528 | ␉// 06C0 - 06CF␊ |
529 | ␉{ 0x10DE06C0,␉NV_SUB_IDS, "GeForce GTX 480" },␊ |
530 | ␉{ 0x10DE06C4,␉NV_SUB_IDS, "GeForce GTX 465" },␊ |
531 | ␉{ 0x10DE06CA,␉NV_SUB_IDS, "GeForce GTX 480M" },␊ |
532 | ␉{ 0x10DE06CD,␉NV_SUB_IDS, "GeForce GTX 470" },␊ |
533 | ␉// 06D0 - 06DF␊ |
534 | ␉{ 0x10DE06D1,␉0x10DE0771,␉"Tesla C2050" },␊ |
535 | ␉{ 0x10DE06D1,␉0x10DE0772,␉"Tesla C2070" },␊ |
536 | ␉{ 0x10DE06D2,␉0x10DE0774,␉"Tesla M2070" },␊ |
537 | ␉{ 0x10DE06D2,␉0x10DE0830,␉"Tesla M2070" },␊ |
538 | ␉{ 0x10DE06D2,␉0x10DE0842,␉"Tesla M2070" },␊ |
539 | ␉{ 0x10DE06D2,␉0x10DE088F,␉"Tesla X2070" },␊ |
540 | ␉{ 0x10DE06D2,␉0x10DE0908,␉"Tesla M2070" },␊ |
541 | ␉{ 0x10DE06D8,␉NV_SUB_IDS, "Quadro 6000" },␊ |
542 | ␉{ 0x10DE06D9,␉NV_SUB_IDS, "Quadro 5000" },␊ |
543 | ␉{ 0x10DE06DA,␉NV_SUB_IDS, "Quadro 5000M" },␊ |
544 | ␉{ 0x10DE06DC,␉NV_SUB_IDS, "Quadro 6000" },␊ |
545 | ␉{ 0x10DE06DD,␉NV_SUB_IDS, "Quadro 4000" },␊ |
546 | ␉{ 0x10DE06DE,␉0x10DE0773,␉"Tesla S2050" },␊ |
547 | ␉{ 0x10DE06DE,␉0x10DE077A,␉"Tesla M2050" },␊ |
548 | ␉{ 0x10DE06DE,␉0x10DE082F,␉"Tesla M2050" },␊ |
549 | ␉{ 0x10DE06DE,␉0x10DE0830,␉"Tesla M2070" },␊ |
550 | ␉{ 0x10DE06DE,␉0x10DE0831,␉"Tesla M2070" },␊ |
551 | ␉{ 0x10DE06DE,␉0x10DE0832,␉"Tesla M2070" },␊ |
552 | ␉{ 0x10DE06DE,␉0x10DE0840,␉"Tesla X2070" },␊ |
553 | ␉{ 0x10DE06DE,␉0x10DE0842,␉"Tesla M2050" },␊ |
554 | ␉{ 0x10DE06DE,␉0x10DE0843,␉"Tesla M2050" },␊ |
555 | ␉{ 0x10DE06DE,␉0x10DE0846,␉"Tesla M2050" },␊ |
556 | ␉{ 0x10DE06DE,␉0x10DE0866,␉"Tesla M2050" },␊ |
557 | ␉{ 0x10DE06DE,␉0x10DE0907,␉"Tesla M2050" },␊ |
558 | ␉{ 0x10DE06DE,␉0x10DE091E,␉"Tesla M2050" },␊ |
559 | ␉{ 0x10DE06DF,␉0x10DE0842,␉"Tesla M2070-Q" },␊ |
560 | ␉{ 0x10DE06DF,␉0x10DE084D,␉"Tesla M2070-Q" },␊ |
561 | ␉{ 0x10DE06DF,␉0x10DE087F,␉"Tesla M2070-Q" },␊ |
562 | ␉// 06E0 - 06EF␊ |
563 | ␉{ 0x10DE06E0, NV_SUB_IDS, "GeForce 9300 GE" },␊ |
564 | ␉{ 0x10DE06E1, NV_SUB_IDS, "GeForce 9300 GS" },␊ |
565 | ␉{ 0x10DE06E2, NV_SUB_IDS, "GeForce 8400" },␊ |
566 | ␉{ 0x10DE06E3, NV_SUB_IDS, "GeForce 8400 SE" },␊ |
567 | ␉{ 0x10DE06E4, NV_SUB_IDS, "GeForce 8400 GS" },␊ |
568 | ␉{ 0x10DE06E5, NV_SUB_IDS, "GeForce 9300M GS" },␊ |
569 | ␉{ 0x10DE06E6, NV_SUB_IDS, "GeForce G100" },␊ |
570 | ␉{ 0x10DE06E7, NV_SUB_IDS, "GeForce 9300 SE" },␊ |
571 | ␉{ 0x10DE06E8, NV_SUB_IDS, "GeForce 9200M GS" },␊ |
572 | ␉{ 0x10DE06E9, NV_SUB_IDS, "GeForce 9300M GS" },␊ |
573 | ␉{ 0x10DE06EA, NV_SUB_IDS, "Quadro NVS 150M" },␊ |
574 | ␉{ 0x10DE06EB, NV_SUB_IDS, "Quadro NVS 160M" },␊ |
575 | ␉{ 0x10DE06EC, NV_SUB_IDS, "GeForce G 105M" },␊ |
576 | ␉{ 0x10DE06EF, NV_SUB_IDS, "GeForce G 103M" },␊ |
577 | ␉// 06F0 - 06FF␊ |
578 | ␉{ 0x10DE06F1, NV_SUB_IDS, "GeForce G105M" },␊ |
579 | ␉{ 0x10DE06F8, NV_SUB_IDS, "Quadro NVS 420" },␊ |
580 | ␉{ 0x10DE06F9, NV_SUB_IDS, "Quadro FX 370 LP" },␊ |
581 | ␉{ 0x10DE06FA, NV_SUB_IDS, "Quadro NVS 450" },␊ |
582 | ␉{ 0x10DE06FB, NV_SUB_IDS, "Quadro FX 370M" },␊ |
583 | ␉{ 0x10DE06FD, NV_SUB_IDS, "Quadro NVS 295" },␊ |
584 | ␉{ 0x10DE06FF, NV_SUB_IDS, "HICx16 + Graphics" },␊ |
585 | ␉// 0700 - 070F␊ |
586 | ␉// 0710 - 071F␊ |
587 | ␉// 0720 - 072F␊ |
588 | ␉// 0730 - 073F␊ |
589 | ␉// 0740 - 074F␊ |
590 | ␉// 0750 - 075F␊ |
591 | ␉// 0760 - 076F␊ |
592 | ␉// 0770 - 077F␊ |
593 | ␉// 0780 - 078F␊ |
594 | ␉// 0790 - 079F␊ |
595 | ␉// 07A0 - 07AF␊ |
596 | ␉// 07B0 - 07BF␊ |
597 | ␉// 07C0 - 07CF␊ |
598 | ␉// 07D0 - 07DF␊ |
599 | ␉// 07E0 - 07EF␊ |
600 | ␉{ 0x10DE07E0, NV_SUB_IDS, "GeForce 7150 / nForce 630i" },␊ |
601 | ␉{ 0x10DE07E1, NV_SUB_IDS, "GeForce 7100 / nForce 630i" },␊ |
602 | ␉{ 0x10DE07E2, NV_SUB_IDS, "GeForce 7050 / nForce 630i" },␊ |
603 | ␉{ 0x10DE07E3, NV_SUB_IDS, "GeForce 7050 / nForce 610i" },␊ |
604 | ␉{ 0x10DE07E5, NV_SUB_IDS, "GeForce 7050 / nForce 620i" },␊ |
605 | ␉// 07F0 - 07FF␊ |
606 | ␉// 0800 - 080F␊ |
607 | ␉// 0810 - 081F␊ |
608 | ␉// 0820 - 082F␊ |
609 | ␉// 0830 - 083F␊ |
610 | ␉// 0840 - 084F␊ |
611 | ␉{ 0x10DE0840, NV_SUB_IDS, "GeForce 8200M" },␊ |
612 | ␉{ 0x10DE0844, NV_SUB_IDS, "GeForce 9100M G" },␊ |
613 | ␉{ 0x10DE0845, NV_SUB_IDS, "GeForce 8200M G" },␊ |
614 | ␉{ 0x10DE0846, NV_SUB_IDS, "GeForce 9200" },␊ |
615 | ␉{ 0x10DE0847, NV_SUB_IDS, "GeForce 9100" },␊ |
616 | ␉{ 0x10DE0848, NV_SUB_IDS, "GeForce 8300" },␊ |
617 | ␉{ 0x10DE0849, NV_SUB_IDS, "GeForce 8200" },␊ |
618 | ␉{ 0x10DE084A, NV_SUB_IDS, "nForce 730a" },␊ |
619 | ␉{ 0x10DE084B, NV_SUB_IDS, "GeForce 9200" },␊ |
620 | ␉{ 0x10DE084C, NV_SUB_IDS, "nForce 980a/780a SLI" },␊ |
621 | ␉{ 0x10DE084D, NV_SUB_IDS, "nForce 750a SLI" },␊ |
622 | ␉{ 0x10DE084F, NV_SUB_IDS, "GeForce 8100 / nForce 720a" },␊ |
623 | ␉// 0850 - 085F␊ |
624 | ␉// 0860 - 086F␊ |
625 | ␉{ 0x10DE0860, NV_SUB_IDS, "GeForce 9400" },␊ |
626 | ␉{ 0x10DE0861, NV_SUB_IDS, "GeForce 9400" },␊ |
627 | ␉{ 0x10DE0862, NV_SUB_IDS, "GeForce 9400M G" },␊ |
628 | ␉{ 0x10DE0863, NV_SUB_IDS, "GeForce 9400M" },␊ |
629 | ␉{ 0x10DE0864, NV_SUB_IDS, "GeForce 9300" },␊ |
630 | ␉{ 0x10DE0865, NV_SUB_IDS, "ION" },␊ |
631 | ␉{ 0x10DE0866, NV_SUB_IDS, "GeForce 9400M G" },␊ |
632 | ␉{ 0x10DE0867, NV_SUB_IDS, "GeForce 9400" },␊ |
633 | ␉{ 0x10DE0868, NV_SUB_IDS, "nForce 760i SLI" },␊ |
634 | ␉{ 0x10DE0869, NV_SUB_IDS, "GeForce 9400" },␊ |
635 | ␉{ 0x10DE086A, NV_SUB_IDS, "GeForce 9400" },␊ |
636 | ␉{ 0x10DE086C, NV_SUB_IDS, "GeForce 9300 / nForce 730i" },␊ |
637 | ␉{ 0x10DE086D, NV_SUB_IDS, "GeForce 9200" },␊ |
638 | ␉{ 0x10DE086E, NV_SUB_IDS, "GeForce 9100M G" },␊ |
639 | ␉{ 0x10DE086F, NV_SUB_IDS, "GeForce 8200M G" },␊ |
640 | ␉// 0870 - 087F␊ |
641 | ␉{ 0x10DE0870, NV_SUB_IDS, "GeForce 9400M" },␊ |
642 | ␉{ 0x10DE0871, NV_SUB_IDS, "GeForce 9200" },␊ |
643 | ␉{ 0x10DE0872, NV_SUB_IDS, "GeForce G102M" },␊ |
644 | ␉{ 0x10DE0873, NV_SUB_IDS, "GeForce G102M" },␊ |
645 | ␉{ 0x10DE0874, NV_SUB_IDS, "ION" },␊ |
646 | ␉{ 0x10DE0876, NV_SUB_IDS, "ION" },␊ |
647 | ␉{ 0x10DE087A, NV_SUB_IDS, "GeForce 9400" },␊ |
648 | ␉{ 0x10DE087D, NV_SUB_IDS, "ION" },␊ |
649 | ␉{ 0x10DE087E, NV_SUB_IDS, "ION LE" },␊ |
650 | ␉{ 0x10DE087F, NV_SUB_IDS, "ION LE" },␊ |
651 | ␉// 0880 - 088F␊ |
652 | ␉// 0890 - 089F␊ |
653 | ␉// 08A0 - 08AF␊ |
654 | ␉{ 0x10DE08A0, NV_SUB_IDS, "GeForce 320M" },␊ |
655 | ␉{ 0x10DE08A4, NV_SUB_IDS, "GeForce 320M" },␊ |
656 | ␉{ 0x10DE08A5, NV_SUB_IDS, "GeForce 320M" },␊ |
657 | ␉// 08B0 - 08BF␊ |
658 | ␉// 08C0 - 08CF␊ |
659 | ␉// 08D0 - 08DF␊ |
660 | ␉// 08E0 - 08EF␊ |
661 | ␉// 08F0 - 08FF␊ |
662 | ␉// 0900 - 090F␊ |
663 | ␉// 0910 - 091F␊ |
664 | ␉// 0920 - 092F␊ |
665 | ␉// 0930 - 093F␊ |
666 | ␉// 0940 - 094F␊ |
667 | ␉// 0950 - 095F␊ |
668 | ␉// 0960 - 096F␊ |
669 | ␉// 0970 - 097F␊ |
670 | ␉// 0980 - 098F␊ |
671 | ␉// 0990 - 099F␊ |
672 | ␉// 09A0 - 09AF␊ |
673 | ␉// 09B0 - 09BF␊ |
674 | ␉// 09C0 - 09CF␊ |
675 | ␉// 09D0 - 09DF␊ |
676 | ␉// 09E0 - 09EF␊ |
677 | ␉// 09F0 - 09FF␊ |
678 | ␉// 0A00 - 0A0F␊ |
679 | ␉// 0A10 - 0A1F␊ |
680 | ␉// 0A20 - 0A2F␊ |
681 | ␉{ 0x10DE0A20, NV_SUB_IDS, "GeForce GT220" },␊ |
682 | ␉{ 0x10DE0A22, NV_SUB_IDS, "GeForce 315" },␊ |
683 | ␉{ 0x10DE0A23, NV_SUB_IDS, "GeForce 210" },␊ |
684 | ␉{ 0x10DE0A26, NV_SUB_IDS, "GeForce 405" },␊ |
685 | ␉{ 0x10DE0A27, NV_SUB_IDS, "GeForce 405" },␊ |
686 | ␉{ 0x10DE0A28, NV_SUB_IDS, "GeForce GT 230M" },␊ |
687 | ␉{ 0x10DE0A29, NV_SUB_IDS, "GeForce GT 330M" },␊ |
688 | ␉{ 0x10DE0A2A, NV_SUB_IDS, "GeForce GT 230M" },␊ |
689 | ␉{ 0x10DE0A2B, NV_SUB_IDS, "GeForce GT 330M" },␊ |
690 | ␉{ 0x10DE0A2C, NV_SUB_IDS, "NVS 5100M" },␊ |
691 | ␉{ 0x10DE0A2D, NV_SUB_IDS, "GeForce GT 320M" },␊ |
692 | ␉// 0A30 - 0A3F␊ |
693 | { 0x10DE0A32, NV_SUB_IDS, "GeForce GT 415" },␊ |
694 | ␉{ 0x10DE0A34, NV_SUB_IDS, "GeForce GT 240M" },␊ |
695 | ␉{ 0x10DE0A35, NV_SUB_IDS, "GeForce GT 325M" },␊ |
696 | ␉{ 0x10DE0A38, NV_SUB_IDS, "Quadro 400" },␊ |
697 | ␉{ 0x10DE0A3C, NV_SUB_IDS, "Quadro FX 880M" },␊ |
698 | ␉// 0A40 - 0A4F␊ |
699 | ␉// 0A50 - 0A5F␊ |
700 | ␉// 0A60 - 0A6F␊ |
701 | ␉{ 0x10DE0A60, NV_SUB_IDS, "GeForce G210" },␊ |
702 | ␉{ 0x10DE0A62, NV_SUB_IDS, "GeForce 205" },␊ |
703 | ␉{ 0x10DE0A63, NV_SUB_IDS, "GeForce 310" },␊ |
704 | ␉{ 0x10DE0A64, NV_SUB_IDS, "ION" },␊ |
705 | ␉{ 0x10DE0A65, NV_SUB_IDS, "GeForce 210" },␊ |
706 | ␉{ 0x10DE0A66, NV_SUB_IDS, "GeForce 310" },␊ |
707 | ␉{ 0x10DE0A67, NV_SUB_IDS, "GeForce 315" },␊ |
708 | ␉{ 0x10DE0A68, NV_SUB_IDS, "GeForce G105M" },␊ |
709 | ␉{ 0x10DE0A69, NV_SUB_IDS, "GeForce G105M" },␊ |
710 | ␉{ 0x10DE0A6A, NV_SUB_IDS, "NVS 2100M" },␊ |
711 | ␉{ 0x10DE0A6C, NV_SUB_IDS, "NVS 3100M" },␊ |
712 | ␉{ 0x10DE0A6E, NV_SUB_IDS, "GeForce 305M" },␊ |
713 | ␉{ 0x10DE0A6F, NV_SUB_IDS, "ION" },␊ |
714 | ␉// 0A70 - 0A7F␊ |
715 | ␉{ 0x10DE0A70, NV_SUB_IDS, "GeForce 310M" },␊ |
716 | ␉{ 0x10DE0A71, NV_SUB_IDS, "GeForce 305M" },␊ |
717 | ␉{ 0x10DE0A72, NV_SUB_IDS, "GeForce 310M" },␊ |
718 | ␉{ 0x10DE0A73, NV_SUB_IDS, "GeForce 305M" },␊ |
719 | ␉{ 0x10DE0A74, NV_SUB_IDS, "GeForce G210M" },␊ |
720 | ␉{ 0x10DE0A75, NV_SUB_IDS, "GeForce 310M" },␊ |
721 | ␉{ 0x10DE0A76, NV_SUB_IDS, "ION" },␊ |
722 | ␉{ 0x10DE0A78, NV_SUB_IDS, "Quadro FX 380 LP" },␊ |
723 | ␉{ 0x10DE0A7A, NV_SUB_IDS, "GeForce 315M" },␊ |
724 | ␉{ 0x10DE0A7C, NV_SUB_IDS, "Quadro FX 380M" },␊ |
725 | ␉// 0A80 - 0A8F␊ |
726 | ␉// 0A90 - 0A9F␊ |
727 | ␉// 0AA0 - 0AAF␊ |
728 | ␉// 0AB0 - 0ABF␊ |
729 | ␉// 0AC0 - 0ACF␊ |
730 | ␉// 0AD0 - 0ADF␊ |
731 | ␉// 0AE0 - 0AEF␊ |
732 | ␉// 0AF0 - 0AFF␊ |
733 | ␉// 0B00 - 0B0F␊ |
734 | ␉// 0B10 - 0B1F␊ |
735 | ␉// 0B20 - 0B2F␊ |
736 | ␉// 0B30 - 0B3F␊ |
737 | ␉// 0B40 - 0B4F␊ |
738 | ␉// 0B50 - 0B5F␊ |
739 | ␉// 0B60 - 0B6F␊ |
740 | ␉// 0B70 - 0B7F␊ |
741 | ␉// 0B80 - 0B8F␊ |
742 | ␉// 0B90 - 0B9F␊ |
743 | ␉// 0BA0 - 0BAF␊ |
744 | ␉// 0BB0 - 0BBF␊ |
745 | ␉// 0BC0 - 0BCF␊ |
746 | ␉// 0BD0 - 0BDF␊ |
747 | ␉// 0BE0 - 0BEF␊ |
748 | ␉// 0BF0 - 0BFF␊ |
749 | ␉// 0C00 - 0C0F␊ |
750 | ␉// 0C10 - 0C1F␊ |
751 | ␉// 0C20 - 0C2F␊ |
752 | ␉// 0C30 - 0C3F␊ |
753 | ␉// 0C40 - 0C4F␊ |
754 | ␉// 0C50 - 0C5F␊ |
755 | ␉// 0C60 - 0C6F␊ |
756 | ␉// 0C70 - 0C7F␊ |
757 | ␉// 0C80 - 0C8F␊ |
758 | ␉// 0C90 - 0C9F␊ |
759 | ␉// 0CA0 - 0CAF␊ |
760 | ␉{ 0x10DE0CA0, NV_SUB_IDS, "GeForce GT 330 " },␊ |
761 | ␉{ 0x10DE0CA2, NV_SUB_IDS, "GeForce GT 320" },␊ |
762 | ␉{ 0x10DE0CA3, NV_SUB_IDS, "GeForce GT 240" },␊ |
763 | ␉{ 0x10DE0CA4, NV_SUB_IDS, "GeForce GT 340" },␊ |
764 | ␉{ 0x10DE0CA5, NV_SUB_IDS, "GeForce GT 220" },␊ |
765 | ␉{ 0x10DE0CA7, NV_SUB_IDS, "GeForce GT 330" },␊ |
766 | ␉{ 0x10DE0CA8, NV_SUB_IDS, "GeForce GTS 260M" },␊ |
767 | ␉{ 0x10DE0CA9, NV_SUB_IDS, "GeForce GTS 250M" },␊ |
768 | ␉{ 0x10DE0CAC, NV_SUB_IDS, "GeForce GT 220" },␊ |
769 | ␉{ 0x10DE0CAF, NV_SUB_IDS, "GeForce GT 335M" },␊ |
770 | ␉// 0CB0 - 0CBF␊ |
771 | ␉{ 0x10DE0CB0, NV_SUB_IDS, "GeForce GTS 350M" },␊ |
772 | ␉{ 0x10DE0CB1, NV_SUB_IDS, "GeForce GTS 360M" },␊ |
773 | ␉{ 0x10DE0CBC, NV_SUB_IDS, "Quadro FX 1800M" },␊ |
774 | ␉// 0CC0 - 0CCF␊ |
775 | ␉// 0CD0 - 0CDF␊ |
776 | ␉// 0CE0 - 0CEF␊ |
777 | ␉// 0CF0 - 0CFF␊ |
778 | ␉// 0D00 - 0D0F␊ |
779 | ␉// 0D10 - 0D1F␊ |
780 | ␉// 0D20 - 0D2F␊ |
781 | ␉// 0D30 - 0D3F␊ |
782 | ␉// 0D40 - 0D4F␊ |
783 | ␉// 0D50 - 0D5F␊ |
784 | ␉// 0D60 - 0D6F␊ |
785 | ␉// 0D70 - 0D7F␊ |
786 | ␉// 0D80 - 0D8F␊ |
787 | ␉// 0D90 - 0D9F␊ |
788 | ␉// 0DA0 - 0DAF␊ |
789 | ␉// 0DB0 - 0DBF␊ |
790 | ␉// 0DC0 - 0DCF␊ |
791 | ␉{ 0x10DE0DC0, NV_SUB_IDS, "GeForce GT 440" },␊ |
792 | ␉{ 0x10DE0DC4, NV_SUB_IDS, "GeForce GTS 450" },␊ |
793 | ␉{ 0x10DE0DC5, NV_SUB_IDS, "GeForce GTS 450" },␊ |
794 | ␉{ 0x10DE0DC6, NV_SUB_IDS, "GeForce GTS 450" },␊ |
795 | ␉{ 0x10DE0DCD, NV_SUB_IDS, "GeForce GT 555M" },␊ |
796 | ␉{ 0x10DE0DCE, NV_SUB_IDS, "GeForce GT 555M" },␊ |
797 | ␉// 0DD0 - 0DDF␊ |
798 | ␉{ 0x10DE0DD1, NV_SUB_IDS, "GeForce GTX 460M" },␊ |
799 | ␉{ 0x10DE0DD2, NV_SUB_IDS, "GeForce GT 445M" },␊ |
800 | ␉{ 0x10DE0DD3, NV_SUB_IDS, "GeForce GT 435M" },␊ |
801 | ␉{ 0x10DE0DD6, NV_SUB_IDS, "GeForce GT 550M" },␊ |
802 | ␉{ 0x10DE0DD8,␉0x10DE084A,␉"Quadro 2000" },␊ |
803 | ␉{ 0x10DE0DD8,␉0x10DE0914,␉"Quadro 2000D" },␊ |
804 | ␉{ 0x10DE0DDA, NV_SUB_IDS, "Quadro 2000M" },␊ |
805 | ␉// 0DE0 - 0DEF␊ |
806 | ␉{ 0x10DE0DE0, NV_SUB_IDS, "GeForce GT 440" },␊ |
807 | ␉{ 0x10DE0DE1, NV_SUB_IDS, "GeForce GT 430" },␊ |
808 | ␉{ 0x10DE0DE2, NV_SUB_IDS, "GeForce GT 420" },␊ |
809 | ␉{ 0x10DE0DE4, NV_SUB_IDS, "GeForce GT 520" },␊ |
810 | ␉{ 0x10DE0DE5, NV_SUB_IDS, "GeForce GT 530" },␊ |
811 | { 0x10DE0DE8, NV_SUB_IDS, "GeForce GT 620M" },␊ |
812 | ␉{ 0x10DE0DE9, NV_SUB_IDS, "GeForce GT 630M" },␊ |
813 | { 0x10DE0DEA, NV_SUB_IDS, "GeForce 610M" },␊ |
814 | ␉{ 0x10DE0DEB, NV_SUB_IDS, "GeForce GT 555M" },␊ |
815 | ␉{ 0x10DE0DEC, NV_SUB_IDS, "GeForce GT 525M" },␊ |
816 | ␉{ 0x10DE0DED, NV_SUB_IDS, "GeForce GT 520M" },␊ |
817 | ␉{ 0x10DE0DEE, NV_SUB_IDS, "GeForce GT 415M" },␊ |
818 | { 0x10DE0DEF, NV_SUB_IDS, "NVS 5400M" },␊ |
819 | ␉// 0DF0 - 0DFF␊ |
820 | ␉{ 0x10DE0DF0, NV_SUB_IDS, "GeForce GT 425M" },␊ |
821 | ␉{ 0x10DE0DF1, NV_SUB_IDS, "GeForce GT 420M" },␊ |
822 | ␉{ 0x10DE0DF2, NV_SUB_IDS, "GeForce GT 435M" },␊ |
823 | ␉{ 0x10DE0DF3, NV_SUB_IDS, "GeForce GT 420M" },␊ |
824 | ␉{ 0x10DE0DF4, NV_SUB_IDS, "GeForce GT 540M" },␊ |
825 | ␉{ 0x10DE0DF5, NV_SUB_IDS, "GeForce GT 525M" },␊ |
826 | ␉{ 0x10DE0DF6, NV_SUB_IDS, "GeForce GT 550M" },␊ |
827 | ␉{ 0x10DE0DF7, NV_SUB_IDS, "GeForce GT 520M" },␊ |
828 | ␉{ 0x10DE0DF8, NV_SUB_IDS, "Quadro 600" },␊ |
829 | { 0x10DE0DF9, NV_SUB_IDS, "Quadro 500M" },␊ |
830 | ␉{ 0x10DE0DFA, NV_SUB_IDS, "Quadro 1000M" },␊ |
831 | ␉{ 0x10DE0DFC, NV_SUB_IDS, "NVS 5200M" },␊ |
832 | ␉// 0E00 - 0E0F␊ |
833 | ␉// 0E10 - 0E1F␊ |
834 | ␉// 0E20 - 0E2F␊ |
835 | ␉{ 0x10DE0E22, NV_SUB_IDS, "GeForce GTX 460" },␊ |
836 | ␉{ 0x10DE0E23, NV_SUB_IDS, "GeForce GTX 460 SE" },␊ |
837 | ␉{ 0x10DE0E24, NV_SUB_IDS, "GeForce GTX 460" },␊ |
838 | ␉// 0E30 - 0E3F␊ |
839 | ␉{ 0x10DE0E30, NV_SUB_IDS, "GeForce GTX 470M" },␊ |
840 | ␉{ 0x10DE0E31, NV_SUB_IDS, "GeForce GTX 485M" },␊ |
841 | ␉{ 0x10DE0E3A, NV_SUB_IDS, "Quadro 3000M" },␊ |
842 | ␉{ 0x10DE0E3B, NV_SUB_IDS, "Quadro 4000M" },␊ |
843 | ␉// 0E40 - 0E4F␊ |
844 | ␉// 0E50 - 0E5F␊ |
845 | ␉// 0E60 - 0E6F␊ |
846 | ␉// 0E70 - 0E7F␊ |
847 | ␉// 0E80 - 0E8F␊ |
848 | ␉// 0E90 - 0E9F␊ |
849 | ␉// 0EA0 - 0EAF␊ |
850 | ␉// 0EB0 - 0EBF␊ |
851 | ␉// 0EC0 - 0ECF␊ |
852 | ␉// 0ED0 - 0EDF␊ |
853 | ␉// 0EE0 - 0EEF␊ |
854 | ␉// 0EF0 - 0EFF␊ |
855 | ␉// 0F00 - 0F0F␊ |
856 | { 0x10DE0F00, NV_SUB_IDS, "GeForce GT 630" },␊ |
857 | { 0x10DE0F01, NV_SUB_IDS, "GeForce GT 620" },␊ |
858 | ␉// 0F10 - 0F1F␊ |
859 | ␉// 0F20 - 0F2F␊ |
860 | ␉// 0F30 - 0F3F␊ |
861 | ␉// 0F40 - 0F4F␊ |
862 | ␉// 0F50 - 0F5F␊ |
863 | ␉// 0F60 - 0F6F␊ |
864 | ␉// 0F70 - 0F7F␊ |
865 | ␉// 0F80 - 0F8F␊ |
866 | ␉// 0F90 - 0F9F␊ |
867 | ␉// 0FA0 - 0FAF␊ |
868 | ␉// 0FB0 - 0FBF␊ |
869 | ␉// 0FC0 - 0FCF␊ |
870 | { 0x10DE0FC0, NV_SUB_IDS, "GeForce GT 640" },␊ |
871 | { 0x10DE0FC1, NV_SUB_IDS, "GeForce GT 640" },␊ |
872 | { 0x10DE0FC2, NV_SUB_IDS, "GeForce GT 630" },␊ |
873 | { 0x10DE0FCE, NV_SUB_IDS, "GeForce GT 640M LE" },␊ |
874 | ␉// 0FD0 - 0FDF␊ |
875 | { 0x10DE0FD1, NV_SUB_IDS, "GeForce GT 650M" },␊ |
876 | ␉{ 0x10DE0FD2, NV_SUB_IDS, "GeForce GT 640M" },␊ |
877 | { 0x10DE0FD3, NV_SUB_IDS, "GeForce GT 640M LE" },␊ |
878 | ␉{ 0x10DE0FD4, NV_SUB_IDS, "GeForce GTX 660M" },␊ |
879 | { 0x10DE0FD5, NV_SUB_IDS, "GeForce GT 650M" },␊ |
880 | { 0x10DE0FD8, NV_SUB_IDS, "GeForce GT 640M" },␊ |
881 | ␉// 0FE0 - 0FEF␊ |
882 | { 0x10DE0FE0, NV_SUB_IDS, "GeForce GTX 660M" },␊ |
883 | ␉// 0FF0 - 0FFF␊ |
884 | { 0x10DE0FFF, NV_SUB_IDS, "Quadro 410" },␊ |
885 | ␉// 1000 - 100F␊ |
886 | ␉// 1010 - 101F␊ |
887 | ␉// 1020 - 102F␊ |
888 | ␉// 1030 - 103F␊ |
889 | ␉// 1040 - 104F␊ |
890 | ␉{ 0x10DE1040, NV_SUB_IDS, "GeForce GT 520" },␊ |
891 | ␉{ 0x10DE1042, NV_SUB_IDS, "GeForce 510" },␊ |
892 | { 0x10DE1048, NV_SUB_IDS, "GeForce 605" },␊ |
893 | ␉{ 0x10DE1049, NV_SUB_IDS, "GeForce GT 620" },␊ |
894 | { 0x10DE104A, NV_SUB_IDS, "GeForce GT 610" },␊ |
895 | ␉// 1050 - 105F␊ |
896 | ␉{ 0x10DE1050, NV_SUB_IDS, "GeForce GT 520M" },␊ |
897 | ␉{ 0x10DE1051, NV_SUB_IDS, "GeForce GT 520MX" },␊ |
898 | { 0x10DE1052, NV_SUB_IDS, "GeForce GT 520M" },␊ |
899 | ␉{ 0x10DE1054, NV_SUB_IDS, "GeForce GT 410M" },␊ |
900 | ␉{ 0x10DE1055, NV_SUB_IDS, "GeForce 410M" },␊ |
901 | ␉{ 0x10DE1056, NV_SUB_IDS, "Quadro NVS 4200M" },␊ |
902 | ␉{ 0x10DE1057, NV_SUB_IDS, "Quadro NVS 4200M" },␊ |
903 | { 0x10DE1058, NV_SUB_IDS, "GeForce 610M" },␊ |
904 | { 0x10DE1059, NV_SUB_IDS, "GeForce 610M" },␊ |
905 | { 0x10DE105A, NV_SUB_IDS, "GeForce 610M" },␊ |
906 | ␉// 1060 - 106F␊ |
907 | ␉// 1070 - 107F␊ |
908 | { 0x10DE107D, NV_SUB_IDS, "NVS 310" },␊ |
909 | ␉// 1080 - 108F␊ |
910 | ␉{ 0x10DE1080, NV_SUB_IDS, "GeForce GTX 580" },␊ |
911 | ␉{ 0x10DE1081, NV_SUB_IDS, "GeForce GTX 570" },␊ |
912 | ␉{ 0x10DE1082, NV_SUB_IDS, "GeForce GTX 560 Ti" },␊ |
913 | ␉{ 0x10DE1084, NV_SUB_IDS, "GeForce GTX 560" },␊ |
914 | ␉{ 0x10DE1086, NV_SUB_IDS, "GeForce GTX 570" },␊ |
915 | ␉{ 0x10DE1087, NV_SUB_IDS, "GeForce GTX 560 Ti 448" },␊ |
916 | ␉{ 0x10DE1088, NV_SUB_IDS, "GeForce GTX 590" },␊ |
917 | ␉{ 0x10DE1089, NV_SUB_IDS, "GeForce GTX 580" },␊ |
918 | ␉{ 0x10DE108B, NV_SUB_IDS, "GeForce GTX 590" },␊ |
919 | ␉// 1090 - 109F␊ |
920 | { 0x10DE1091,␉0x10DE0887,␉"Tesla M2090" },␊ |
921 | ␉{ 0x10DE1091,␉0x10DE088E,␉"Tesla X2090" },␊ |
922 | ␉{ 0x10DE1091,␉0x10DE0891,␉"Tesla X2090" },␊ |
923 | ␉{ 0x10DE1094,␉0x10DE0888,␉"nVidia Tesla M2075" },␊ |
924 | ␉{ 0x10DE1096, NV_SUB_IDS, "Tesla C2075" },␊ |
925 | ␉{ 0x10DE109A, NV_SUB_IDS, "Quadro 5010M" },␊ |
926 | ␉{ 0x10DE109B, NV_SUB_IDS, "Quadro 7000" },␊ |
927 | ␉// 10A0 - 10AF␊ |
928 | ␉// 10B0 - 10BF␊ |
929 | ␉// 10C0 - 10CF␊ |
930 | ␉{ 0x10DE10C0, NV_SUB_IDS, "GeForce 9300 GS" },␊ |
931 | ␉{ 0x10DE10C3, NV_SUB_IDS, "GeForce 8400 GS" },␊ |
932 | ␉{ 0x10DE10C5, NV_SUB_IDS, "GeForce 405" },␊ |
933 | ␉// 10D0 - 10DF␊ |
934 | ␉{ 0x10DE10D8, NV_SUB_IDS, "NVS 300" },␊ |
935 | ␉// 10E0 - 10EF␊ |
936 | ␉// 10F0 - 10FF␊ |
937 | ␉// 1100 - 110F␊ |
938 | ␉// 1110 - 111F␊ |
939 | ␉// 1120 - 112F␊ |
940 | ␉// 1130 - 113F␊ |
941 | ␉// 1140 - 114F␊ |
942 | { 0x10DE1140, NV_SUB_IDS, "GeForce GT 620M / GT 630M" },␊ |
943 | ␉// 1150 - 115F␊ |
944 | ␉// 1160 - 116F␊ |
945 | ␉// 1170 - 117F␊ |
946 | ␉// 1180 - 118F␊ |
947 | ␉{ 0x10DE1180, NV_SUB_IDS, "GeForce GTX 680" },␊ |
948 | { 0x10DE1188, NV_SUB_IDS, "GeForce GTX 690" },␊ |
949 | { 0x10DE1189, NV_SUB_IDS, "GeForce GTX 670" },␊ |
950 | ␉// 1190 - 119F␊ |
951 | ␉// 11A0 - 11AF␊ |
952 | ␉// 11B0 - 11BF␊ |
953 | ␉// 11C0 - 11CF␊ |
954 | ␉// 11D0 - 11DF␊ |
955 | ␉// 11E0 - 11EF␊ |
956 | ␉// 11F0 - 11FF␊ |
957 | ␉// 1200 - 120F␊ |
958 | ␉{ 0x10DE1200, NV_SUB_IDS, "GeForce GTX 560 Ti" },␊ |
959 | ␉{ 0x10DE1201, NV_SUB_IDS, "GeForce GTX 560" },␊ |
960 | ␉{ 0x10DE1203, NV_SUB_IDS, "GeForce GTX 460 SE v2" },␊ |
961 | { 0x10DE1205, NV_SUB_IDS, "GeForce GTX 460 v2" },␊ |
962 | { 0x10DE1206, NV_SUB_IDS, "GeForce GTX 555" },␊ |
963 | { 0x10DE1207, NV_SUB_IDS, "GeForce GT 645" },␊ |
964 | { 0x10DE1208, NV_SUB_IDS, "GeForce GTX 560 SE" },␊ |
965 | ␉// 1210 - 121F␊ |
966 | ␉{ 0x10DE1210, NV_SUB_IDS, "GeForce GTX 570M" },␊ |
967 | ␉{ 0x10DE1211, NV_SUB_IDS, "GeForce GTX 580M" },␊ |
968 | { 0x10DE1212, NV_SUB_IDS, "GeForce GTX 675M" },␊ |
969 | ␉{ 0x10DE1213, NV_SUB_IDS, "GeForce GTX 670M" },␊ |
970 | ␉// 1220 - 122F␊ |
971 | ␉// 1230 - 123F␊ |
972 | ␉// 1240 - 124F␊ |
973 | { 0x10DE1240, NV_SUB_IDS, "GeForce GT 620M" },␊ |
974 | ␉{ 0x10DE1241, NV_SUB_IDS, "GeForce GT 545" },␊ |
975 | ␉{ 0x10DE1243, NV_SUB_IDS, "GeForce GT 545" },␊ |
976 | ␉{ 0x10DE1244, NV_SUB_IDS, "GeForce GTX 550 Ti" },␊ |
977 | ␉{ 0x10DE1245, NV_SUB_IDS, "GeForce GTS 450" },␊ |
978 | { 0x10DE1246, NV_SUB_IDS, "GeForce GTX 550M" },␊ |
979 | ␉{ 0x10DE1247, NV_SUB_IDS, "GeForce GT 555M" },␊ |
980 | ␉{ 0x10DE1247, 0x10DE212A, "GT 635M" },␊ |
981 | ␉{ 0x10DE1247, 0x10DE212B, "GT 635M" },␊ |
982 | ␉{ 0x10DE1247, 0x10DE212C, "GT 635M" },␊ |
983 | { 0x10DE1248, NV_SUB_IDS, "GeForce GT 555M / GT 635M" },␊ |
984 | { 0x10DE124B, NV_SUB_IDS, "GeForce GT 640" },␊ |
985 | { 0x10DE1249, NV_SUB_IDS, "GeForce GTS 450" },␊ |
986 | { 0x10DE124B, NV_SUB_IDS, "GeForce GT 640" },␊ |
987 | { 0x10DE124D, NV_SUB_IDS, "GeForce GT 555M / GT 635M" },␊ |
988 | ␉// 1250 - 125F␊ |
989 | ␉{ 0x10DE1251, NV_SUB_IDS, "GeForce GTX 560M" },␊ |
990 | ␉// 1260 - 126F␊ |
991 | ␉// 1270 - 127F␊ |
992 | ␉// 1280 - 128F␊ |
993 | ␉// 1290 - 129F␊ |
994 | ␉// 12A0 - 12AF␊ |
995 | ␉// 12B0 - 12BF␊ |
996 | ␉// 12C0 - 12CF␊ |
997 | ␉// 12D0 - 12DF␊ |
998 | ␉// 12E0 - 12EF␊ |
999 | ␉// 12F0 - 12FF␊ |
1000 | };␊ |
1001 | ␊ |
1002 | static int patch_nvidia_rom(uint8_t *rom)␊ |
1003 | {␊ |
1004 | ␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊ |
1005 | ␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊ |
1006 | ␉␉return PATCH_ROM_FAILED;␊ |
1007 | ␉}␊ |
1008 | ␊ |
1009 | ␉uint16_t dcbptr = READ_LE_SHORT(rom, 0x36);␊ |
1010 | ␊ |
1011 | ␉if (!dcbptr) {␊ |
1012 | ␉␉printf("no dcb table found\n");␊ |
1013 | ␉␉return PATCH_ROM_FAILED;␊ |
1014 | ␉}␊ |
1015 | //␉else␊ |
1016 | //␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊ |
1017 | ␊ |
1018 | ␉uint8_t *dcbtable␉ = &rom[dcbptr];␊ |
1019 | ␉uint8_t dcbtable_version = dcbtable[0];␊ |
1020 | ␉uint8_t headerlength␉ = 0;␊ |
1021 | ␉uint8_t numentries␉ = 0;␊ |
1022 | ␉uint8_t recordlength␉ = 0;␊ |
1023 | ␉␊ |
1024 | ␉if (dcbtable_version >= 0x20)␊ |
1025 | ␉{␊ |
1026 | ␉␉uint32_t sig;␊ |
1027 | ␉␉␊ |
1028 | ␉␉if (dcbtable_version >= 0x30)␊ |
1029 | ␉␉{␊ |
1030 | ␉␉␉headerlength = dcbtable[1];␊ |
1031 | ␉␉␉numentries␉ = dcbtable[2];␊ |
1032 | ␉␉␉recordlength = dcbtable[3];␊ |
1033 | ␊ |
1034 | ␉␉␉sig = READ_LE_INT(dcbtable, 6);␊ |
1035 | ␉␉}␊ |
1036 | ␉␉else␊ |
1037 | ␉␉{␊ |
1038 | ␉␉␉sig = READ_LE_INT(dcbtable, 4);␊ |
1039 | ␉␉␉headerlength = 8;␊ |
1040 | ␉␉}␊ |
1041 | ␊ |
1042 | ␉␉if (sig != 0x4edcbdcb)␊ |
1043 | ␉␉{␊ |
1044 | ␉␉␉printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48␊ |
1045 | ␉␉␉return PATCH_ROM_FAILED;␊ |
1046 | ␉␉}␊ |
1047 | ␉}␊ |
1048 | ␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊ |
1049 | ␉{␊ |
1050 | ␉␉char sig[8] = { 0 };␊ |
1051 | ␉␉␊ |
1052 | ␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊ |
1053 | ␉␉recordlength = 10;␊ |
1054 | ␊ |
1055 | ␉␉if (strcmp(sig, "DEV_REC"))␊ |
1056 | ␉␉{␊ |
1057 | ␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊ |
1058 | ␉␉␉return PATCH_ROM_FAILED;␊ |
1059 | ␉␉}␊ |
1060 | ␉}␊ |
1061 | ␉else␊ |
1062 | ␉{␊ |
1063 | ␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊ |
1064 | ␉␉return PATCH_ROM_FAILED;␊ |
1065 | ␉}␊ |
1066 | ␉␊ |
1067 | ␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊ |
1068 | ␉␉numentries = MAX_NUM_DCB_ENTRIES;␊ |
1069 | ␊ |
1070 | ␉uint8_t num_outputs = 0, i = 0;␊ |
1071 | ␊ |
1072 | ␉struct dcbentry␊ |
1073 | ␉{␊ |
1074 | ␉␉uint8_t type;␊ |
1075 | ␉␉uint8_t index;␊ |
1076 | ␉␉uint8_t *heads;␊ |
1077 | ␉} entries[numentries];␊ |
1078 | ␊ |
1079 | ␉for (i = 0; i < numentries; i++)␊ |
1080 | ␉{␊ |
1081 | ␉␉uint32_t connection;␊ |
1082 | ␉␉connection = READ_LE_INT(dcbtable,headerlength + recordlength * i);␊ |
1083 | ␊ |
1084 | ␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊ |
1085 | ␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊ |
1086 | ␉␉␉continue;␊ |
1087 | ␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊ |
1088 | ␉␉␉continue;␊ |
1089 | ␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊ |
1090 | ␉␉␉continue;␊ |
1091 | ␊ |
1092 | ␉␉entries[num_outputs].type = connection & 0xf;␊ |
1093 | ␉␉entries[num_outputs].index = num_outputs;␊ |
1094 | ␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊ |
1095 | ␊ |
1096 | ␉}␊ |
1097 | ␉␊ |
1098 | ␉int has_lvds = false;␊ |
1099 | ␉uint8_t channel1 = 0, channel2 = 0;␊ |
1100 | ␊ |
1101 | ␉for (i = 0; i < num_outputs; i++)␊ |
1102 | ␉{␊ |
1103 | ␉␉if (entries[i].type == 3)␊ |
1104 | ␉␉{␊ |
1105 | ␉␉␉has_lvds = true;␊ |
1106 | ␉␉␉//printf("found LVDS\n");␊ |
1107 | ␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
1108 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1109 | ␉␉}␊ |
1110 | ␉}␊ |
1111 | ␊ |
1112 | ␉// if we have a LVDS output, we group the rest to the second channel␊ |
1113 | ␉if (has_lvds)␊ |
1114 | ␉{␊ |
1115 | ␉␉for (i = 0; i < num_outputs; i++)␊ |
1116 | ␉␉{␊ |
1117 | ␉␉␉if (entries[i].type == TYPE_GROUPED)␊ |
1118 | ␉␉␉␉continue;␊ |
1119 | ␊ |
1120 | ␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
1121 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1122 | ␉␉}␊ |
1123 | ␉}␊ |
1124 | ␉else␊ |
1125 | ␉{␊ |
1126 | ␉␉int x;␊ |
1127 | ␉␉// we loop twice as we need to generate two channels␊ |
1128 | ␉␉for (x = 0; x <= 1; x++)␊ |
1129 | ␉␉{␊ |
1130 | ␉␉␉for (i=0; i<num_outputs; i++)␊ |
1131 | ␉␉␉{␊ |
1132 | ␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊ |
1133 | ␉␉␉␉␉continue;␊ |
1134 | ␉␉␉␉// if type is TMDS, the prior output is ANALOG␊ |
1135 | ␉␉␉␉// we always group ANALOG and TMDS␊ |
1136 | ␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊ |
1137 | ␉␉␉␉if (i && entries[i].type == 0x2)␊ |
1138 | ␉␉␉␉{␊ |
1139 | ␉␉␉␉␉switch (x)␊ |
1140 | ␉␉␉␉␉{␊ |
1141 | ␉␉␉␉␉␉case 0:␊ |
1142 | ␉␉␉␉␉␉␉//printf("group channel 1\n");␊ |
1143 | ␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
1144 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1145 | ␊ |
1146 | ␉␉␉␉␉␉␉if (entries[i-1].type == 0x0)␊ |
1147 | ␉␉␉␉␉␉␉{␊ |
1148 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊ |
1149 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
1150 | ␉␉␉␉␉␉␉}␊ |
1151 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
1152 | ␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊ |
1153 | ␉␉␉␉␉␉␉{␊ |
1154 | ␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊ |
1155 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊ |
1156 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
1157 | ␉␉␉␉␉␉␉}␊ |
1158 | ␉␉␉␉␉␉␉break;␊ |
1159 | ␊ |
1160 | ␉␉␉␉␉␉case 1:␊ |
1161 | ␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊ |
1162 | ␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
1163 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1164 | ␊ |
1165 | ␉␉␉␉␉␉␉if (entries[i - 1].type == 0x0)␊ |
1166 | ␉␉␉␉␉␉␉{␊ |
1167 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊ |
1168 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
1169 | ␉␉␉␉␉␉␉}␊ |
1170 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
1171 | ␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊ |
1172 | ␉␉␉␉␉␉␉{␊ |
1173 | ␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊ |
1174 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊ |
1175 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
1176 | ␉␉␉␉␉␉␉}␊ |
1177 | ␉␉␉␉␉␉␉break;␊ |
1178 | ␉␉␉␉␉}␊ |
1179 | ␉␉␉␉␉break;␊ |
1180 | ␉␉␉␉}␊ |
1181 | ␉␉␉}␊ |
1182 | ␉␉}␊ |
1183 | ␉}␊ |
1184 | ␉␊ |
1185 | ␉// if we have left ungrouped outputs merge them to the empty channel␊ |
1186 | ␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊ |
1187 | ␉togroup = &channel2;␊ |
1188 | ␊ |
1189 | ␉for (i = 0; i < num_outputs; i++)␊ |
1190 | ␉{␊ |
1191 | ␉␉if (entries[i].type != TYPE_GROUPED)␊ |
1192 | ␉␉{␊ |
1193 | ␉␉␉//printf("%d not grouped\n", i);␊ |
1194 | ␉␉␉if (togroup)␊ |
1195 | ␉␉␉{␊ |
1196 | ␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊ |
1197 | ␉␉␉}␊ |
1198 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1199 | ␉␉}␊ |
1200 | ␉}␊ |
1201 | ␉␊ |
1202 | ␉if (channel1 > channel2)␊ |
1203 | ␉{␊ |
1204 | ␉␉uint8_t buff = channel1;␊ |
1205 | ␉␉channel1 = channel2;␊ |
1206 | ␉␉channel2 = buff;␊ |
1207 | ␉}␊ |
1208 | ␉␊ |
1209 | ␉default_NVCAP[6] = channel1;␊ |
1210 | ␉default_NVCAP[8] = channel2;␊ |
1211 | ␉␊ |
1212 | ␉// patching HEADS␊ |
1213 | ␉for (i = 0; i < num_outputs; i++)␊ |
1214 | ␉{␊ |
1215 | ␉␉if (channel1 & (1 << i))␊ |
1216 | ␉␉{␊ |
1217 | ␉␉␉*entries[i].heads = 1;␊ |
1218 | ␉␉}␊ |
1219 | ␉␉else if(channel2 & (1 << i))␊ |
1220 | ␉␉{␊ |
1221 | ␉␉␉*entries[i].heads = 2;␊ |
1222 | ␉␉}␊ |
1223 | ␉}␊ |
1224 | ␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊ |
1225 | }␊ |
1226 | ␊ |
1227 | static char *get_nvidia_model(uint32_t device_id, uint32_t subsys_id)␊ |
1228 | {␊ |
1229 | ␉int i;␊ |
1230 | ␊ |
1231 | ␉// First check in the plist, (for e.g this can override any hardcoded devices)␊ |
1232 | ␉cardList_t * nvcard = FindCardWithIds(device_id, subsys_id);␊ |
1233 | ␉if (nvcard) ␊ |
1234 | ␉{␊ |
1235 | ␉␉if (nvcard->model) ␊ |
1236 | ␉␉{␊ |
1237 | ␉␉␉return nvcard->model;␊ |
1238 | ␉␉}␊ |
1239 | ␉}␊ |
1240 | ␊ |
1241 | ␉for (i = 1; i < (sizeof(nvidia_cards) / sizeof(nvidia_cards[0])); i++) // size of nvidia_cards array for-loop␊ |
1242 | ␉{␊ |
1243 | ␉␉if ((nvidia_cards[i].device == device_id) && (nvidia_cards[i].subdev == subsys_id))␊ |
1244 | {␊ |
1245 | return nvidia_cards[i].name_model;␊ |
1246 | break;␊ |
1247 | }␊ |
1248 | else if ((nvidia_cards[i].device == device_id) && (nvidia_cards[i].subdev == 0x00000000))␊ |
1249 | {␊ |
1250 | return nvidia_cards[i].name_model;␊ |
1251 | break;␊ |
1252 | }␊ |
1253 | ␉}␊ |
1254 | return nvidia_cards[0].name_model;␊ |
1255 | }␊ |
1256 | ␊ |
1257 | static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊ |
1258 | {␊ |
1259 | ␉int fd;␊ |
1260 | ␉int size;␊ |
1261 | ␊ |
1262 | ␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊ |
1263 | ␉{␊ |
1264 | ␉␉return 0;␊ |
1265 | ␉}␊ |
1266 | ␊ |
1267 | ␉size = file_size(fd);␊ |
1268 | ␊ |
1269 | ␉if (size > bufsize)␊ |
1270 | ␉{␊ |
1271 | ␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊ |
1272 | ␉␉␉␉filename, bufsize);␊ |
1273 | ␉␉size = bufsize;␊ |
1274 | ␉}␊ |
1275 | ␉size = read(fd, (char *)buf, size);␊ |
1276 | ␉close(fd);␊ |
1277 | ␊ |
1278 | ␉return size > 0 ? size : 0;␊ |
1279 | }␊ |
1280 | ␊ |
1281 | static int devprop_add_nvidia_template(struct DevPropDevice *device)␊ |
1282 | {␊ |
1283 | ␉char tmp[16];␊ |
1284 | ␊ |
1285 | ␉if (!device)␊ |
1286 | ␉␉return 0;␊ |
1287 | ␊ |
1288 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊ |
1289 | ␉␉return 0;␊ |
1290 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊ |
1291 | ␉␉return 0;␊ |
1292 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊ |
1293 | ␉␉return 0;␊ |
1294 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊ |
1295 | ␉␉return 0;␊ |
1296 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊ |
1297 | ␉␉return 0;␊ |
1298 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊ |
1299 | ␉␉return 0;␊ |
1300 | ␉if (devices_number == 1)␊ |
1301 | ␉{␊ |
1302 | ␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊ |
1303 | ␉␉ return 0;␊ |
1304 | ␉}␊ |
1305 | ␉else␊ |
1306 | ␉{␊ |
1307 | ␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊ |
1308 | ␉␉ return 0;␊ |
1309 | ␉}␊ |
1310 | ␊ |
1311 | ␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊ |
1312 | ␉// len = sprintf(tmp, "Slot-%x", devices_number);␊ |
1313 | ␉sprintf(tmp, "Slot-%x",devices_number);␊ |
1314 | ␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊ |
1315 | ␉devices_number++;␊ |
1316 | ␊ |
1317 | ␉return 1;␊ |
1318 | }␊ |
1319 | ␊ |
1320 | int hex2bin(const char *hex, uint8_t *bin, int len)␊ |
1321 | {␊ |
1322 | ␉char␉*p;␊ |
1323 | ␉int␉i;␊ |
1324 | ␉char␉buf[3];␊ |
1325 | ␊ |
1326 | ␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊ |
1327 | ␉␉printf("[ERROR] bin2hex input error\n");␊ |
1328 | ␉␉return -1;␊ |
1329 | ␉}␊ |
1330 | ␊ |
1331 | ␉buf[2] = '\0';␊ |
1332 | ␉p = (char *) hex;␊ |
1333 | ␊ |
1334 | ␉for (i = 0; i < len; i++)␊ |
1335 | ␉{␊ |
1336 | ␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊ |
1337 | ␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊ |
1338 | ␉␉␉return -2;␊ |
1339 | ␉␉}␊ |
1340 | ␉␉buf[0] = *p++;␊ |
1341 | ␉␉buf[1] = *p++;␊ |
1342 | ␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊ |
1343 | ␉}␊ |
1344 | ␉return 0;␊ |
1345 | }␊ |
1346 | ␊ |
1347 | unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev, uint32_t device_id, uint32_t subsys_id)␊ |
1348 | {␊ |
1349 | ␉unsigned long long vram_size = 0;␊ |
1350 | ␉␊ |
1351 | ␉// First check if any value exist in the plist␊ |
1352 | ␉cardList_t * nvcard = FindCardWithIds(device_id, subsys_id);␊ |
1353 | ␉if (nvcard) ␊ |
1354 | ␉{␊ |
1355 | ␉␉if (nvcard->videoRam > 0) ␊ |
1356 | ␉␉{␊ |
1357 | ␉␉␉vram_size = nvcard->videoRam * 1024 * 1024;␊ |
1358 | ␊ |
1359 | ␉␉␉return vram_size;␊ |
1360 | ␉␉}␊ |
1361 | ␉}␊ |
1362 | ␊ |
1363 | ␉// Then, Workaround for 9600M GT, GT 210/420/430/440/525M/540M & GTX 560M␊ |
1364 | ␉switch (nvda_dev->device_id)␊ |
1365 | ␉{␊ |
1366 | ␉␉case 0x0647: // 9600M GT 0647␊ |
1367 | ␉␉␉vram_size = 512*1024*1024; // 512 MB␊ |
1368 | ␉␉␉break;␊ |
1369 | ␉␉case 0x0A65: // GT 210␊ |
1370 | ␉␉case 0x0DE0: // GT 440␊ |
1371 | ␉␉case 0x0DE1: // GT 430␊ |
1372 | ␉␉case 0x0DE2: // GT 420␊ |
1373 | ␉␉case 0x0DEC: // GT 525M␊ |
1374 | ␉␉case 0x0DF4: // GT 540M␊ |
1375 | ␉␉case 0x0DF5: // GT 525M␊ |
1376 | ␉␉␉vram_size = 1024*1024*1024; // 1 GB␊ |
1377 | ␉␉␉break;␊ |
1378 | ␉␉case 0x1251: // GTX 560M␊ |
1379 | ␉␉␉vram_size = 1536*1024*1024; // 1.5 GB␊ |
1380 | ␉␉␉break;␊ |
1381 | ␉␉default:␊ |
1382 | ␉␉␉break;␊ |
1383 | ␉}␊ |
1384 | ␊ |
1385 | ␉if (!vram_size) ␊ |
1386 | ␉{ // Finally, if vram_size still not set do the calculation with our own method␊ |
1387 | ␉␉if (nvCardType < NV_ARCH_50)␊ |
1388 | ␉␉{␊ |
1389 | ␉␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
1390 | ␉␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊ |
1391 | ␉␉}␊ |
1392 | ␉␉else if (nvCardType < NV_ARCH_C0)␊ |
1393 | ␉␉{␊ |
1394 | ␉␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
1395 | ␉␉␉vram_size |= (vram_size & 0xff) << 32;␊ |
1396 | ␉␉␉vram_size &= 0xffffffff00ll;␊ |
1397 | ␉␉}␊ |
1398 | ␉␉else // >= NV_ARCH_C0␊ |
1399 | ␉␉{␊ |
1400 | ␉␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊ |
1401 | ␉␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊ |
1402 | ␉␉}␊ |
1403 | ␉}␊ |
1404 | ␊ |
1405 | ␉return vram_size;␊ |
1406 | }␊ |
1407 | ␊ |
1408 | static bool checkNvRomSig(uint8_t * aRom){␊ |
1409 | return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);␊ |
1410 | }␊ |
1411 | ␊ |
1412 | bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊ |
1413 | {␊ |
1414 | ␉struct DevPropDevice␉*device;␊ |
1415 | ␉char␉␉␉␉␉*devicepath;␊ |
1416 | ␉option_rom_pci_header_t *rom_pci_header;␊ |
1417 | ␉volatile uint8_t␉␉*regs;␊ |
1418 | ␉uint8_t␉␉␉␉␉*rom;␊ |
1419 | ␉uint8_t␉␉␉␉␉*nvRom;␊ |
1420 | ␉uint8_t␉␉␉␉␉nvCardType;␊ |
1421 | ␉unsigned long long␉␉videoRam;␊ |
1422 | ␉uint32_t␉␉␉␉nvBiosOveride;␊ |
1423 | ␉uint32_t␉␉␉␉bar[7];␊ |
1424 | ␉uint32_t␉␉␉␉boot_display;␊ |
1425 | ␉int␉␉␉␉␉␉nvPatch;␊ |
1426 | ␉int␉␉␉␉␉␉len;␊ |
1427 | ␉char␉␉␉␉␉biosVersion[32];␊ |
1428 | ␉char␉␉␉␉␉nvFilename[32];␊ |
1429 | ␉char␉␉␉␉␉kNVCAP[12];␊ |
1430 | ␉char␉␉␉␉␉*model;␊ |
1431 | ␉const char␉␉␉␉*value;␊ |
1432 | ␉bool␉␉␉␉␉doit;␊ |
1433 | ␊ |
1434 | ␉fill_card_list();␊ |
1435 | ␊ |
1436 | ␉devicepath = get_pci_dev_path(nvda_dev);␊ |
1437 | ␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊ |
1438 | ␉regs = (uint8_t *) (bar[0] & ~0x0f);␊ |
1439 | ␊ |
1440 | ␉// get card type␊ |
1441 | ␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊ |
1442 | ␊ |
1443 | ␉model = get_nvidia_model(((nvda_dev->vendor_id << 16) | nvda_dev->device_id),((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id));␊ |
1444 | ␊ |
1445 | ␉// Amount of VRAM in kilobytes␊ |
1446 | ␉videoRam = mem_detect(regs, nvCardType, nvda_dev,((nvda_dev->vendor_id << 16) | nvda_dev->device_id),((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id) );␊ |
1447 | ␊ |
1448 | ␉rom = malloc(NVIDIA_ROM_SIZE);␊ |
1449 | ␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊ |
1450 | ␉␉␉(uint16_t)nvda_dev->device_id);␊ |
1451 | ␊ |
1452 | ␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)␊ |
1453 | ␉{␊ |
1454 | ␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊ |
1455 | ␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊ |
1456 | ␊ |
1457 | ␉␉if (nvBiosOveride > 0)␊ |
1458 | ␉␉{␊ |
1459 | ␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊ |
1460 | ␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊ |
1461 | ␉␉}␊ |
1462 | ␉␉else␊ |
1463 | ␉␉{␊ |
1464 | ␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊ |
1465 | ␉␉␉return false;␊ |
1466 | ␉␉}␊ |
1467 | ␉}␊ |
1468 | ␉else␊ |
1469 | ␉{␊ |
1470 | ␉␉// Otherwise read bios from card␊ |
1471 | ␉␉nvBiosOveride = 0;␊ |
1472 | ␊ |
1473 | // PROM first␊ |
1474 | // Enable PROM access␊ |
1475 | (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊ |
1476 | nvRom = (uint8_t*)®s[NV_PROM_OFFSET];␊ |
1477 | ␊ |
1478 | // Valid Signature ?␊ |
1479 | ␉␉if (checkNvRomSig(nvRom))␊ |
1480 | ␉␉{␊ |
1481 | bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
1482 | DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1483 | }␊ |
1484 | else␊ |
1485 | {␊ |
1486 | ␊ |
1487 | // disable PROM access␊ |
1488 | (REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊ |
1489 | ␊ |
1490 | ␉ //PRAM next␊ |
1491 | nvRom = (uint8_t*)®s[NV_PRAMIN_OFFSET];␊ |
1492 | ␊ |
1493 | if(checkNvRomSig(nvRom))␊ |
1494 | {␊ |
1495 | bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
1496 | DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1497 | }␊ |
1498 | else␊ |
1499 | ␉␉{␊ |
1500 | ␉␉␉␉// 0xC0000 last␊ |
1501 | ␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊ |
1502 | ␉␉␉␉␊ |
1503 | ␉␉␉␉// Valid Signature ?␊ |
1504 | ␉␉␉␉if (!checkNvRomSig(rom))␊ |
1505 | ␉␉␉␉{␊ |
1506 | ␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊ |
1507 | ␉␉␉␉␉return false;␊ |
1508 | ␉␉␉␉}␊ |
1509 | else␊ |
1510 | {␊ |
1511 | DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1512 | }␊ |
1513 | ␉␉␉}//end PRAM check␊ |
1514 | }//end PROM check␊ |
1515 | ␉}//end load rom from bios␊ |
1516 | ␊ |
1517 | ␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED)␊ |
1518 | ␉{␊ |
1519 | ␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊ |
1520 | ␉␉//return false;␊ |
1521 | ␉}␊ |
1522 | ␊ |
1523 | ␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊ |
1524 | ␊ |
1525 | ␉// check for 'PCIR' sig␊ |
1526 | ␉if (rom_pci_header->signature == 0x50434952)␊ |
1527 | ␉{␊ |
1528 | ␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊ |
1529 | ␉␉{␊ |
1530 | ␉␉␉// Get Model from the OpROM␊ |
1531 | ␉␉␉model = get_nvidia_model(((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id), NV_SUB_IDS);␊ |
1532 | ␊ |
1533 | ␉␉␉// Get VRAM again␊ |
1534 | ␉␉␉videoRam = mem_detect(regs, nvCardType, nvda_dev,((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id), NV_SUB_IDS );␊ |
1535 | ␊ |
1536 | ␉␉}␊ |
1537 | ␉␉else␊ |
1538 | ␉␉{␊ |
1539 | ␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊ |
1540 | ␉␉}␊ |
1541 | ␉}␊ |
1542 | ␊ |
1543 | ␉verbose("%s %dMB NV%02x [%04x:%04x]-[%04x:%04x] :: %s device number: %d\n",␊ |
1544 | ␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊ |
1545 | ␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊ |
1546 | ␉␉␉nvda_dev->subsys_id.subsys.vendor_id, nvda_dev->subsys_id.subsys.device_id,␊ |
1547 | ␉␉␉devicepath, devices_number);␊ |
1548 | ␊ |
1549 | ␉if (!string) {␊ |
1550 | ␉␉string = devprop_create_string();␊ |
1551 | ␉}␊ |
1552 | ␉device = devprop_add_device(string, devicepath);␊ |
1553 | ␊ |
1554 | ␉/* FIXME: for primary graphics card only */␊ |
1555 | ␉boot_display = 1;␊ |
1556 | ␉if (devices_number == 1)␊ |
1557 | ␉{␊ |
1558 | ␉␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊ |
1559 | ␉}␊ |
1560 | ␊ |
1561 | ␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊ |
1562 | ␉␉uint8_t built_in = 0x01;␊ |
1563 | ␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊ |
1564 | ␉}␊ |
1565 | ␊ |
1566 | ␉// get bios version␊ |
1567 | ␉const int MAX_BIOS_VERSION_LENGTH = 32;␊ |
1568 | ␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊ |
1569 | ␊ |
1570 | ␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊ |
1571 | ␊ |
1572 | ␉int i, version_start;␊ |
1573 | ␉int crlf_count = 0;␊ |
1574 | ␊ |
1575 | ␉// only search the first 384 bytes␊ |
1576 | ␉for (i = 0; i < 0x180; i++)␊ |
1577 | ␉{␊ |
1578 | ␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊ |
1579 | ␉␉{␊ |
1580 | ␉␉␉crlf_count++;␊ |
1581 | ␉␉␉// second 0x0D0A was found, extract bios version␊ |
1582 | ␉␉␉if (crlf_count == 2)␊ |
1583 | ␉␉␉{␊ |
1584 | ␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊ |
1585 | ␊ |
1586 | ␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊ |
1587 | ␉␉␉␉{␊ |
1588 | ␉␉␉␉␉// find start␊ |
1589 | ␉␉␉␉␉if (rom[version_start] == 0x00)␊ |
1590 | ␉␉␉␉␉{␊ |
1591 | ␉␉␉␉␉␉version_start++;␊ |
1592 | ␊ |
1593 | ␉␉␉␉␉␉// strip "Version "␊ |
1594 | ␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊ |
1595 | ␉␉␉␉␉␉{␊ |
1596 | ␉␉␉␉␉␉␉version_start += 8;␊ |
1597 | ␉␉␉␉␉␉}␊ |
1598 | ␉␉␉␉␉␉␊ |
1599 | ␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊ |
1600 | ␉␉␉␉␉␉break;␊ |
1601 | ␉␉␉␉␉}␊ |
1602 | ␉␉␉␉}␊ |
1603 | ␉␉␉␉break;␊ |
1604 | ␉␉␉}␊ |
1605 | ␉␉}␊ |
1606 | ␉}␊ |
1607 | ␉␊ |
1608 | ␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊ |
1609 | ␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊ |
1610 | ␊ |
1611 | ␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2)␊ |
1612 | ␉{␊ |
1613 | ␉␉uint8_t new_NVCAP[NVCAP_LEN];␊ |
1614 | ␊ |
1615 | ␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊ |
1616 | ␉␉{␊ |
1617 | ␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊ |
1618 | ␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊ |
1619 | ␉␉}␊ |
1620 | ␉}␊ |
1621 | ␊ |
1622 | ␉if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2)␊ |
1623 | ␉{␊ |
1624 | ␉␉uint8_t new_dcfg0[DCFG0_LEN];␊ |
1625 | ␊ |
1626 | ␉␉if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0)␊ |
1627 | ␉␉{␊ |
1628 | ␉␉␉memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);␊ |
1629 | ␊ |
1630 | ␉␉␉verbose("Using user supplied @0,display-cfg\n");␊ |
1631 | ␉␉␉printf("@0,display-cfg: %02x%02x%02x%02x\n",␊ |
1632 | ␉␉␉␉ default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);␊ |
1633 | ␉␉}␊ |
1634 | ␉}␊ |
1635 | ␊ |
1636 | ␉if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2)␊ |
1637 | ␉{␊ |
1638 | ␉␉uint8_t new_dcfg1[DCFG1_LEN];␊ |
1639 | ␊ |
1640 | ␉␉if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0)␊ |
1641 | ␉␉{␊ |
1642 | ␉␉␉memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);␊ |
1643 | ␊ |
1644 | ␉␉␉verbose("Using user supplied @1,display-cfg\n");␊ |
1645 | ␉␉␉printf("@1,display-cfg: %02x%02x%02x%02x\n",␊ |
1646 | ␉␉␉␉ default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);␊ |
1647 | ␉␉}␊ |
1648 | ␉}␊ |
1649 | ␊ |
1650 | #if DEBUG_NVCAP␊ |
1651 | ␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊ |
1652 | ␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊ |
1653 | ␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊ |
1654 | ␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊ |
1655 | ␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊ |
1656 | ␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊ |
1657 | #endif␊ |
1658 | ␉␊ |
1659 | ␉devprop_add_nvidia_template(device);␊ |
1660 | ␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊ |
1661 | ␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊ |
1662 | ␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊ |
1663 | ␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊ |
1664 | ␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊ |
1665 | ␉devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);␊ |
1666 | ␉devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);␊ |
1667 | ␊ |
1668 | ␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit)␊ |
1669 | ␉{␊ |
1670 | ␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊ |
1671 | ␉}␊ |
1672 | ␊ |
1673 | ␉//add HDMI Audio back to nvidia␊ |
1674 | ␉doit = false;␊ |
1675 | ␉//http://forge.voodooprojects.org/p/chameleon/issues/67/␊ |
1676 | ␉if(getBoolForKey(kEnableHDMIAudio, &doit, &bootInfo->chameleonConfig) && doit)␊ |
1677 | ␉{␊ |
1678 | ␉␉static uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};␊ |
1679 | ␉␉devprop_add_value(device, "@1,connector-type",connector_type_1, 4);␊ |
1680 | ␉}␊ |
1681 | ␉//end Nvidia HDMI Audio␊ |
1682 | ␊ |
1683 | ␉stringdata = malloc(sizeof(uint8_t) * string->length);␊ |
1684 | ␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊ |
1685 | ␉stringlength = string->length;␊ |
1686 | ␊ |
1687 | ␉free(rom);␊ |
1688 | ␉return true;␊ |
1689 | }␊ |
1690 | |