| 1 | /*␊ |
| 2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
| 3 | * AsereBLN: 2009: cleanup and bugfix␊ |
| 4 | */␊ |
| 5 | ␊ |
| 6 | #ifndef __LIBSAIO_CPU_H␊ |
| 7 | #define __LIBSAIO_CPU_H␊ |
| 8 | ␊ |
| 9 | #include "platform.h"␊ |
| 10 | ␊ |
| 11 | extern void scan_cpu(PlatformInfo_t *);␊ |
| 12 | ␊ |
| 13 | #define bit(n)␉␉␉(1ULL << (n))␊ |
| 14 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
| 15 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
| 16 | ␊ |
| 17 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
| 18 | ␊ |
| 19 | #define MSR_IA32_PLATFORM_ID 0x17␊ |
| 20 | #define␉MSR_IA32_PERF_STATUS 0x198␊ |
| 21 | #define MSR_IA32_PERF_CONTROL 0x199␊ |
| 22 | #define MSR_IA32_EXT_CONFIG 0xEE␊ |
| 23 | #define MSR_PKG_CST_CONFIG_CTL 0xE2␊ |
| 24 | #define MSR_FLEX_RATIO 0x194␊ |
| 25 | #define MSR_TURBO_RATIO_LIMIT 0x1AD␊ |
| 26 | #define␉MSR_PLATFORM_INFO 0xCE␊ |
| 27 | #define MSR_CORE_THREAD_COUNT 0x35␉␉␉// Undocumented␊ |
| 28 | ␊ |
| 29 | #define K8_FIDVID_STATUS 0xC0010042␊ |
| 30 | #define K10_COFVID_STATUS 0xC0010071␊ |
| 31 | ␊ |
| 32 | #define MSR_AMD_MPERF 0x000000E7␊ |
| 33 | #define MSR_AMD_APERF 0x000000E8␊ |
| 34 | ␊ |
| 35 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
| 36 | ␊ |
| 37 | // DFE: This constant comes from older xnu:␊ |
| 38 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
| 39 | ␊ |
| 40 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
| 41 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
| 42 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
| 43 | ␊ |
| 44 | // CPUID Values␊ |
| 45 | ␊ |
| 46 | #define CPUID_MODEL_PRESCOTT␉␉3 // 0x03 Celeron D, Pentium 4 (90nm)␊ |
| 47 | #define CPUID_MODEL_NOCONA␉␉4 // 0x04 Xeon Nocona, Irwindale (90nm)␊ |
| 48 | #define CPUID_MODEL_PRESLER␉␉6 // 0x06 Pentium 4, Pentium D (65nm)␊ |
| 49 | #define CPUID_MODEL_PENTIUM_M␉␉9 // 0x09␊ |
| 50 | #define CPUID_MODEL_DOTHAN␉␉13 // 0x0D Dothan␊ |
| 51 | #define CPUID_MODEL_YONAH␉␉14 // 0x0E Intel Mobile Core Solo, Duo␊ |
| 52 | #define CPUID_MODEL_MEROM␉␉15 // 0x0F Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
| 53 | #define CPUID_MODEL_CONROE␉␉15 // 0x0F␊ |
| 54 | #define CPUID_MODEL_CELERON␉␉22 // 0x16␊ |
| 55 | #define CPUID_MODEL_PENRYN␉␉23 // 0x17 Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
| 56 | #define CPUID_MODEL_WOLFDALE␉␉23 // 0x17␊ |
| 57 | #define CPUID_MODEL_NEHALEM␉␉26 // 0x1A Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
| 58 | #define CPUID_MODEL_ATOM␉␉28 // 0x1C Intel Atom (45nm) Pineview, Silverthorne␊ |
| 59 | #define CPUID_MODEL_XEON_MP␉␉29 // 0x1D MP 7400␊ |
| 60 | #define CPUID_MODEL_FIELDS␉␉30 // 0x1E Intel Core i5, i7, Xeon X34xx LGA1156 (45nm),(Clarksfiled, Lynnfield, Jasper Forest)␊ |
| 61 | #define CPUID_MODEL_DALES␉␉31 // 0x1F Havendale, Auburndale␊ |
| 62 | #define CPUID_MODEL_CLARKDALE␉␉37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale)␊ |
| 63 | #define CPUID_MODEL_ATOM_SAN␉␉38 // 0x26␊ |
| 64 | #define CPUID_MODEL_LINCROFT␉␉39 // 0x27 Intel Atom (45nm) Z6xx (single core)␊ |
| 65 | #define CPUID_MODEL_SANDYBRIDGE␉␉42 // 0x2A Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
| 66 | #define CPUID_MODEL_WESTMERE␉␉44 // 0x2C Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
| 67 | #define CPUID_MODEL_JAKETOWN␉␉45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP␊ |
| 68 | #define CPUID_MODEL_NEHALEM_EX␉␉46 // 0x2E Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
| 69 | #define CPUID_MODEL_WESTMERE_EX␉␉47 // 0x2F Intel Xeon E7␊ |
| 70 | #define CPUID_MODEL_ATOM_2000␉␉54 // 0x36 Intel Atom (32nm) Cedarview␊ |
| 71 | #define CPUID_MODEL_IVYBRIDGE␉␉58 // 0x3A Intel Core i5, i7 LGA1155 (22nm)␊ |
| 72 | #define CPUID_MODEL_HASWELL␉␉60 // 0x3C␊ |
| 73 | #define CPUID_MODEL_IVY_BRIDGE_E5␉62 // 0x3E␊ |
| 74 | ␊ |
| 75 | static inline uint64_t rdtsc64(void)␊ |
| 76 | {␊ |
| 77 | ␉uint64_t ret;␊ |
| 78 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
| 79 | ␉return ret;␊ |
| 80 | }␊ |
| 81 | ␊ |
| 82 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
| 83 | {␊ |
| 84 | uint64_t ret;␊ |
| 85 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
| 86 | return ret;␊ |
| 87 | }␊ |
| 88 | ␊ |
| 89 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
| 90 | {␊ |
| 91 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
| 92 | }␊ |
| 93 | ␊ |
| 94 | static inline void intel_waitforsts(void) {␊ |
| 95 | ␉uint32_t inline_timeout = 100000;␊ |
| 96 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
| 97 | }␊ |
| 98 | ␊ |
| 99 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
| 100 | {␊ |
| 101 | ␉asm volatile ("cpuid"␊ |
| 102 | ␉␉␉␉ : "=a" (data[0]),␊ |
| 103 | ␉␉␉␉ "=b" (data[1]),␊ |
| 104 | ␉␉␉␉ "=c" (data[2]),␊ |
| 105 | ␉␉␉␉ "=d" (data[3])␊ |
| 106 | ␉␉␉␉ : "a" (selector));␊ |
| 107 | }␊ |
| 108 | ␊ |
| 109 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
| 110 | {␊ |
| 111 | ␉asm volatile ("cpuid"␊ |
| 112 | ␉␉␉␉ : "=a" (data[0]),␊ |
| 113 | ␉␉␉␉ "=b" (data[1]),␊ |
| 114 | ␉␉␉␉ "=c" (data[2]),␊ |
| 115 | ␉␉␉␉ "=d" (data[3])␊ |
| 116 | ␉␉␉␉ : "a" (selector), "c" (selector2));␊ |
| 117 | }␊ |
| 118 | ␊ |
| 119 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
| 120 | ␊ |
| 121 | /*␊ |
| 122 | * Enable or disable timer 2.␊ |
| 123 | * Port 0x61 controls timer 2:␊ |
| 124 | * bit 0 gates the clock,␊ |
| 125 | * bit 1 gates output to speaker.␊ |
| 126 | */␊ |
| 127 | static inline void enable_PIT2(void)␊ |
| 128 | {␊ |
| 129 | /* Enable gate, disable speaker */␊ |
| 130 | __asm__ volatile(␊ |
| 131 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
| 132 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
| 133 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
| 134 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
| 135 | ␉␉␉␉␉ : : : "%al" );␊ |
| 136 | }␊ |
| 137 | ␊ |
| 138 | static inline void disable_PIT2(void)␊ |
| 139 | {␊ |
| 140 | /* Disable gate and output to speaker */␊ |
| 141 | __asm__ volatile(␊ |
| 142 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
| 143 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
| 144 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
| 145 | ␉␉␉␉␉ : : : "%al" );␊ |
| 146 | }␊ |
| 147 | ␊ |
| 148 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
| 149 | // roughly based on Linux code␊ |
| 150 | ␊ |
| 151 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
| 152 | In mode 0, the counter will initially set its gate low when the␊ |
| 153 | timer expires. For this to be useful, you ought to set it high␊ |
| 154 | before calling this function. The enable_PIT2 function does this.␊ |
| 155 | */␊ |
| 156 | static inline void set_PIT2_mode0(uint16_t value)␊ |
| 157 | {␊ |
| 158 | __asm__ volatile(␊ |
| 159 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
| 160 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
| 161 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
| 162 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
| 163 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
| 164 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
| 165 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
| 166 | }␊ |
| 167 | ␊ |
| 168 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
| 169 | static inline unsigned long poll_PIT2_gate(void)␊ |
| 170 | {␊ |
| 171 | unsigned long count = 0;␊ |
| 172 | unsigned char nmi_sc_val;␊ |
| 173 | do {␊ |
| 174 | ++count;␊ |
| 175 | __asm__ volatile(␊ |
| 176 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
| 177 | ␉␉␉␉␉␉ : "=q"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
| 178 | } while( (nmi_sc_val & 0x20) == 0);␊ |
| 179 | return count;␊ |
| 180 | }␊ |
| 181 | ␊ |
| 182 | inline static void␊ |
| 183 | set_PIT2(int value)␊ |
| 184 | {␊ |
| 185 | /*␊ |
| 186 | * First, tell the clock we are going to write 16 bits to the counter␊ |
| 187 | * and enable one-shot mode (command 0xB8 to port 0x43)␊ |
| 188 | * Then write the two bytes into the PIT2 clock register (port 0x42).␊ |
| 189 | * Loop until the value is "realized" in the clock,␊ |
| 190 | * this happens on the next tick.␊ |
| 191 | */␊ |
| 192 | asm volatile(␊ |
| 193 | " movb $0xB8,%%al \n\t"␊ |
| 194 | " outb %%al,$0x43 \n\t"␊ |
| 195 | " movb %%dl,%%al \n\t"␊ |
| 196 | " outb %%al,$0x42 \n\t"␊ |
| 197 | " movb %%dh,%%al \n\t"␊ |
| 198 | " outb %%al,$0x42 \n"␊ |
| 199 | "1: inb $0x42,%%al \n\t" ␊ |
| 200 | " inb $0x42,%%al \n\t"␊ |
| 201 | " cmp %%al,%%dh \n\t"␊ |
| 202 | " jne 1b"␊ |
| 203 | : : "d"(value) : "%al");␊ |
| 204 | }␊ |
| 205 | ␊ |
| 206 | ␊ |
| 207 | inline static uint64_t␊ |
| 208 | get_PIT2(unsigned int *value)␊ |
| 209 | {␊ |
| 210 | register uint64_t result;␊ |
| 211 | /*␊ |
| 212 | * This routine first latches the time (command 0x80 to port 0x43),␊ |
| 213 | * then gets the time stamp so we know how long the read will take later.␊ |
| 214 | * Read (from port 0x42) and return the current value of the timer.␊ |
| 215 | */␊ |
| 216 | #ifdef __i386__␊ |
| 217 | asm volatile(␊ |
| 218 | " xorl %%ecx,%%ecx \n\t"␊ |
| 219 | " movb $0x80,%%al \n\t"␊ |
| 220 | " outb %%al,$0x43 \n\t"␊ |
| 221 | " rdtsc \n\t"␊ |
| 222 | " pushl %%eax \n\t"␊ |
| 223 | " inb $0x42,%%al \n\t"␊ |
| 224 | " movb %%al,%%cl \n\t"␊ |
| 225 | " inb $0x42,%%al \n\t"␊ |
| 226 | " movb %%al,%%ch \n\t"␊ |
| 227 | " popl %%eax "␊ |
| 228 | : "=A"(result), "=c"(*value));␊ |
| 229 | #else /* __x86_64__ */␊ |
| 230 | asm volatile(␊ |
| 231 | ␉␉" xorq %%rcx,%%rcx \n\t"␊ |
| 232 | ␉␉" movb $0x80,%%al \n\t"␊ |
| 233 | ␉␉" outb %%al,$0x43 \n\t"␊ |
| 234 | ␉␉" rdtsc \n\t"␊ |
| 235 | ␉␉" pushq %%rax \n\t"␊ |
| 236 | ␉␉" inb $0x42,%%al \n\t"␊ |
| 237 | ␉␉" movb %%al,%%cl \n\t"␊ |
| 238 | ␉␉" inb $0x42,%%al \n\t"␊ |
| 239 | ␉␉" movb %%al,%%ch \n\t"␊ |
| 240 | ␉␉" popq %%rax "␊ |
| 241 | ␉␉: "=A"(result), "=c"(*value));␊ |
| 242 | #endif␊ |
| 243 | ␊ |
| 244 | return result;␊ |
| 245 | }␊ |
| 246 | ␊ |
| 247 | #endif /* !__LIBSAIO_CPU_H */␊ |
| 248 | |
