1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | #include "cpu.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "boot.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␉␉msglog(x)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * timeRDTSC()␊ |
24 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
25 | * It pauses until the value is latched in the counter␊ |
26 | * and then reads the time stamp counter to return to the caller.␊ |
27 | */␊ |
28 | uint64_t timeRDTSC(void)␊ |
29 | {␊ |
30 | ␉int␉␉attempts = 0;␊ |
31 | ␉uint64_t latchTime;␊ |
32 | ␉uint64_t␉saveTime,intermediate;␊ |
33 | ␉unsigned int timerValue, lastValue;␊ |
34 | ␉//boolean_t␉int_enabled;␊ |
35 | ␉/*␊ |
36 | ␉ * Table of correction factors to account for␊ |
37 | ␉ *␉ - timer counter quantization errors, and␊ |
38 | ␉ *␉ - undercounts 0..5␊ |
39 | ␉ */␊ |
40 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
41 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
42 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
43 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
44 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
45 | ␉uint64_t␉scale[6] = {␊ |
46 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
47 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
48 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
49 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
50 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
51 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
52 | ␉};␊ |
53 | ␊ |
54 | restart:␊ |
55 | ␉if (attempts >= 9) // increase to up to 9 attempts.␊ |
56 | ␉{␊ |
57 | ␉ // This will flash-reboot. TODO: Use tscPanic instead.␊ |
58 | ␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
59 | ␉}␊ |
60 | attempts++;␊ |
61 | enable_PIT2();␉␉// turn on PIT2␊ |
62 | set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
63 | latchTime = rdtsc64();␉// get the time stamp to time ␊ |
64 | latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
65 | set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
66 | saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
67 | get_PIT2(&lastValue);␊ |
68 | get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
69 | do {␊ |
70 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
71 | ␉␉if (timerValue > lastValue) {␊ |
72 | ␉␉␉// Timer wrapped␊ |
73 | ␉␉␉set_PIT2(0);␊ |
74 | ␉␉␉disable_PIT2();␊ |
75 | ␉␉␉goto restart;␊ |
76 | ␉␉}␊ |
77 | ␉␉lastValue = timerValue;␊ |
78 | } while (timerValue > 5);␊ |
79 | printf("timerValue␉ %d\n",timerValue);␊ |
80 | printf("intermediate 0x%016llx\n",intermediate);␊ |
81 | printf("saveTime␉ 0x%016llx\n",saveTime);␊ |
82 | ␊ |
83 | intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
84 | intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
85 | intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
86 | intermediate += latchTime;␉␉// add on our save fudge␊ |
87 | ␊ |
88 | set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
89 | disable_PIT2();␉␉␉// turn off PIT 2␊ |
90 | ␉␊ |
91 | return intermediate;␊ |
92 | }␊ |
93 | ␊ |
94 | /*␊ |
95 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
96 | */␊ |
97 | static uint64_t measure_tsc_frequency(void)␊ |
98 | {␊ |
99 | ␉uint64_t tscStart;␊ |
100 | ␉uint64_t tscEnd;␊ |
101 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
102 | ␉unsigned long pollCount;␊ |
103 | ␉uint64_t retval = 0;␊ |
104 | ␉int i;␊ |
105 | ␉␊ |
106 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
107 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
108 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
109 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
110 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
111 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
112 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
113 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
114 | ␉ */␊ |
115 | ␉for(i = 0; i < 10; ++i)␊ |
116 | ␉{␊ |
117 | ␉␉enable_PIT2();␊ |
118 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
119 | ␉␉tscStart = rdtsc64();␊ |
120 | ␉␉pollCount = poll_PIT2_gate();␊ |
121 | ␉␉tscEnd = rdtsc64();␊ |
122 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
123 | ␉␉if (pollCount <= 1)␊ |
124 | ␉␉␉continue;␊ |
125 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
126 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
127 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
128 | ␉␉ */␊ |
129 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
130 | ␉␉␉continue;␊ |
131 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
132 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
133 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
134 | ␉}␊ |
135 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
136 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
137 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
138 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
139 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
140 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
141 | ␉ */␊ |
142 | ␊ |
143 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
144 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
145 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
146 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
147 | ␉ */␊ |
148 | ␉if (tscDelta > (1ULL<<32))␊ |
149 | ␉␉retval = 0;␊ |
150 | ␉else␊ |
151 | ␉{␊ |
152 | ␉␉retval = tscDelta * 1000 / 30;␊ |
153 | ␉}␊ |
154 | ␉disable_PIT2();␊ |
155 | ␉return retval;␊ |
156 | }␊ |
157 | ␊ |
158 | /*␊ |
159 | * Original comment/code:␊ |
160 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
161 | *␊ |
162 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
163 | * (just a naming change, mperf --> aperf )␊ |
164 | */␊ |
165 | static uint64_t measure_aperf_frequency(void)␊ |
166 | {␊ |
167 | ␉uint64_t aperfStart;␊ |
168 | ␉uint64_t aperfEnd;␊ |
169 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
170 | ␉unsigned long pollCount;␊ |
171 | ␉uint64_t retval = 0;␊ |
172 | ␉int i;␊ |
173 | ␉␊ |
174 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
175 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
176 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
177 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
178 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
179 | ␉ * expire.␊ |
180 | ␉ */␊ |
181 | ␉for(i = 0; i < 10; ++i)␊ |
182 | ␉{␊ |
183 | ␉␉enable_PIT2();␊ |
184 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
185 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
186 | ␉␉pollCount = poll_PIT2_gate();␊ |
187 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
188 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
189 | ␉␉if (pollCount <= 1)␊ |
190 | ␉␉␉continue;␊ |
191 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
192 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
193 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
194 | ␉␉ */␊ |
195 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
196 | ␉␉␉continue;␊ |
197 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
198 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
199 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
200 | ␉}␊ |
201 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
202 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
203 | ␉ */␊ |
204 | ␉␊ |
205 | ␉if (aperfDelta > (1ULL<<32))␊ |
206 | ␉␉retval = 0;␊ |
207 | ␉else␊ |
208 | ␉{␊ |
209 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
210 | ␉}␊ |
211 | ␉disable_PIT2();␊ |
212 | ␉return retval;␊ |
213 | }␊ |
214 | ␊ |
215 | /*␊ |
216 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
217 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
218 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
219 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
220 | * - fsbFrequency = tscFrequency / multi␊ |
221 | * - cpuFrequency = fsbFrequency * multi␊ |
222 | */␊ |
223 | void scan_cpu(PlatformInfo_t *p)␊ |
224 | {␊ |
225 | ␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊ |
226 | ␉uint64_t␉msr, flex_ratio;␊ |
227 | ␉uint8_t␉␉maxcoef, maxdiv, currcoef, bus_ratio_max, currdiv;␊ |
228 | ␉const char␉*newratio;␊ |
229 | ␉int␉␉␉len, myfsb;␊ |
230 | ␉uint8_t␉␉bus_ratio_min;␊ |
231 | ␉uint32_t␉max_ratio, min_ratio;␊ |
232 | ␊ |
233 | ␉max_ratio = min_ratio = myfsb = bus_ratio_min = 0;␊ |
234 | ␉maxcoef = maxdiv = bus_ratio_max = currcoef = currdiv = 0;␊ |
235 | ␊ |
236 | ␉/* get cpuid values */␊ |
237 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
238 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
239 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊ |
240 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊ |
241 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
242 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
243 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5) {␊ |
244 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
245 | ␉}␊ |
246 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 6) {␊ |
247 | ␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
248 | ␉}␊ |
249 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8) {␊ |
250 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
251 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
252 | ␉}␊ |
253 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊ |
254 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
255 | ␉}␊ |
256 | ␊ |
257 | #if DEBUG_CPU␊ |
258 | ␉{␊ |
259 | ␉␉int␉␉i;␊ |
260 | ␉␉printf("CPUID Raw Values:\n");␊ |
261 | ␉␉for (i=0; i<CPUID_MAX; i++) {␊ |
262 | ␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
263 | ␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
264 | ␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
265 | ␉␉}␊ |
266 | ␉}␊ |
267 | #endif␊ |
268 | ␊ |
269 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
270 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
271 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
272 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
273 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
274 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
275 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
276 | ␊ |
277 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
278 | ␊ |
279 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊ |
280 | ␉␉p->CPU.Family == 0x06 &&␊ |
281 | ␉␉p->CPU.Model >= CPU_MODEL_NEHALEM &&␊ |
282 | ␉␉p->CPU.Model != CPU_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
283 | ␉␉)␊ |
284 | ␉{␊ |
285 | ␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊ |
286 | ␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉// Using undocumented MSR to get actual values␊ |
287 | ␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉// Using undocumented MSR to get actual values␊ |
288 | ␉}␊ |
289 | ␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊ |
290 | ␉{␊ |
291 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
292 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
293 | ␉}␊ |
294 | ␉else␊ |
295 | ␉{␊ |
296 | ␉␉// Use previous method for Cores and Threads␊ |
297 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
298 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
299 | ␉}␊ |
300 | ␊ |
301 | ␉/* get brand string (if supported) */␊ |
302 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
303 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊ |
304 | ␉␉uint32_t␉reg[4];␊ |
305 | ␉␉char␉␉str[128], *s;␊ |
306 | ␉␉/*␊ |
307 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
308 | ␉␉ * be NULL terminated.␊ |
309 | ␉␉ */␊ |
310 | ␉␉do_cpuid(0x80000002, reg);␊ |
311 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
312 | ␉␉do_cpuid(0x80000003, reg);␊ |
313 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
314 | ␉␉do_cpuid(0x80000004, reg);␊ |
315 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
316 | ␉␉for (s = str; *s != '\0'; s++) {␊ |
317 | ␉␉␉if (*s != ' ') break;␊ |
318 | ␉␉}␊ |
319 | ␉␉␊ |
320 | ␉␉strlcpy(p->CPU.BrandString, s, sizeof(p->CPU.BrandString));␊ |
321 | ␉␉␊ |
322 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊ |
323 | ␉␉␉/*␊ |
324 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
325 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
326 | ␉␉␉ */␊ |
327 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
328 | ␉␉}␊ |
329 | ␉}␊ |
330 | ␉␊ |
331 | ␉/* setup features */␊ |
332 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
333 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
334 | ␉}␊ |
335 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
336 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
337 | ␉}␊ |
338 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
339 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
340 | ␉}␊ |
341 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
342 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
343 | ␉}␊ |
344 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
345 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
346 | ␉}␊ |
347 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0) {␊ |
348 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
349 | ␉}␊ |
350 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0) {␊ |
351 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
352 | ␉}␊ |
353 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
354 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
355 | ␉}␊ |
356 | ␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
357 | ␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊ |
358 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
359 | ␉}␊ |
360 | ␊ |
361 | ␉tscFrequency = measure_tsc_frequency();␊ |
362 | ␉/* if usual method failed */␊ |
363 | ␉if ( tscFrequency < 1000 )␊ |
364 | ␉{␊ |
365 | ␉tscFrequency = timeRDTSC() * 20;␊ |
366 | ␉}␊ |
367 | ␉fsbFrequency = 0;␊ |
368 | ␉cpuFrequency = 0;␊ |
369 | ␊ |
370 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊ |
371 | ␉␉int intelCPU = p->CPU.Model;␊ |
372 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊ |
373 | ␉␉␉/* Nehalem CPU model */␊ |
374 | ␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊ |
375 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉||␊ |
376 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉||␊ |
377 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊ |
378 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊ |
379 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊ |
380 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊ |
381 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊ |
382 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN ||␊ |
383 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON␉||␊ |
384 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊ |
385 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL ||␊ |
386 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_MB ||␊ |
387 | ␉␉␉␉␉␉␉␉␉␉ //p->CPU.Model == CPU_MODEL_HASWELL_H ||␊ |
388 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊ |
389 | ␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULX ))␊ |
390 | ␉␉␉{␊ |
391 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
392 | ␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
393 | ␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
394 | ␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
395 | ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
396 | ␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
397 | ␉␉␉␉if (bitfield(msr, 16, 16)) {␊ |
398 | ␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
399 | ␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
400 | ␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
401 | ␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
402 | ␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
403 | ␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
404 | ␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
405 | ␉␉␉␉␉ is inadvertently set to 0.␊ |
406 | ␉␉␉␉␉ */␊ |
407 | ␉␉␉␉␉if (flex_ratio == 0) {␊ |
408 | ␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
409 | ␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
410 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
411 | ␉␉␉␉␉␉verbose("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
412 | ␉␉␉␉␉} else {␊ |
413 | ␉␉␉␉␉␉if (bus_ratio_max > flex_ratio) {␊ |
414 | ␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
415 | ␉␉␉␉␉␉}␊ |
416 | ␉␉␉␉␉}␊ |
417 | ␉␉␉␉}␊ |
418 | ␊ |
419 | ␉␉␉␉if (bus_ratio_max) {␊ |
420 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
421 | ␉␉␉␉}␊ |
422 | ␉␉␉␉//valv: Turbo Ratio Limit␊ |
423 | ␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f)) {␊ |
424 | ␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
425 | ␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
426 | ␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
427 | ␉␉␉␉} else {␊ |
428 | ␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
429 | ␉␉␉␉}␊ |
430 | ␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4)) {␊ |
431 | ␉␉␉␉␉max_ratio = atoi(newratio);␊ |
432 | ␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
433 | ␉␉␉␉␉if (len >= 3) max_ratio = (max_ratio + 5);␊ |
434 | ␊ |
435 | ␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
436 | ␊ |
437 | ␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
438 | ␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320)) {␊ |
439 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
440 | ␉␉␉␉␉␉if (len >= 3) maxdiv = 1;␊ |
441 | ␉␉␉␉␉␉else maxdiv = 0;␊ |
442 | ␉␉␉␉␉} else {␊ |
443 | ␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
444 | ␉␉␉␉␉}␊ |
445 | ␉␉␉␉}␊ |
446 | ␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
447 | ␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
448 | ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
449 | ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
450 | ␊ |
451 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
452 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio);␊ |
453 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
454 | ␉␉␉} else {␊ |
455 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
456 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
457 | ␉␉␉␉currcoef = bitfield(msr, 12, 8);␊ |
458 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
459 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
460 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
461 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
462 | ␊ |
463 | ␉␉␉␉// This will always be model >= 3␊ |
464 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
465 | ␉␉␉␉{␊ |
466 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
467 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
468 | ␉␉␉␉} else {␊ |
469 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
470 | ␉␉␉␉␉/* XXX */␊ |
471 | ␉␉␉␉␉maxcoef = currcoef;␊ |
472 | ␉␉␉␉}␊ |
473 | ␊ |
474 | ␉␉␉␉if (maxcoef) {␊ |
475 | ␉␉␉␉␉if (maxdiv) {␊ |
476 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
477 | ␉␉␉␉␉} else {␊ |
478 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
479 | ␉␉␉␉␉}␊ |
480 | ␉␉␉␉␉if (currdiv) {␊ |
481 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
482 | ␉␉␉␉␉} else {␊ |
483 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
484 | ␉␉␉␉␉}␊ |
485 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
486 | ␉␉␉␉}␊ |
487 | ␉␉␉}␊ |
488 | ␉␉}␊ |
489 | ␉␉/* Mobile CPU */␊ |
490 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) {␊ |
491 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
492 | ␉␉}␊ |
493 | ␉}␊ |
494 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
495 | ␉{␊ |
496 | ␉␉switch(p->CPU.ExtFamily)␊ |
497 | ␉␉{␊ |
498 | ␉␉␉case 0x00: /* K8 */␊ |
499 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
500 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
501 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
502 | ␉␉␉␉break;␊ |
503 | ␊ |
504 | ␉␉␉case 0x01: /* K10 */␊ |
505 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
506 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
507 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
508 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
509 | ␉␉␉␉{␊ |
510 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
511 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
512 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
513 | ␉␉␉␉}␊ |
514 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
515 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
516 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
517 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
518 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
519 | ␊ |
520 | ␉␉␉␉break;␊ |
521 | ␊ |
522 | ␉␉␉case 0x05: /* K14 */␊ |
523 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
524 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
525 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
526 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
527 | ␊ |
528 | ␉␉␉␉break;␊ |
529 | ␊ |
530 | ␉␉␉case 0x02: /* K11 */␊ |
531 | ␉␉␉␉// not implimented␊ |
532 | ␉␉␉␉break;␊ |
533 | ␉␉}␊ |
534 | ␊ |
535 | ␉␉if (maxcoef)␊ |
536 | ␉␉{␊ |
537 | ␉␉␉if (currdiv)␊ |
538 | ␉␉␉{␊ |
539 | ␉␉␉␉if (!currcoef) currcoef = maxcoef;␊ |
540 | ␉␉␉␉if (!cpuFrequency)␊ |
541 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
542 | ␉␉␉␉else␊ |
543 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
544 | ␉␉␉␉␊ |
545 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
546 | ␉␉␉} else {␊ |
547 | ␉␉␉␉if (!cpuFrequency)␊ |
548 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
549 | ␉␉␉␉else ␊ |
550 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
551 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
552 | ␉␉␉}␊ |
553 | ␉␉}␊ |
554 | ␉␉else if (currcoef)␊ |
555 | ␉␉{␊ |
556 | ␉␉␉if (currdiv)␊ |
557 | ␉␉␉{␊ |
558 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
559 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
560 | ␉␉␉} else {␊ |
561 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
562 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
563 | ␉␉␉}␊ |
564 | ␉␉}␊ |
565 | ␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊ |
566 | ␉}␊ |
567 | ␉␊ |
568 | #if 0␊ |
569 | ␉if (!fsbFrequency) {␊ |
570 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
571 | ␉␉cpuFrequency = tscFrequency;␊ |
572 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
573 | ␉}␊ |
574 | #endif␊ |
575 | ␊ |
576 | ␉p->CPU.MaxCoef = maxcoef;␊ |
577 | ␉p->CPU.MaxDiv = maxdiv;␊ |
578 | ␉p->CPU.CurrCoef = currcoef;␊ |
579 | ␉p->CPU.CurrDiv = currdiv;␊ |
580 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
581 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
582 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
583 | ␊ |
584 | ␉// keep formatted with spaces instead of tabs␊ |
585 | ␉DBG("CPU: Brand String: %s\n", p->CPU.BrandString);␊ |
586 | DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n", p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊ |
587 | DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n", p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊ |
588 | DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n", p->CPU.MaxCoef, p->CPU.CurrCoef);␊ |
589 | DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n", p->CPU.MaxDiv, p->CPU.CurrDiv);␊ |
590 | DBG("CPU: TSCFreq: %dMHz\n", p->CPU.TSCFrequency / 1000000);␊ |
591 | DBG("CPU: FSBFreq: %dMHz\n", p->CPU.FSBFrequency / 1000000);␊ |
592 | DBG("CPU: CPUFreq: %dMHz\n", p->CPU.CPUFrequency / 1000000);␊ |
593 | DBG("CPU: NoCores/NoThreads: %d/%d\n", p->CPU.NoCores, p->CPU.NoThreads);␊ |
594 | DBG("CPU: Features: 0x%08x\n", p->CPU.Features);␊ |
595 | #if DEBUG_CPU␊ |
596 | ␉pause();␊ |
597 | #endif␊ |
598 | }␊ |
599 | |