1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
34 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_E5:␊ |
36 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
37 | ␉␉␉␉␉␉value->word = 0;␊ |
38 | ␉␉␉␉␉␉break;␊ |
39 | ␉␉␉␉␉default:␊ |
40 | ␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
41 | ␉␉␉␉}␊ |
42 | ␉␉␉}␊ |
43 | ␉␉␉␉break;␊ |
44 | ␊ |
45 | ␉␉␉default:␊ |
46 | ␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
47 | ␉␉}␊ |
48 | ␉}␊ |
49 | ␉else␊ |
50 | ␉{␊ |
51 | ␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
52 | ␉}␊ |
53 | ␊ |
54 | ␉return true;␊ |
55 | }␊ |
56 | ␊ |
57 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
58 | {␊ |
59 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
60 | ␉return true;␊ |
61 | }␊ |
62 | ␊ |
63 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
64 | {␊ |
65 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
66 | ␉{␉␉␊ |
67 | ␉␉switch (Platform.CPU.Family) ␊ |
68 | ␉␉{␊ |
69 | ␉␉␉case 0x06:␊ |
70 | ␉␉␉{␊ |
71 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
72 | ␉␉␉␉{␊ |
73 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
74 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
75 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
76 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
77 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
78 | ␉␉␉␉␉␉return false;␊ |
79 | ␊ |
80 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
81 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
82 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
83 | ␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
84 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
85 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
86 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
87 | ␉␉␉␉␉{␊ |
88 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
89 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
90 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
91 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
92 | ␉␉␉␉␉␉int i;␊ |
93 | ␉␉␉␉␉␉␊ |
94 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
95 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
96 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
97 | ␉␉␉␉␉␉{␊ |
98 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
99 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
100 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
101 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
102 | ␉␉␉␉␉␉␉␊ |
103 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
104 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
105 | ␉␉␉␉␉␉}␊ |
106 | ␉␉␉␉␉␉␊ |
107 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
108 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
109 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
110 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
111 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
112 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
113 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
114 | ␉␉␉␉␉␉{␊ |
115 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
116 | ␉␉␉␉␉␉}␊ |
117 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
118 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
119 | ␉␉␉␉␉␉return true;␊ |
120 | ␉␉␉␉␉}␊ |
121 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
122 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
123 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_E5:␊ |
124 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
125 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
126 | ␉␉␉␉␉{␊ |
127 | ␉␉␉␉␉␉int busspeed;␊ |
128 | ␉␉␉␉␉␉busspeed = 100;␊ |
129 | ␉␉␉␉␉␉value->word = busspeed;␊ |
130 | ␉␉␉␉␉␉return true;␊ |
131 | ␉␉␉␉␉}␊ |
132 | ␉␉␉␉}␊ |
133 | ␉␉␉}␊ |
134 | ␉␉}␊ |
135 | ␉}␊ |
136 | ␉return false;␊ |
137 | }␊ |
138 | ␊ |
139 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
140 | {␊ |
141 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
142 | ␉{␊ |
143 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
144 | ␉}␊ |
145 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
146 | ␉{␊ |
147 | ␉␉return 0x0201;␉// Core Solo␊ |
148 | ␉};␊ |
149 | ␉␊ |
150 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
151 | }␊ |
152 | ␊ |
153 | bool getSMBOemProcessorType(returnType *value)␊ |
154 | {␊ |
155 | ␉static bool done = false;␉␉␊ |
156 | ␊ |
157 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
158 | ␊ |
159 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
160 | ␉{␊ |
161 | ␉␉if (!done)␊ |
162 | ␉␉{␊ |
163 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
164 | ␉␉␉done = true;␊ |
165 | ␉␉}␊ |
166 | ␊ |
167 | ␉␉switch (Platform.CPU.Family) ␊ |
168 | ␉␉{␊ |
169 | ␉␉␉case 0x06:␊ |
170 | ␉␉␉{␊ |
171 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
172 | ␉␉␉␉{␊ |
173 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊ |
174 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
175 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
176 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
177 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
178 | ␉␉␉␉␉␉return true;␊ |
179 | ␊ |
180 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
181 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
182 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
183 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
184 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
185 | ␉␉␉␉␉␉{␊ |
186 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊ |
187 | ␉␉␉␉␉␉}␊ |
188 | ␉␉␉␉␉␉else␊ |
189 | ␉␉␉␉␉␉{␊ |
190 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
191 | ␉␉␉␉␉␉}␊ |
192 | ␉␉␉␉␉␉return true;␊ |
193 | ␊ |
194 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
195 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
196 | ␉␉␉␉␉␉{␊ |
197 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊ |
198 | ␉␉␉␉␉␉}␊ |
199 | ␉␉␉␉␉␉else␊ |
200 | ␉␉␉␉␉␉{␊ |
201 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
202 | ␉␉␉␉␉␉␉{␊ |
203 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊ |
204 | ␉␉␉␉␉␉␉}␊ |
205 | ␉␉␉␉␉␉␉else␊ |
206 | ␉␉␉␉␉␉␉{␊ |
207 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
208 | ␉␉␉␉␉␉␉}␊ |
209 | ␉␉␉␉␉␉}␊ |
210 | ␉␉␉␉␉␉return true;␊ |
211 | ␊ |
212 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
213 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
214 | ␉␉␉␉␉␉{␊ |
215 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
216 | ␉␉␉␉␉␉}␊ |
217 | ␉␉␉␉␉␉else␊ |
218 | ␉␉␉␉␉␉{␊ |
219 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
220 | ␉␉␉␉␉␉}␊ |
221 | ␉␉␉␉␉␉return true;␊ |
222 | ␊ |
223 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7, Xeon E3-12xx LGA1155 (32nm)␊ |
224 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
225 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_E5:␊ |
226 | ␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
227 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
228 | ␉␉␉␉␉␉{␊ |
229 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊ |
230 | ␉␉␉␉␉␉}␊ |
231 | ␉␉␉␉␉␉else if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
232 | ␉␉␉␉␉␉{␊ |
233 | ␉␉␉␉␉␉␉␉value->word = 0x0901;␉␉// Core i3␊ |
234 | ␉␉␉␉␉␉}␊ |
235 | ␉␉␉␉␉␉else if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
236 | ␉␉␉␉␉␉{␊ |
237 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊ |
238 | ␉␉␉␉␉␉}␊ |
239 | ␉␉␉␉␉␉else␊ |
240 | ␉␉␉␉␉␉{␊ |
241 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
242 | ␉␉␉␉␉␉}␊ |
243 | ␉␉␉␉␉␉return true;␊ |
244 | ␉␉␉␉}␊ |
245 | ␉␉␉}␊ |
246 | ␉␉}␊ |
247 | ␉}␊ |
248 | ␉␊ |
249 | ␉return false;␊ |
250 | }␊ |
251 | ␊ |
252 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
253 | {␊ |
254 | ␉static int idx = -1;␊ |
255 | ␉int␉map;␊ |
256 | ␊ |
257 | ␉idx++;␊ |
258 | ␉if (idx < MAX_RAM_SLOTS)␊ |
259 | ␉{␊ |
260 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
261 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
262 | ␉␉{␊ |
263 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
264 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
265 | ␉␉␉return true;␊ |
266 | ␉␉}␊ |
267 | ␉}␊ |
268 | ␉␊ |
269 | ␉return false;␊ |
270 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
271 | //␉return true;␊ |
272 | }␊ |
273 | ␊ |
274 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
275 | {␊ |
276 | value->word = 0xFFFF;␊ |
277 | return true;␊ |
278 | }␊ |
279 | ␊ |
280 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
281 | {␊ |
282 | ␉static int idx = -1;␊ |
283 | ␉int␉map;␊ |
284 | ␊ |
285 | ␉idx++;␊ |
286 | ␉if (idx < MAX_RAM_SLOTS)␊ |
287 | ␉{␊ |
288 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
289 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
290 | ␉␉{␊ |
291 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
292 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
293 | ␉␉␉return true;␊ |
294 | ␉␉}␊ |
295 | ␉}␊ |
296 | ␊ |
297 | ␉return false;␊ |
298 | //␉value->dword = 800;␊ |
299 | //␉return true;␊ |
300 | }␊ |
301 | ␊ |
302 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
303 | {␊ |
304 | ␉static int idx = -1;␊ |
305 | ␉int␉map;␊ |
306 | ␊ |
307 | ␉idx++;␊ |
308 | ␉if (idx < MAX_RAM_SLOTS)␊ |
309 | ␉{␊ |
310 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
311 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
312 | ␉␉{␊ |
313 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
314 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
315 | ␉␉␉return true;␊ |
316 | ␉␉}␊ |
317 | ␉}␊ |
318 | ␊ |
319 | ␉if (!bootInfo->memDetect)␊ |
320 | ␉{␊ |
321 | ␉␉return false;␊ |
322 | ␉}␊ |
323 | ␉value->string = NOT_AVAILABLE;␊ |
324 | ␉return true;␊ |
325 | }␊ |
326 | ␉␊ |
327 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
328 | {␊ |
329 | ␉static int idx = -1;␊ |
330 | ␉int␉map;␊ |
331 | ␊ |
332 | ␉idx++;␊ |
333 | ␊ |
334 | DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
335 | ␊ |
336 | ␉if (idx < MAX_RAM_SLOTS)␊ |
337 | ␉{␊ |
338 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
339 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
340 | ␉␉{␊ |
341 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
342 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
343 | ␉␉␉return true;␊ |
344 | ␉␉}␊ |
345 | ␉}␊ |
346 | ␊ |
347 | ␉if (!bootInfo->memDetect)␊ |
348 | ␉{␊ |
349 | ␉␉return false;␊ |
350 | ␉}␊ |
351 | ␉value->string = NOT_AVAILABLE;␊ |
352 | ␉return true;␊ |
353 | }␊ |
354 | ␊ |
355 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
356 | {␊ |
357 | ␉static int idx = -1;␊ |
358 | ␉int␉map;␊ |
359 | ␊ |
360 | ␉idx++;␊ |
361 | ␉if (idx < MAX_RAM_SLOTS)␊ |
362 | ␉{␊ |
363 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
364 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
365 | ␉␉{␊ |
366 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
367 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
368 | ␉␉␉return true;␊ |
369 | ␉␉}␊ |
370 | ␉}␊ |
371 | ␊ |
372 | ␉if (!bootInfo->memDetect)␊ |
373 | ␉{␊ |
374 | ␉␉return false;␊ |
375 | ␉}␊ |
376 | ␉value->string = NOT_AVAILABLE;␊ |
377 | ␉return true;␊ |
378 | }␊ |
379 | ␊ |
380 | ␊ |
381 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
382 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
383 | static const char * const SMTAG = "_SM_";␊ |
384 | static const char* const DMITAG = "_DMI_";␊ |
385 | ␊ |
386 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
387 | {␊ |
388 | ␉SMBEntryPoint␉*smbios;␊ |
389 | ␉/* ␊ |
390 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
391 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
392 | ␉ */␊ |
393 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
394 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
395 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
396 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
397 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
398 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
399 | ␉ {␊ |
400 | ␉␉␉return smbios;␊ |
401 | ␉ }␊ |
402 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
403 | ␉}␊ |
404 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
405 | ␉pause();␊ |
406 | ␉return NULL;␊ |
407 | }␊ |
408 | ␊ |
409 | |