1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
34 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
36 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
37 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
38 | ␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊ |
39 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
40 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULX:␊ |
41 | ␊ |
42 | ␉␉␉␉␉␉value->word = 0;␊ |
43 | ␉␉␉␉␉␉break;␊ |
44 | ␉␉␉␉␉default:␊ |
45 | ␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
46 | ␉␉␉␉}␊ |
47 | ␉␉␉}␊ |
48 | ␉␉␉␉break;␊ |
49 | ␊ |
50 | ␉␉␉default:␊ |
51 | ␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
52 | ␉␉}␊ |
53 | ␉}␊ |
54 | ␉else␊ |
55 | ␉{␊ |
56 | ␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
57 | ␉}␊ |
58 | ␊ |
59 | ␉return true;␊ |
60 | }␊ |
61 | ␊ |
62 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
63 | {␊ |
64 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
65 | ␉return true;␊ |
66 | }␊ |
67 | ␊ |
68 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
69 | {␊ |
70 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
71 | ␉{␉␉␊ |
72 | ␉␉switch (Platform.CPU.Family) ␊ |
73 | ␉␉{␊ |
74 | ␉␉␉case 0x06:␊ |
75 | ␉␉␉{␊ |
76 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
77 | ␉␉␉␉{␊ |
78 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
79 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
80 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
81 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
82 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
83 | ␉␉␉␉␉␉return false;␊ |
84 | ␊ |
85 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
86 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
87 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
88 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
89 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
90 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
91 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
92 | ␉␉␉␉␉{␊ |
93 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
94 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
95 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
96 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
97 | ␉␉␉␉␉␉int i;␊ |
98 | ␉␉␉␉␉␉␊ |
99 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
100 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
101 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
102 | ␉␉␉␉␉␉{␊ |
103 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
104 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
105 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
106 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
107 | ␉␉␉␉␉␉␉␊ |
108 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
109 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
110 | ␉␉␉␉␉␉}␊ |
111 | ␊ |
112 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
113 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
114 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
115 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
116 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
117 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
118 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
119 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
120 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
121 | ␉␉␉␉␉␉return true;␊ |
122 | ␉␉␉␉␉}␊ |
123 | ␉␉␉␉}␊ |
124 | ␉␉␉}␊ |
125 | ␉␉}␊ |
126 | ␉}␊ |
127 | ␉return false;␊ |
128 | }␊ |
129 | ␊ |
130 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
131 | {␊ |
132 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
133 | ␉{␊ |
134 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
135 | ␉}␊ |
136 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
137 | ␉{␊ |
138 | ␉␉return 0x0201;␉// Core Solo␊ |
139 | ␉};␊ |
140 | ␉␊ |
141 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
142 | }␊ |
143 | ␊ |
144 | bool getSMBOemProcessorType(returnType *value)␊ |
145 | {␊ |
146 | ␉static bool done = false;␉␉␊ |
147 | ␊ |
148 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
149 | ␊ |
150 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
151 | ␉{␊ |
152 | ␉␉if (!done)␊ |
153 | ␉␉{␊ |
154 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
155 | ␉␉␉done = true;␊ |
156 | ␉␉}␊ |
157 | ␊ |
158 | ␉␉switch (Platform.CPU.Family) ␊ |
159 | ␉␉{␊ |
160 | ␉␉␉case 0x06:␊ |
161 | ␉␉␉{␊ |
162 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
163 | ␉␉␉␉{␊ |
164 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊ |
165 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
166 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
167 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
168 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
169 | ␉␉␉␉␉␉return true;␊ |
170 | ␊ |
171 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
172 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
173 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
174 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
175 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
176 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊ |
177 | ␉␉␉␉␉␉else␊ |
178 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
179 | ␉␉␉␉␉␉return true;␊ |
180 | ␊ |
181 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
182 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
183 | ␉␉␉␉␉␉␉value->word = 0x0501;// Xeon␊ |
184 | ␉␉␉␉␉␉else␊ |
185 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
186 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
187 | ␉␉␉␉␉␉␉else␊ |
188 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
189 | ␉␉␉␉␉␉return true;␊ |
190 | ␊ |
191 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
192 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
193 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
194 | ␉␉␉␉␉␉else␊ |
195 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
196 | ␉␉␉␉␉␉return true;␊ |
197 | ␊ |
198 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
199 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
200 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
201 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
202 | ␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊ |
203 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
204 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULX:␊ |
205 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
206 | ␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊ |
207 | ␉␉␉␉␉␉else␊ |
208 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
209 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉// Core i5␊ |
210 | ␉␉␉␉␉␉␉else␊ |
211 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
212 | ␉␉␉␉␉␉return true;␊ |
213 | ␉␉␉␉}␊ |
214 | ␉␉␉}␊ |
215 | ␉␉}␊ |
216 | ␉}␊ |
217 | ␉␊ |
218 | ␉return false;␊ |
219 | }␊ |
220 | ␊ |
221 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
222 | {␊ |
223 | ␉static int idx = -1;␊ |
224 | ␉int␉map;␊ |
225 | ␊ |
226 | ␉idx++;␊ |
227 | ␉if (idx < MAX_RAM_SLOTS)␊ |
228 | ␉{␊ |
229 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
230 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
231 | ␉␉{␊ |
232 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
233 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
234 | ␉␉␉return true;␊ |
235 | ␉␉}␊ |
236 | ␉}␊ |
237 | ␉␊ |
238 | ␉return false;␊ |
239 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
240 | //␉return true;␊ |
241 | }␊ |
242 | ␊ |
243 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
244 | {␊ |
245 | ␉value->word = 0xFFFF;␊ |
246 | ␉return true;␊ |
247 | }␊ |
248 | ␊ |
249 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
250 | {␊ |
251 | ␉static int idx = -1;␊ |
252 | ␉int␉map;␊ |
253 | ␊ |
254 | ␉idx++;␊ |
255 | ␉if (idx < MAX_RAM_SLOTS)␊ |
256 | ␉{␊ |
257 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
258 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
259 | ␉␉{␊ |
260 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
261 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
262 | ␉␉␉return true;␊ |
263 | ␉␉}␊ |
264 | ␉}␊ |
265 | ␊ |
266 | ␉return false;␊ |
267 | //␉value->dword = 800;␊ |
268 | //␉return true;␊ |
269 | }␊ |
270 | ␊ |
271 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
272 | {␊ |
273 | ␉static int idx = -1;␊ |
274 | ␉int␉map;␊ |
275 | ␊ |
276 | ␉idx++;␊ |
277 | ␉if (idx < MAX_RAM_SLOTS)␊ |
278 | ␉{␊ |
279 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
280 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
281 | ␉␉{␊ |
282 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
283 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
284 | ␉␉␉return true;␊ |
285 | ␉␉}␊ |
286 | ␉}␊ |
287 | ␊ |
288 | ␉if (!bootInfo->memDetect)␊ |
289 | ␉{␊ |
290 | ␉␉return false;␊ |
291 | ␉}␊ |
292 | ␉value->string = NOT_AVAILABLE;␊ |
293 | ␉return true;␊ |
294 | }␊ |
295 | ␉␊ |
296 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
297 | {␊ |
298 | ␉static int idx = -1;␊ |
299 | ␉int␉map;␊ |
300 | ␊ |
301 | ␉idx++;␊ |
302 | ␊ |
303 | DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
304 | ␊ |
305 | ␉if (idx < MAX_RAM_SLOTS)␊ |
306 | ␉{␊ |
307 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
308 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
309 | ␉␉{␊ |
310 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
311 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
312 | ␉␉␉return true;␊ |
313 | ␉␉}␊ |
314 | ␉}␊ |
315 | ␊ |
316 | ␉if (!bootInfo->memDetect)␊ |
317 | ␉{␊ |
318 | ␉␉return false;␊ |
319 | ␉}␊ |
320 | ␉value->string = NOT_AVAILABLE;␊ |
321 | ␉return true;␊ |
322 | }␊ |
323 | ␊ |
324 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
325 | {␊ |
326 | ␉static int idx = -1;␊ |
327 | ␉int␉map;␊ |
328 | ␊ |
329 | ␉idx++;␊ |
330 | ␉if (idx < MAX_RAM_SLOTS)␊ |
331 | ␉{␊ |
332 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
333 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
334 | ␉␉{␊ |
335 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
336 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
337 | ␉␉␉return true;␊ |
338 | ␉␉}␊ |
339 | ␉}␊ |
340 | ␊ |
341 | ␉if (!bootInfo->memDetect)␊ |
342 | ␉{␊ |
343 | ␉␉return false;␊ |
344 | ␉}␊ |
345 | ␉value->string = NOT_AVAILABLE;␊ |
346 | ␉return true;␊ |
347 | }␊ |
348 | ␊ |
349 | ␊ |
350 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
351 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
352 | static const char * const SMTAG = "_SM_";␊ |
353 | static const char* const DMITAG = "_DMI_";␊ |
354 | ␊ |
355 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
356 | {␊ |
357 | ␉SMBEntryPoint␉*smbios;␊ |
358 | ␉/* ␊ |
359 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
360 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
361 | ␉ */␊ |
362 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
363 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
364 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
365 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
366 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
367 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
368 | ␉ {␊ |
369 | ␉␉␉return smbios;␊ |
370 | ␉ }␊ |
371 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
372 | ␉}␊ |
373 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
374 | ␉pause();␊ |
375 | ␉return NULL;␊ |
376 | }␊ |
377 | ␊ |
378 | |