1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PCI_H␊ |
8 | #define __LIBSAIO_PCI_H␊ |
9 | ␊ |
10 | /*␊ |
11 | * 31 24 16 15 11 10 8␊ |
12 | * +---------------------------------------------------------------+␊ |
13 | * |1| 0 | BUS | DEV |FUNC | 0 |␊ |
14 | * +---------------------------------------------------------------+␊ |
15 | */␊ |
16 | ␊ |
17 | typedef struct {␊ |
18 | ␉uint32_t␉␉:2;␊ |
19 | ␉uint32_t␉reg␉:6;␊ |
20 | ␉uint32_t␉func␉:3;␊ |
21 | ␉uint32_t␉dev␉:5;␊ |
22 | ␉uint32_t␉bus␉:8;␊ |
23 | ␉uint32_t␉␉:7;␊ |
24 | ␉uint32_t␉eb␉:1;␊ |
25 | } pci_addr_t;␊ |
26 | ␊ |
27 | typedef union {␊ |
28 | ␉pci_addr_t␉bits;␊ |
29 | ␉uint32_t␉addr;␊ |
30 | } pci_dev_t;␊ |
31 | ␊ |
32 | typedef struct pci_dt_t {␊ |
33 | ␉uint8_t* regs;␊ |
34 | ␉pci_dev_t␉dev;␊ |
35 | ␊ |
36 | ␉uint16_t␉devfn; /* encoded device & function index */␊ |
37 | ␉uint16_t␉vendor_id; /* Specifies a vendor ID. The PCI bus configuration code obtains this␊ |
38 | vendor ID from the vendor ID device register. */␊ |
39 | ␉uint16_t␉device_id; /* Specifies a device ID that identifies the specific device. The PCI␊ |
40 | bus configuration code obtains this device ID from the device ID␊ |
41 | device register. */␊ |
42 | ␊ |
43 | ␉union {␊ |
44 | ␉␉struct {␊ |
45 | ␉␉␉uint16_t␉vendor_id; /* Specifies a subsystem vendor ID. */␊ |
46 | ␉␉␉uint16_t␉device_id; /* Specifies a subsystem device ID that identifies the specific device. */␊ |
47 | ␉␉} subsys;␊ |
48 | ␉␉uint32_t␉subsys_id;␊ |
49 | ␉}subsys_id;␊ |
50 | ␊ |
51 | ␉uint8_t progif; /* A read-only register that specifies a register-level programming interface the device has, if it has any at all. */␊ |
52 | ␊ |
53 | ␉uint8_t revision_id; /* PCI revision ID. Specifies a revision identifier for a particular device. Where valid IDs are allocated by the vendor. */␊ |
54 | ␊ |
55 | ␉uint16_t␉class_id; /* Specifies a class code. This member is a data structure that stores information related to the device's class code device register. */␊ |
56 | ␊ |
57 | ␉//uint16_t subclass_id; /* A read-only register that specifies the specific function the device performs. */␊ |
58 | ␊ |
59 | ␉struct pci_dt_t␉␉␉*parent;␊ |
60 | ␉struct pci_dt_t␉␉␉*children;␊ |
61 | ␉struct pci_dt_t␉␉␉*next;␊ |
62 | } pci_dt_t; // Info␊ |
63 | ␊ |
64 | // http://h30097.www3.hp.com/docs/dev_doc/DOCUMENTATION/HTML/DDK_R2/DOCS/HTML/MAN/MAN9/0192___S.HTM␊ |
65 | ␊ |
66 | /* Have pci_addr in the same format as the values written to 0xcf8␊ |
67 | * so register accesses can be made easy. */␊ |
68 | #define PCIADDR(bus, dev, func) ((1 << 31) | (bus << 16) | (dev << 11) | (func << 8))␊ |
69 | //#define MK_CONFIG_ADDR(BUS, DEV, FUNC, REG) (unsigned long)(((BUS) << 16) | ((DEV) << 11) | ((FUNC) << 8) | ((REG) & 0xfc) | (0x80000000))␊ |
70 | #define PCI_ADDR_REG␉␉0xcf8␊ |
71 | #define PCI_DATA_REG␉␉0xcfc␊ |
72 | ␊ |
73 | extern pci_dt_t␉␉*root_pci_dev;␊ |
74 | extern uint8_t␉␉pci_config_read8(uint32_t, uint8_t);␊ |
75 | extern uint16_t␉␉pci_config_read16(uint32_t, uint8_t);␊ |
76 | extern uint32_t␉␉pci_config_read32(uint32_t, uint8_t);␊ |
77 | extern void␉␉pci_config_write8(uint32_t, uint8_t, uint8_t);␊ |
78 | extern void␉␉pci_config_write16(uint32_t, uint8_t, uint16_t);␊ |
79 | extern void␉␉pci_config_write32(uint32_t, uint8_t, uint32_t);␊ |
80 | extern char␉␉*get_pci_dev_path(pci_dt_t *);␊ |
81 | extern void␉␉build_pci_dt(void);␊ |
82 | extern void␉␉dump_pci_dt(pci_dt_t *);␊ |
83 | ␊ |
84 | //-----------------------------------------------------------------------------␊ |
85 | // added by iNDi␊ |
86 | ␊ |
87 | /* Option ROM PCI Data Structure */␊ |
88 | typedef struct {␊ |
89 | ␉uint32_t␉␉signature;␉␉// ati - 0x52494350, nvidia - 0x50434952, 'PCIR'␊ |
90 | ␉uint16_t␉␉vendor_id;␊ |
91 | ␉uint16_t␉␉device_id;␊ |
92 | ␉uint16_t␉␉vital_product_data_offset;␊ |
93 | ␉uint16_t␉␉structure_length;␊ |
94 | ␉uint8_t␉␉␉structure_revision;␊ |
95 | ␉uint8_t␉␉␉class_code[3];␊ |
96 | ␉uint16_t␉␉image_length; //same as rom_size for NVidia and ATI, 0x80 for Intel␊ |
97 | ␉uint16_t␉␉image_revision;␊ |
98 | ␉uint8_t␉␉␉code_type;␊ |
99 | ␉uint8_t␉␉␉indicator;␊ |
100 | ␉uint16_t␉␉reserved;␊ |
101 | } option_rom_pci_header_t;␊ |
102 | ␊ |
103 | ␊ |
104 | typedef struct {␊ |
105 | ␉uint32_t␉␉signature;␉␉// 0x24506E50 '$PnP'␊ |
106 | ␉uint8_t␉␉␉revision;␉␉//␉1␊ |
107 | ␉uint8_t␉␉␉length;␊ |
108 | ␉uint16_t␉␉offset;␊ |
109 | ␉uint8_t␉␉␉checksum;␊ |
110 | ␉uint32_t␉␉identifier;␊ |
111 | ␉uint16_t␉␉manufacturer;␊ |
112 | ␉uint16_t␉␉product;␊ |
113 | ␉uint8_t␉␉␉class[3];␊ |
114 | ␉uint8_t␉␉␉indicators;␊ |
115 | ␉uint16_t␉␉boot_vector;␊ |
116 | ␉uint16_t␉␉disconnect_vector;␊ |
117 | ␉uint16_t␉␉bootstrap_vector;␊ |
118 | ␉uint16_t␉␉reserved;␊ |
119 | ␉uint16_t␉␉resource_vector;␊ |
120 | } option_rom_pnp_header_t;␊ |
121 | ␊ |
122 | /* Option ROM header */␊ |
123 | typedef struct {␊ |
124 | ␉uint16_t␉signature; // 0xAA55␊ |
125 | ␉uint8_t␉␉rom_size; //in 512 bytes blocks␊ |
126 | ␉uint8_t␉␉jump; //0xE9 for ATI and Intel, 0xEB for NVidia␊ |
127 | ␉uint8_t␉␉entry_point[4]; //offset to␊ |
128 | ␉uint8_t␉␉reserved[16];␊ |
129 | ␉uint16_t␉pci_header_offset; //@0x18␊ |
130 | ␉uint16_t␉expansion_header_offset;␊ |
131 | } option_rom_header_t;␊ |
132 | ␊ |
133 | ␊ |
134 | /*␊ |
135 | * Under PCI, each device has 256 bytes of configuration address space,␊ |
136 | * of which the first 64 bytes are standardized as follows:␊ |
137 | *␊ |
138 | * register name offset␊ |
139 | *******************************************************/␊ |
140 | #define PCI_VENDOR_ID␉␉␉␉␉␉0x00␉␉␉/* 16 bits */␊ |
141 | #define PCI_DEVICE_ID␉␉␉␉␉␉0x02␉␉␉/* 16 bits */␊ |
142 | #define PCI_COMMAND 0x04␉␉␉/* 16 bits */␊ |
143 | #define PCI_COMMAND_IO␉␉␉␉␉␉0x0001␉␉␉/* Enable response in I/O space */␊ |
144 | #define PCI_COMMAND_MEMORY␉␉␉␉␉0x0002␉␉␉/* Enable response in Memory space */␊ |
145 | #define PCI_COMMAND_MASTER␉␉␉␉␉0x0004␉␉␉/* Enable bus mastering */␊ |
146 | #define PCI_COMMAND_SPECIAL␉␉␉␉␉0x0008␉␉␉/* Enable response to special cycles (1 byte) */␊ |
147 | #define PCI_COMMAND_INVALIDATE␉␉␉␉0x0010␉␉␉/* Use memory write and invalidate */␊ |
148 | #define PCI_COMMAND_VGA_PALETTE␉␉␉␉0x0020␉␉␉/* Enable palette snooping */␊ |
149 | #define PCI_COMMAND_PARITY␉␉␉␉␉0x0040␉␉␉/* Enable parity checking */␊ |
150 | #define PCI_COMMAND_WAIT␉␉␉␉␉0x0080␉␉␉/* Enable address/data stepping */␊ |
151 | #define PCI_COMMAND_SERR␉␉␉␉␉0x0100␉␉␉/* Enable SERR */␊ |
152 | #define PCI_COMMAND_FAST_BACK␉␉␉␉0x0200␉␉␉/* Enable back-to-back writes */␊ |
153 | #define PCI_COMMAND_DISABLE_INTx␉␉␉0x0400␉␉␉/* PCIE: Disable INTx interrupts */␊ |
154 | ␊ |
155 | #define PCI_STATUS 0x06␉␉␉/* 16 bits */␊ |
156 | #define PCI_STATUS_INTx␉␉␉␉␉␉0x0008␉␉␉/* PCIE: INTx interrupt pending */␊ |
157 | #define PCI_STATUS_CAP_LIST␉␉␉␉␉0x0010␉␉␉/* Support Capability List */␊ |
158 | #define PCI_STATUS_66MHZ␉␉␉␉␉0x0020␉␉␉/* Support 66 Mhz PCI 2.1 bus */␊ |
159 | #define PCI_STATUS_UDF␉␉␉␉␉␉0x0040␉␉␉/* Support User Definable Features [obsolete] */␊ |
160 | #define PCI_STATUS_FAST_BACK␉␉␉␉0x0080␉␉␉/* Accept fast-back to back */␊ |
161 | #define PCI_STATUS_PARITY␉␉␉␉␉0x0100␉␉␉/* Detected parity error */␊ |
162 | #define PCI_STATUS_DEVSEL_FAST␉␉␉␉0x0000␊ |
163 | #define PCI_STATUS_DEVSEL_MEDIUM␉␉␉0x0200␊ |
164 | #define PCI_STATUS_DEVSEL_SLOW␉␉␉␉0x0400␊ |
165 | #define PCI_STATUS_DEVSEL_MASK␉␉␉␉0x0600␉␉␉/* DEVSEL timing */␊ |
166 | #define PCI_STATUS_SIG_TARGET_ABORT␉␉␉0x0800␉␉␉/* Set on target abort */␊ |
167 | #define PCI_STATUS_REC_TARGET_ABORT␉␉␉0x1000␉␉␉/* Master ack of " */␊ |
168 | #define PCI_STATUS_REC_MASTER_ABORT␉␉␉0x2000␉␉␉/* Set on master abort */␊ |
169 | #define PCI_STATUS_SIG_SYSTEM_ERROR␉␉␉0x4000␉␉␉/* Set when we drive SERR */␊ |
170 | #define PCI_STATUS_DETECTED_PARITY␉␉␉0x8000␉␉␉/* Set on parity error */␊ |
171 | ␊ |
172 | #define PCI_CLASS_REVISION␉␉␉␉␉0x08␉␉␉/* High 24 bits are class, low 8 revision */␊ |
173 | #define PCI_CLASS_PROG␉␉␉␉␉␉0x09␉␉␉/* Reg. Level Programming Interface know also as PCI_PROG_IF */␊ |
174 | #define PCI_CLASS_DEVICE␉␉␉␉␉0x0a␉␉␉/* Device subclass */␊ |
175 | //#define PCI_SUBCLASS_DEVICE␉␉␉␉0x0b␉␉␉/* Device class */␊ |
176 | ␊ |
177 | #define PCI_CACHE_LINE_SIZE␉␉␉␉␉0x0c␉␉␉/* 8 bits */␊ |
178 | #define PCI_LATENCY_TIMER␉␉␉␉␉0x0d␉␉␉/* 8 bits */␊ |
179 | #define PCI_HEADER_TYPE␉␉␉␉␉␉0x0e␉␉␉/* 8 bits */␊ |
180 | #define PCI_HEADER_TYPE_NORMAL␉␉␉␉0x00␊ |
181 | #define PCI_HEADER_TYPE_BRIDGE␉␉␉␉0x01␊ |
182 | #define PCI_HEADER_TYPE_CARDBUS␉␉␉␉0x02␊ |
183 | ␊ |
184 | #define PCI_BIST 0x0f␉␉␉/* 8 bits */␊ |
185 | #define PCI_BIST_CODE_MASK␉␉␉␉␉0x0f␉␉␉/* Return result */␊ |
186 | #define PCI_BIST_START␉␉␉␉␉␉0x40␉␉␉/* 1 to start BIST, 2 secs or less */␊ |
187 | #define PCI_BIST_CAPABLE␉␉␉␉␉0x80␉␉␉/* 1 if BIST capable */␊ |
188 | ␊ |
189 | /*␊ |
190 | * Base addresses specify locations in memory or I/O space.␊ |
191 | * Decoded size can be determined by writing a value of␊ |
192 | * 0xffffffff to the register, and reading it back. Only␊ |
193 | * 1 bits are decoded.␊ |
194 | */␊ |
195 | #define PCI_BASE_ADDRESS_0␉␉␉␉␉0x10␉␉␉/* 32 bits */␊ |
196 | #define PCI_BASE_ADDRESS_1␉␉␉␉␉0x14␉␉␉/* 32 bits [htype 0,1 only] */␊ |
197 | #define PCI_BASE_ADDRESS_2␉␉␉␉␉0x18␉␉␉/* 32 bits [htype 0 only] */␊ |
198 | #define PCI_BASE_ADDRESS_3␉␉␉␉␉0x1c␉␉␉/* 32 bits */␊ |
199 | #define PCI_BASE_ADDRESS_4␉␉␉␉␉0x20␉␉␉/* 32 bits */␊ |
200 | #define PCI_BASE_ADDRESS_5␉␉␉␉␉0x24␉␉␉/* 32 bits */␊ |
201 | #define PCI_BASE_ADDRESS_SPACE␉␉␉␉0x01␉␉␉/* 0 = memory, 1 = I/O */␊ |
202 | #define PCI_BASE_ADDRESS_SPACE_IO␉␉␉0x01␊ |
203 | #define PCI_BASE_ADDRESS_SPACE_MEMORY␉␉0x00␊ |
204 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK␉␉0x06␊ |
205 | #define PCI_BASE_ADDRESS_MEM_TYPE_32␉␉0x00␉␉␉/* 32 bit address */␊ |
206 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M␉␉0x02␉␉␉/* Below 1M [obsolete] */␊ |
207 | #define PCI_BASE_ADDRESS_MEM_TYPE_64␉␉0x04␉␉␉/* 64 bit address */␊ |
208 | #define PCI_BASE_ADDRESS_MEM_PREFETCH␉␉0x08␉␉␉/* prefetchable? */␊ |
209 | #define PCI_BASE_ADDRESS_MEM_MASK␉␉␉(~(pciaddr_t)0x0f)␊ |
210 | #define PCI_BASE_ADDRESS_IO_MASK␉␉␉(~(pciaddr_t)0x03)␊ |
211 | /* bit 1 is reserved if address_space = 1 */␊ |
212 | ␊ |
213 | /* Header type 0 (normal devices) */␊ |
214 | #define PCI_CARDBUS_CIS␉␉␉␉␉␉0x28␊ |
215 | #define PCI_SUBSYSTEM_VENDOR_ID␉␉␉␉0x2c␊ |
216 | #define PCI_SUBSYSTEM_ID␉␉␉␉␉0x2e␊ |
217 | #define PCI_ROM_ADDRESS␉␉␉␉␉␉0x30␉␉␉/* Bits 31..11 are address, 10..1 reserved */␊ |
218 | #define PCI_ROM_ADDRESS_ENABLE␉␉␉␉0x01␊ |
219 | #define PCI_ROM_ADDRESS_MASK␉␉␉␉(~(pciaddr_t)0x7ff)␊ |
220 | ␊ |
221 | #define PCI_CAPABILITY_LIST␉␉␉␉␉0x34␉␉␉/* Offset of first capability list entry */␊ |
222 | ␊ |
223 | /* 0x35-0x3b are reserved */␊ |
224 | #define PCI_INTERRUPT_LINE␉␉␉␉␉0x3c␉␉␉/* 8 bits */␊ |
225 | #define PCI_INTERRUPT_PIN␉␉␉␉␉0x3d␉␉␉/* 8 bits */␊ |
226 | #define PCI_MIN_GNT 0x3e␉␉␉/* 8 bits */␊ |
227 | #define PCI_MAX_LAT 0x3f␉␉␉/* 8 bits */␊ |
228 | ␊ |
229 | /* Header type 1 (PCI-to-PCI bridges) */␊ |
230 | #define PCI_PRIMARY_BUS␉␉␉␉␉␉0x18␉␉␉/* Primary bus number */␊ |
231 | #define PCI_SECONDARY_BUS␉␉␉␉␉0x19␉␉␉/* Secondary bus number */␊ |
232 | #define PCI_SUBORDINATE_BUS␉␉␉␉␉0x1a␉␉␉/* Highest bus number behind the bridge */␊ |
233 | #define PCI_SEC_LATENCY_TIMER␉␉␉␉0x1b␉␉␉/* Latency timer for secondary interface */␊ |
234 | #define PCI_IO_BASE 0x1c␉␉␉/* I/O range behind the bridge */␊ |
235 | #define PCI_IO_LIMIT␉␉␉␉␉␉0x1d␊ |
236 | #define PCI_IO_RANGE_TYPE_MASK␉␉␉␉0x0f␉␉␉/* I/O bridging type */␊ |
237 | #define PCI_IO_RANGE_TYPE_16␉␉␉␉0x00␊ |
238 | #define PCI_IO_RANGE_TYPE_32␉␉␉␉0x01␊ |
239 | #define PCI_IO_RANGE_MASK␉␉␉␉␉~0x0f␊ |
240 | #define PCI_SEC_STATUS␉␉␉␉␉␉0x1e␉␉␉/* Secondary status register */␊ |
241 | #define PCI_MEMORY_BASE␉␉␉␉␉␉0x20␉␉␉/* Memory range behind */␊ |
242 | #define PCI_MEMORY_LIMIT␉␉␉␉␉0x22␊ |
243 | #define PCI_MEMORY_RANGE_TYPE_MASK␉␉␉␉0x0f␊ |
244 | #define PCI_MEMORY_RANGE_MASK␉␉␉␉␉~0x0f␊ |
245 | #define PCI_PREF_MEMORY_BASE␉␉␉␉␉0x24␉␉␉/* Prefetchable memory range behind */␊ |
246 | #define PCI_PREF_MEMORY_LIMIT␉␉␉␉␉0x26␊ |
247 | #define PCI_PREF_RANGE_TYPE_MASK␉␉␉␉0x0f␊ |
248 | #define PCI_PREF_RANGE_TYPE_32␉␉␉␉␉0x00␊ |
249 | #define PCI_PREF_RANGE_TYPE_64␉␉␉␉␉0x01␊ |
250 | #define PCI_PREF_RANGE_MASK␉␉␉␉␉~0x0f␊ |
251 | #define PCI_PREF_BASE_UPPER32␉␉␉␉␉0x28␉␉␉/* Upper half of prefetchable memory range */␊ |
252 | #define PCI_PREF_LIMIT_UPPER32␉␉␉␉␉0x2c␊ |
253 | #define PCI_IO_BASE_UPPER16␉␉␉␉␉0x30␉␉␉/* Upper half of I/O addresses */␊ |
254 | #define PCI_IO_LIMIT_UPPER16␉␉␉␉␉0x32␊ |
255 | /* 0x34 same as for htype 0 */␊ |
256 | /* 0x35-0x3b is reserved */␊ |
257 | #define PCI_ROM_ADDRESS1␉␉␉␉␉0x38␉␉␉/* Same as PCI_ROM_ADDRESS, but for htype 1 */␊ |
258 | /* 0x3c-0x3d are same as for htype 0 */␊ |
259 | #define PCI_BRIDGE_CONTROL␉␉␉␉␉0x3e␊ |
260 | #define PCI_BRIDGE_CTL_PARITY␉␉␉␉␉0x01␉␉␉/* Enable parity detection on secondary interface */␊ |
261 | #define PCI_BRIDGE_CTL_SERR␉␉␉␉␉0x02␉␉␉/* The same for SERR forwarding */␊ |
262 | #define PCI_BRIDGE_CTL_NO_ISA␉␉␉␉␉0x04␉␉␉/* Disable bridging of ISA ports */␊ |
263 | #define PCI_BRIDGE_CTL_VGA␉␉␉␉␉0x08␉␉␉/* Forward VGA addresses */␊ |
264 | #define PCI_BRIDGE_CTL_MASTER_ABORT␉␉␉␉0x20␉␉␉/* Report master aborts */␊ |
265 | #define PCI_BRIDGE_CTL_BUS_RESET␉␉␉␉0x40␉␉␉/* Secondary bus reset */␊ |
266 | #define PCI_BRIDGE_CTL_FAST_BACK␉␉␉␉0x80␉␉␉/* Fast Back2Back enabled on secondary interface */␊ |
267 | #define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER␉␉␉0x100␉␉␉/* PCI-X? */␊ |
268 | #define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER␉␉␉0x200␉␉␉/* PCI-X? */␊ |
269 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS␉␉␉0x400␉␉␉/* PCI-X? */␊ |
270 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN␉␉␉0x800␉␉␉/* PCI-X? */␊ |
271 | ␊ |
272 | /* Header type 2 (CardBus bridges) */␊ |
273 | /* 0x14-0x15 reserved */␊ |
274 | #define PCI_CB_SEC_STATUS␉␉␉␉␉0x16␉␉␉/* Secondary status */␊ |
275 | #define PCI_CB_PRIMARY_BUS␉␉␉␉␉0x18␉␉␉/* PCI bus number */␊ |
276 | #define PCI_CB_CARD_BUS␉␉␉␉␉␉0x19␉␉␉/* CardBus bus number */␊ |
277 | #define PCI_CB_SUBORDINATE_BUS␉␉␉␉␉0x1a␉␉␉/* Subordinate bus number */␊ |
278 | #define PCI_CB_LATENCY_TIMER␉␉␉␉␉0x1b␉␉␉/* CardBus latency timer */␊ |
279 | #define PCI_CB_MEMORY_BASE_0␉␉␉␉␉0x1c␊ |
280 | #define PCI_CB_MEMORY_LIMIT_0␉␉␉␉␉0x20␊ |
281 | #define PCI_CB_MEMORY_BASE_1␉␉␉␉␉0x24␊ |
282 | #define PCI_CB_MEMORY_LIMIT_1␉␉␉␉␉0x28␊ |
283 | #define PCI_CB_IO_BASE_0␉␉␉␉␉0x2c␊ |
284 | #define PCI_CB_IO_BASE_0_HI␉␉␉␉␉0x2e␊ |
285 | #define PCI_CB_IO_LIMIT_0␉␉␉␉␉0x30␊ |
286 | #define PCI_CB_IO_LIMIT_0_HI␉␉␉␉␉0x32␊ |
287 | #define PCI_CB_IO_BASE_1␉␉␉␉␉0x34␊ |
288 | #define PCI_CB_IO_BASE_1_HI␉␉␉␉␉0x36␊ |
289 | #define PCI_CB_IO_LIMIT_1␉␉␉␉␉0x38␊ |
290 | #define PCI_CB_IO_LIMIT_1_HI␉␉␉␉␉0x3a␊ |
291 | #define␉PCI_CB_IO_RANGE_MASK␉␉␉␉␉~0x03␊ |
292 | /* 0x3c-0x3d are same as for htype 0 */␊ |
293 | #define PCI_CB_BRIDGE_CONTROL␉␉␉␉␉0x3e␊ |
294 | #define PCI_CB_BRIDGE_CTL_PARITY␉␉␉␉0x01␉␉␉/* Similar to standard bridge control register */␊ |
295 | #define PCI_CB_BRIDGE_CTL_SERR␉␉␉␉␉0x02␊ |
296 | #define PCI_CB_BRIDGE_CTL_ISA␉␉␉␉␉0x04␊ |
297 | #define PCI_CB_BRIDGE_CTL_VGA␉␉␉␉␉0x08␊ |
298 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT␉␉␉␉0x20␊ |
299 | #define PCI_CB_BRIDGE_CTL_CB_RESET␉␉␉␉0x40␉␉␉/* CardBus reset */␊ |
300 | #define PCI_CB_BRIDGE_CTL_16BIT_INT␉␉␉␉0x80␉␉␉/* Enable interrupt for 16-bit cards */␊ |
301 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0␉␉␉␉0x100␉␉␉/* Prefetch enable for both memory regions */␊ |
302 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1␉␉␉␉0x200␊ |
303 | #define PCI_CB_BRIDGE_CTL_POST_WRITES␉␉␉␉0x400␊ |
304 | #define PCI_CB_SUBSYSTEM_VENDOR_ID␉␉␉␉0x40␊ |
305 | #define PCI_CB_SUBSYSTEM_ID␉␉␉␉␉0x42␊ |
306 | #define PCI_CB_LEGACY_MODE_BASE␉␉␉␉␉0x44␉␉␉/* 16-bit PC Card legacy mode base address (ExCa) */␊ |
307 | /* 0x48-0x7f reserved */␊ |
308 | ␊ |
309 | /* Capability Identification Numbers list */␊ |
310 | #define PCI_CAP_LIST_ID␉␉␉␉␉␉0␉␉␉/* Capability ID */␊ |
311 | #define PCI_CAP_ID_PM␉␉␉␉␉␉0x01␉␉␉/* Power Management */␊ |
312 | #define PCI_CAP_ID_AGP␉␉␉␉␉␉0x02␉␉␉/* Accelerated Graphics Port */␊ |
313 | #define PCI_CAP_ID_VPD␉␉␉␉␉␉0x03␉␉␉/* Vital Product Data */␊ |
314 | #define PCI_CAP_ID_SLOTID␉␉␉␉␉0x04␉␉␉/* Slot Identification */␊ |
315 | #define PCI_CAP_ID_MSI␉␉␉␉␉␉0x05␉␉␉/* Message Signaled Interrupts */␊ |
316 | #define PCI_CAP_ID_CHSWP␉␉␉␉␉0x06␉␉␉/* CompactPCI HotSwap */␊ |
317 | #define PCI_CAP_ID_PCIX␉␉␉␉␉␉0x07␉␉␉/* PCI-X */␊ |
318 | #define PCI_CAP_ID_HT␉␉␉␉␉␉0x08␉␉␉/* HyperTransport */␊ |
319 | #define PCI_CAP_ID_VNDR␉␉␉␉␉␉0x09␉␉␉/* Vendor specific */␊ |
320 | #define PCI_CAP_ID_DBG␉␉␉␉␉␉0x0A␉␉␉/* Debug port */␊ |
321 | #define PCI_CAP_ID_CCRC␉␉␉␉␉␉0x0B␉␉␉/* CompactPCI Central Resource Control */␊ |
322 | #define PCI_CAP_ID_HOTPLUG␉␉␉␉␉0x0C␉␉␉/* PCI hot-plug */␊ |
323 | #define PCI_CAP_ID_SSVID␉␉␉␉␉0x0D␉␉␉/* Bridge subsystem vendor/device ID */␊ |
324 | #define PCI_CAP_ID_AGP3␉␉␉␉␉␉0x0E␉␉␉/* AGP 8x */␊ |
325 | #define PCI_CAP_ID_SECURE␉␉␉␉␉0x0F␉␉␉/* Secure device (?) */␊ |
326 | #define PCI_CAP_ID_EXP␉␉␉␉␉␉0x10␉␉␉/* PCI Express */␊ |
327 | #define PCI_CAP_ID_MSIX␉␉␉␉␉␉0x11␉␉␉/* MSI-X */␊ |
328 | #define PCI_CAP_ID_SATA␉␉␉␉␉␉0x12␉␉␉/* Serial-ATA HBA */␊ |
329 | #define PCI_CAP_ID_AF␉␉␉␉␉␉0x13␉␉␉/* Advanced features of PCI devices integrated in PCIe root cplx */␊ |
330 | #define PCI_CAP_LIST_NEXT␉␉␉␉␉1␉␉␉/* Next capability in the list */␊ |
331 | #define PCI_CAP_FLAGS␉␉␉␉␉␉2␉␉␉/* Capability defined flags (16 bits) */␊ |
332 | #define PCI_CAP_SIZEOF␉␉␉␉␉␉4␊ |
333 | ␊ |
334 | /* Capabilities residing in the PCI Express extended configuration space */␊ |
335 | #define PCI_EXT_CAP_ID_AER␉␉␉␉␉0x01␉␉␉/* Advanced Error Reporting */␊ |
336 | #define PCI_EXT_CAP_ID_VC␉␉␉␉␉0x02␉␉␉/* Virtual Channel */␊ |
337 | #define PCI_EXT_CAP_ID_DSN␉␉␉␉␉0x03␉␉␉/* Device Serial Number */␊ |
338 | #define PCI_EXT_CAP_ID_PB␉␉␉␉␉0x04␉␉␉/* Power Budgeting */␊ |
339 | #define PCI_EXT_CAP_ID_RCLINK␉␉␉␉␉0x05␉␉␉/* Root Complex Link Declaration */␊ |
340 | #define PCI_EXT_CAP_ID_RCILINK␉␉␉␉␉0x06␉␉␉/* Root Complex Internal Link Declaration */␊ |
341 | #define PCI_EXT_CAP_ID_RCECOLL␉␉␉␉␉0x07␉␉␉/* Root Complex Event Collector */␊ |
342 | #define PCI_EXT_CAP_ID_MFVC␉␉␉␉␉0x08␉␉␉/* Multi-Function Virtual Channel */␊ |
343 | #define PCI_EXT_CAP_ID_RBCB␉␉␉␉␉0x0a␉␉␉/* Root Bridge Control Block */␊ |
344 | #define PCI_EXT_CAP_ID_VNDR␉␉␉␉␉0x0b␉␉␉/* Vendor specific */␊ |
345 | #define PCI_EXT_CAP_ID_ACS␉␉␉␉␉0x0d␉␉␉/* Access Controls */␊ |
346 | #define PCI_EXT_CAP_ID_ARI␉␉␉␉␉0x0e␉␉␉/* Alternative Routing-ID Interpretation */␊ |
347 | #define PCI_EXT_CAP_ID_ATS␉␉␉␉␉0x0f␉␉␉/* Address Translation Service */␊ |
348 | #define PCI_EXT_CAP_ID_SRIOV␉␉␉␉␉0x10␉␉␉/* Single Root I/O Virtualization */␊ |
349 | ␊ |
350 | /* Power Management Registers */␊ |
351 | #define PCI_PM_CAP_VER_MASK␉␉␉␉␉0x0007␉␉␉/* Version (2=PM1.1) */␊ |
352 | #define PCI_PM_CAP_PME_CLOCK␉␉␉␉␉0x0008␉␉␉/* Clock required for PME generation */␊ |
353 | #define PCI_PM_CAP_DSI␉␉␉␉␉␉0x0020␉␉␉/* Device specific initialization required */␊ |
354 | #define PCI_PM_CAP_AUX_C_MASK␉␉␉␉␉0x01c0␉␉␉/* Maximum aux current required in D3cold */␊ |
355 | #define PCI_PM_CAP_D1␉␉␉␉␉␉0x0200␉␉␉/* D1 power state support */␊ |
356 | #define PCI_PM_CAP_D2␉␉␉␉␉␉0x0400␉␉␉/* D2 power state support */␊ |
357 | #define PCI_PM_CAP_PME_D0␉␉␉␉␉0x0800␉␉␉/* PME can be asserted from D0 */␊ |
358 | #define PCI_PM_CAP_PME_D1␉␉␉␉␉0x1000␉␉␉/* PME can be asserted from D1 */␊ |
359 | #define PCI_PM_CAP_PME_D2␉␉␉␉␉0x2000␉␉␉/* PME can be asserted from D2 */␊ |
360 | #define PCI_PM_CAP_PME_D3_HOT␉␉␉␉␉0x4000␉␉␉/* PME can be asserted from D3hot */␊ |
361 | #define PCI_PM_CAP_PME_D3_COLD␉␉␉␉␉0x8000␉␉␉/* PME can be asserted from D3cold */␊ |
362 | #define PCI_PM_CTRL␉␉␉␉␉␉4␉␉␉/* PM control and status register */␊ |
363 | #define PCI_PM_CTRL_STATE_MASK␉␉␉␉␉0x0003␉␉␉/* Current power state (D0 to D3) */␊ |
364 | #define PCI_PM_CTRL_PME_ENABLE␉␉␉␉␉0x0100␉␉␉/* PME pin enable */␊ |
365 | #define PCI_PM_CTRL_DATA_SEL_MASK␉␉␉␉0x1e00␉␉␉/* PM table data index */␊ |
366 | #define PCI_PM_CTRL_DATA_SCALE_MASK␉␉␉␉0x6000␉␉␉/* PM table data scaling factor */␊ |
367 | #define PCI_PM_CTRL_PME_STATUS␉␉␉␉␉0x8000␉␉␉/* PME pin status */␊ |
368 | #define PCI_PM_PPB_EXTENSIONS␉␉␉␉␉6␉␉␉/* PPB support extensions */␊ |
369 | #define PCI_PM_PPB_B2_B3␉␉␉␉␉0x40␉␉␉/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */␊ |
370 | #define PCI_PM_BPCC_ENABLE␉␉␉␉␉0x80␉␉␉/* Secondary bus is power managed */␊ |
371 | #define PCI_PM_DATA_REGISTER␉␉␉␉␉7␉␉␉/* PM table contents read here */␊ |
372 | #define PCI_PM_SIZEOF␉␉␉␉␉␉8␊ |
373 | ␊ |
374 | /* AGP registers */␊ |
375 | #define PCI_AGP_VERSION␉␉␉␉␉␉2␉␉␉/* BCD version number */␊ |
376 | #define PCI_AGP_RFU␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
377 | #define PCI_AGP_STATUS␉␉␉␉␉␉4␉␉␉/* Status register */␊ |
378 | #define PCI_AGP_STATUS_RQ_MASK␉␉␉␉␉0xff000000␉␉/* Maximum number of requests - 1 */␊ |
379 | #define PCI_AGP_STATUS_ISOCH␉␉␉␉␉0x10000␉␉␉/* Isochronous transactions supported */␊ |
380 | #define PCI_AGP_STATUS_ARQSZ_MASK␉␉␉␉0xe000␉␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
381 | #define PCI_AGP_STATUS_CAL_MASK␉␉␉␉␉0x1c00␉␉␉/* Calibration cycle timing */␊ |
382 | #define PCI_AGP_STATUS_SBA␉␉␉␉␉0x0200␉␉␉/* Sideband addressing supported */␊ |
383 | #define PCI_AGP_STATUS_ITA_COH␉␉␉␉␉0x0100␉␉␉/* In-aperture accesses always coherent */␊ |
384 | #define PCI_AGP_STATUS_GART64␉␉␉␉␉0x0080␉␉␉/* 64-bit GART entries supported */␊ |
385 | #define PCI_AGP_STATUS_HTRANS␉␉␉␉␉0x0040␉␉␉/* If 0, core logic can xlate host CPU accesses thru aperture */␊ |
386 | #define PCI_AGP_STATUS_64BIT␉␉␉␉␉0x0020␉␉␉/* 64-bit addressing cycles supported */␊ |
387 | #define PCI_AGP_STATUS_FW␉␉␉␉␉0x0010␉␉␉/* Fast write transfers supported */␊ |
388 | #define PCI_AGP_STATUS_AGP3␉␉␉␉␉0x0008␉␉␉/* AGP3 mode supported */␊ |
389 | #define PCI_AGP_STATUS_RATE4␉␉␉␉␉0x0004␉␉␉/* 4x transfer rate supported (RFU in AGP3 mode) */␊ |
390 | #define PCI_AGP_STATUS_RATE2␉␉␉␉␉0x0002␉␉␉/* 2x transfer rate supported (8x in AGP3 mode) */␊ |
391 | #define PCI_AGP_STATUS_RATE1␉␉␉␉␉0x0001␉␉␉/* 1x transfer rate supported (4x in AGP3 mode) */␊ |
392 | #define PCI_AGP_COMMAND␉␉␉␉␉␉8␉␉␉/* Control register */␊ |
393 | #define PCI_AGP_COMMAND_RQ_MASK␉␉␉␉␉0xff000000␉␉/* Master: Maximum number of requests */␊ |
394 | #define PCI_AGP_COMMAND_ARQSZ_MASK␉␉␉␉0xe000␉␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
395 | #define PCI_AGP_COMMAND_CAL_MASK␉␉␉␉0x1c00␉␉␉/* Calibration cycle timing */␊ |
396 | #define PCI_AGP_COMMAND_SBA␉␉␉␉␉0x0200␉␉␉/* Sideband addressing enabled */␊ |
397 | #define PCI_AGP_COMMAND_AGP␉␉␉␉␉0x0100␉␉␉/* Allow processing of AGP transactions */␊ |
398 | #define PCI_AGP_COMMAND_GART64␉␉␉␉␉0x0080␉␉␉/* 64-bit GART entries enabled */␊ |
399 | #define PCI_AGP_COMMAND_64BIT␉␉␉␉␉0x0020␉␉␉/* Allow generation of 64-bit addr cycles */␊ |
400 | #define PCI_AGP_COMMAND_FW␉␉␉␉␉0x0010␉␉␉/* Enable FW transfers */␊ |
401 | #define PCI_AGP_COMMAND_RATE4␉␉␉␉␉0x0004␉␉␉/* Use 4x rate (RFU in AGP3 mode) */␊ |
402 | #define PCI_AGP_COMMAND_RATE2␉␉␉␉␉0x0002␉␉␉/* Use 2x rate (8x in AGP3 mode) */␊ |
403 | #define PCI_AGP_COMMAND_RATE1␉␉␉␉␉0x0001␉␉␉/* Use 1x rate (4x in AGP3 mode) */␊ |
404 | #define PCI_AGP_SIZEOF␉␉␉␉␉␉12␊ |
405 | ␊ |
406 | /* Vital Product Data */␊ |
407 | #define PCI_VPD_ADDR␉␉␉␉␉␉2␉␉␉/* Address to access (15 bits!) */␊ |
408 | #define PCI_VPD_ADDR_MASK␉␉␉␉␉0x7fff␉␉␉/* Address mask */␊ |
409 | #define PCI_VPD_ADDR_F␉␉␉␉␉␉0x8000␉␉␉/* Write 0, 1 indicates completion */␊ |
410 | #define PCI_VPD_DATA␉␉␉␉␉␉4␉␉␉/* 32-bits of data returned here */␊ |
411 | ␊ |
412 | /* Slot Identification */␊ |
413 | #define PCI_SID_ESR␉␉␉␉␉␉2␉␉␉/* Expansion Slot Register */␊ |
414 | #define PCI_SID_ESR_NSLOTS␉␉␉␉␉0x1f␉␉␉/* Number of expansion slots available */␊ |
415 | #define PCI_SID_ESR_FIC␉␉␉␉␉␉0x20␉␉␉/* First In Chassis Flag */␊ |
416 | #define PCI_SID_CHASSIS_NR␉␉␉␉␉3␉␉␉/* Chassis Number */␊ |
417 | ␊ |
418 | /* Message Signaled Interrupts registers */␊ |
419 | #define PCI_MSI_FLAGS␉␉␉␉␉␉2␉␉␉/* Various flags */␊ |
420 | #define PCI_MSI_FLAGS_MASK_BIT␉␉␉␉␉0x100␉␉␉/* interrupt masking & reporting supported */␊ |
421 | #define PCI_MSI_FLAGS_64BIT␉␉␉␉␉0x080␉␉␉/* 64-bit addresses allowed */␊ |
422 | #define PCI_MSI_FLAGS_QSIZE␉␉␉␉␉0x070␉␉␉/* Message queue size configured */␊ |
423 | #define PCI_MSI_FLAGS_QMASK␉␉␉␉␉0x00e␉␉␉/* Maximum queue size available */␊ |
424 | #define PCI_MSI_FLAGS_ENABLE␉␉␉␉␉0x001␉␉␉/* MSI feature enabled */␊ |
425 | #define PCI_MSI_RFU␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
426 | #define PCI_MSI_ADDRESS_LO␉␉␉␉␉4␉␉␉/* Lower 32 bits */␊ |
427 | #define PCI_MSI_ADDRESS_HI␉␉␉␉␉8␉␉␉/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */␊ |
428 | #define PCI_MSI_DATA_32␉␉␉␉␉␉8␉␉␉/* 16 bits of data for 32-bit devices */␊ |
429 | #define PCI_MSI_DATA_64␉␉␉␉␉␉12␉␉␉/* 16 bits of data for 64-bit devices */␊ |
430 | #define PCI_MSI_MASK_BIT_32␉␉␉␉␉12␉␉␉/* per-vector masking for 32-bit devices */␊ |
431 | #define PCI_MSI_MASK_BIT_64␉␉␉␉␉16␉␉␉/* per-vector masking for 64-bit devices */␊ |
432 | #define PCI_MSI_PENDING_32␉␉␉␉␉16␉␉␉/* per-vector interrupt pending for 32-bit devices */␊ |
433 | #define PCI_MSI_PENDING_64␉␉␉␉␉20␉␉␉/* per-vector interrupt pending for 64-bit devices */␊ |
434 | ␊ |
435 | /* PCI-X */␊ |
436 | #define PCI_PCIX_COMMAND␉␉␉␉␉2␉␉␉/* Command register offset */␊ |
437 | #define PCI_PCIX_COMMAND_DPERE␉␉␉␉␉0x0001␉␉␉/* Data Parity Error Recover Enable */␊ |
438 | #define PCI_PCIX_COMMAND_ERO␉␉␉␉␉0x0002␉␉␉/* Enable Relaxed Ordering */␊ |
439 | #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT␉␉0x000c␉␉␉/* Maximum Memory Read Byte Count */␊ |
440 | #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS␉␉0x0070␊ |
441 | #define PCI_PCIX_COMMAND_RESERVED␉␉␉␉0xf80␊ |
442 | #define PCI_PCIX_STATUS␉␉␉␉␉␉4␉␉␉/* Status register offset */␊ |
443 | #define PCI_PCIX_STATUS_FUNCTION␉␉␉␉0x00000007␊ |
444 | #define PCI_PCIX_STATUS_DEVICE␉␉␉␉␉0x000000f8␊ |
445 | #define PCI_PCIX_STATUS_BUS␉␉␉␉␉0x0000ff00␊ |
446 | #define PCI_PCIX_STATUS_64BIT␉␉␉␉␉0x00010000␊ |
447 | #define PCI_PCIX_STATUS_133MHZ␉␉␉␉␉0x00020000␊ |
448 | #define PCI_PCIX_STATUS_SC_DISCARDED␉␉␉␉0x00040000␉␉/* Split Completion Discarded */␊ |
449 | #define PCI_PCIX_STATUS_UNEXPECTED_SC␉␉␉␉0x00080000␉␉/* Unexpected Split Completion */␊ |
450 | #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY␉␉␉0x00100000␉␉/* 0 = simple device, 1 = bridge device */␊ |
451 | #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT␉0x00600000␉␉/* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */␊ |
452 | #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS␉0x03800000␊ |
453 | #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE␉0x1c000000␊ |
454 | #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS␉␉␉0x20000000␉␉/* Received Split Completion Error Message */␊ |
455 | #define PCI_PCIX_STATUS_266MHZ␉␉␉␉␉0x40000000␉␉/* 266 MHz capable */␊ |
456 | #define PCI_PCIX_STATUS_533MHZ␉␉␉␉␉0x80000000␉␉/* 533 MHz capable */␊ |
457 | #define PCI_PCIX_SIZEOF␉␉␉␉␉␉4␊ |
458 | ␊ |
459 | /* PCI-X Bridges */␊ |
460 | #define PCI_PCIX_BRIDGE_SEC_STATUS␉␉␉␉2␉␉␉/* Secondary bus status register offset */␊ |
461 | #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT␉␉␉0x0001␊ |
462 | #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ␉␉␉0x0002␊ |
463 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED␉␉␉0x0004␉␉␉/* Split Completion Discarded on secondary bus */␊ |
464 | #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC␉␉0x0008␉␉␉/* Unexpected Split Completion on secondary bus */␊ |
465 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN␉␉␉0x0010␉␉␉/* Split Completion Overrun on secondary bus */␊ |
466 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED␉0x0020␊ |
467 | #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ␉␉␉0x01c0␊ |
468 | #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED␉␉␉0xfe00␊ |
469 | #define PCI_PCIX_BRIDGE_STATUS␉␉␉␉␉4␉␉␉/* Primary bus status register offset */␊ |
470 | #define PCI_PCIX_BRIDGE_STATUS_FUNCTION␉␉␉␉0x00000007␊ |
471 | #define PCI_PCIX_BRIDGE_STATUS_DEVICE␉␉␉␉0x000000f8␊ |
472 | #define PCI_PCIX_BRIDGE_STATUS_BUS␉␉␉␉0x0000ff00␊ |
473 | #define PCI_PCIX_BRIDGE_STATUS_64BIT␉␉␉␉0x00010000␊ |
474 | #define PCI_PCIX_BRIDGE_STATUS_133MHZ␉␉␉␉0x00020000␊ |
475 | #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED␉␉␉0x00040000␉␉/* Split Completion Discarded */␊ |
476 | #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC␉␉␉0x00080000␉␉/* Unexpected Split Completion */␊ |
477 | #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN␉␉␉0x00100000␉␉/* Split Completion Overrun */␊ |
478 | #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED␉␉0x00200000␊ |
479 | #define PCI_PCIX_BRIDGE_STATUS_RESERVED␉␉␉␉0xffc00000␊ |
480 | #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL␉␉8␉␉␉/* Upstream Split Transaction Register offset */␊ |
481 | #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL␉␉12␉␉␉/* Downstream Split Transaction Register offset */␊ |
482 | #define PCI_PCIX_BRIDGE_STR_CAPACITY␉␉␉␉0x0000ffff␊ |
483 | #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT␉␉␉0xffff0000␊ |
484 | #define PCI_PCIX_BRIDGE_SIZEOF 12␊ |
485 | ␊ |
486 | /* PCI Express */␊ |
487 | #define PCI_EXP_FLAGS␉␉␉␉␉␉0x2␉␉␉/* Capabilities register */␊ |
488 | #define PCI_EXP_FLAGS_VERS␉␉␉␉␉0x000f␉␉␉/* Capability version */␊ |
489 | #define PCI_EXP_FLAGS_TYPE␉␉␉␉␉0x00f0␉␉␉/* Device/Port type */␊ |
490 | #define PCI_EXP_TYPE_ENDPOINT␉␉␉␉0x0 ␉␉␉/* Express Endpoint */␊ |
491 | #define PCI_EXP_TYPE_LEG_END␉␉␉␉0x1 ␉␉␉/* Legacy Endpoint */␊ |
492 | #define PCI_EXP_TYPE_ROOT_PORT␉␉␉␉0x4 ␉␉␉/* Root Port */␊ |
493 | #define PCI_EXP_TYPE_UPSTREAM␉␉␉␉0x5 ␉␉␉/* Upstream Port */␊ |
494 | #define PCI_EXP_TYPE_DOWNSTREAM␉␉␉␉0x6 ␉␉␉/* Downstream Port */␊ |
495 | #define PCI_EXP_TYPE_PCI_BRIDGE␉␉␉␉0x7 ␉␉␉/* PCI/PCI-X Bridge */␊ |
496 | #define PCI_EXP_TYPE_PCIE_BRIDGE␉␉␉0x8 ␉␉␉/* PCI/PCI-X to PCIE Bridge */␊ |
497 | #define PCI_EXP_TYPE_ROOT_INT_EP␉␉␉0x9 ␉␉␉/* Root Complex Integrated Endpoint */␊ |
498 | #define PCI_EXP_TYPE_ROOT_EC␉␉␉␉0xa ␉␉␉/* Root Complex Event Collector */␊ |
499 | #define PCI_EXP_FLAGS_SLOT␉␉␉␉␉0x0100␉␉␉/* Slot implemented */␊ |
500 | #define PCI_EXP_FLAGS_IRQ␉␉␉␉␉0x3e00␉␉␉/* Interrupt message number */␊ |
501 | #define PCI_EXP_DEVCAP␉␉␉␉␉␉0x4 ␉␉␉/* Device capabilities */␊ |
502 | #define PCI_EXP_DEVCAP_PAYLOAD␉␉␉␉0x07␉␉␉/* Max_Payload_Size */␊ |
503 | #define PCI_EXP_DEVCAP_PHANTOM␉␉␉␉0x18␉␉␉/* Phantom functions */␊ |
504 | #define PCI_EXP_DEVCAP_EXT_TAG␉␉␉␉0x20␉␉␉/* Extended tags */␊ |
505 | #define PCI_EXP_DEVCAP_L0S␉␉␉␉␉0x1c0␉␉␉/* L0s Acceptable Latency */␊ |
506 | #define PCI_EXP_DEVCAP_L1␉␉␉␉␉0xe00␉␉␉/* L1 Acceptable Latency */␊ |
507 | #define PCI_EXP_DEVCAP_ATN_BUT␉␉␉␉0x1000␉␉␉/* Attention Button Present */␊ |
508 | #define PCI_EXP_DEVCAP_ATN_IND␉␉␉␉0x2000␉␉␉/* Attention Indicator Present */␊ |
509 | #define PCI_EXP_DEVCAP_PWR_IND␉␉␉␉0x4000␉␉␉/* Power Indicator Present */␊ |
510 | #define PCI_EXP_DEVCAP_RBE␉␉␉␉␉0x8000␉␉␉/* Role-Based Error Reporting */␊ |
511 | #define PCI_EXP_DEVCAP_PWR_VAL␉␉␉␉0x3fc0000␉␉/* Slot Power Limit Value */␊ |
512 | #define PCI_EXP_DEVCAP_PWR_SCL␉␉␉␉0xc000000␉␉/* Slot Power Limit Scale */␊ |
513 | #define PCI_EXP_DEVCAP_FLRESET␉␉␉␉0x10000000␉␉/* Function-Level Reset */␊ |
514 | #define PCI_EXP_DEVCTL␉␉␉␉␉␉0x8 /* Device Control */␊ |
515 | #define PCI_EXP_DEVCTL_CERE␉␉␉␉␉0x0001␉␉␉/* Correctable Error Reporting En. */␊ |
516 | #define PCI_EXP_DEVCTL_NFERE␉␉␉␉0x0002␉␉␉/* Non-Fatal Error Reporting Enable */␊ |
517 | #define PCI_EXP_DEVCTL_FERE␉␉␉␉␉0x0004␉␉␉/* Fatal Error Reporting Enable */␊ |
518 | #define PCI_EXP_DEVCTL_URRE␉␉␉␉␉0x0008␉␉␉/* Unsupported Request Reporting En. */␊ |
519 | #define PCI_EXP_DEVCTL_RELAXED␉␉␉␉0x0010␉␉␉/* Enable Relaxed Ordering */␊ |
520 | #define PCI_EXP_DEVCTL_PAYLOAD␉␉␉␉0x00e0␉␉␉/* Max_Payload_Size */␊ |
521 | #define PCI_EXP_DEVCTL_EXT_TAG␉␉␉␉0x0100␉␉␉/* Extended Tag Field Enable */␊ |
522 | #define PCI_EXP_DEVCTL_PHANTOM␉␉␉␉0x0200␉␉␉/* Phantom Functions Enable */␊ |
523 | #define PCI_EXP_DEVCTL_AUX_PME␉␉␉␉0x0400␉␉␉/* Auxiliary Power PM Enable */␊ |
524 | #define PCI_EXP_DEVCTL_NOSNOOP␉␉␉␉0x0800␉␉␉/* Enable No Snoop */␊ |
525 | #define PCI_EXP_DEVCTL_READRQ␉␉␉␉0x7000␉␉␉/* Max_Read_Request_Size */␊ |
526 | #define PCI_EXP_DEVCTL_BCRE␉␉␉␉␉0x8000␉␉␉/* Bridge Configuration Retry Enable */␊ |
527 | #define PCI_EXP_DEVCTL_FLRESET␉␉␉␉0x8000␉␉␉/* Function-Level Reset [bit shared with BCRE] */␊ |
528 | #define PCI_EXP_DEVSTA␉␉␉␉␉␉0xa ␉␉␉/* Device Status */␊ |
529 | #define PCI_EXP_DEVSTA_CED␉␉␉␉␉0x01␉␉␉/* Correctable Error Detected */␊ |
530 | #define PCI_EXP_DEVSTA_NFED␉␉␉␉␉0x02␉␉␉/* Non-Fatal Error Detected */␊ |
531 | #define PCI_EXP_DEVSTA_FED␉␉␉␉␉0x04␉␉␉/* Fatal Error Detected */␊ |
532 | #define PCI_EXP_DEVSTA_URD␉␉␉␉␉0x08␉␉␉/* Unsupported Request Detected */␊ |
533 | #define PCI_EXP_DEVSTA_AUXPD␉␉␉␉0x10␉␉␉/* AUX Power Detected */␊ |
534 | #define PCI_EXP_DEVSTA_TRPND␉␉␉␉0x20␉␉␉/* Transactions Pending */␊ |
535 | #define PCI_EXP_LNKCAP␉␉␉␉␉␉0xc /* Link Capabilities */␊ |
536 | #define PCI_EXP_LNKCAP_SPEED␉␉␉␉0x0000f ␉␉/* Maximum Link Speed */␊ |
537 | #define PCI_EXP_LNKCAP_WIDTH␉␉␉␉0x003f0 ␉␉/* Maximum Link Width */␊ |
538 | #define PCI_EXP_LNKCAP_ASPM␉␉␉␉␉0x00c00 ␉␉/* Active State Power Management */␊ |
539 | #define PCI_EXP_LNKCAP_L0S␉␉␉␉␉0x07000 ␉␉/* L0s Acceptable Latency */␊ |
540 | #define PCI_EXP_LNKCAP_L1␉␉␉␉␉0x38000 ␉␉/* L1 Acceptable Latency */␊ |
541 | #define PCI_EXP_LNKCAP_CLOCKPM␉␉␉␉0x40000 ␉␉/* Clock Power Management */␊ |
542 | #define PCI_EXP_LNKCAP_SURPRISE␉␉␉␉0x80000 ␉␉/* Surprise Down Error Reporting */␊ |
543 | #define PCI_EXP_LNKCAP_DLLA␉␉␉␉␉0x100000␉␉/* Data Link Layer Active Reporting */␊ |
544 | #define PCI_EXP_LNKCAP_LBNC␉␉␉␉␉0x200000␉␉/* Link Bandwidth Notification Capability */␊ |
545 | #define PCI_EXP_LNKCAP_PORT␉␉␉␉␉0xff000000␉␉/* Port Number */␊ |
546 | #define PCI_EXP_LNKCTL␉␉␉␉␉␉0x10␉␉␉/* Link Control */␊ |
547 | #define PCI_EXP_LNKCTL_ASPM␉␉␉␉␉0x0003␉␉␉/* ASPM Control */␊ |
548 | #define PCI_EXP_LNKCTL_RCB␉␉␉␉␉0x0008␉␉␉/* Read Completion Boundary */␊ |
549 | #define PCI_EXP_LNKCTL_DISABLE␉␉␉␉0x0010␉␉␉/* Link Disable */␊ |
550 | #define PCI_EXP_LNKCTL_RETRAIN␉␉␉␉0x0020␉␉␉/* Retrain Link */␊ |
551 | #define PCI_EXP_LNKCTL_CLOCK␉␉␉␉0x0040␉␉␉/* Common Clock Configuration */␊ |
552 | #define PCI_EXP_LNKCTL_XSYNCH␉␉␉␉0x0080␉␉␉/* Extended Synch */␊ |
553 | #define PCI_EXP_LNKCTL_CLOCKPM␉␉␉␉0x0100␉␉␉/* Clock Power Management */␊ |
554 | #define PCI_EXP_LNKCTL_HWAUTWD␉␉␉␉0x0200␉␉␉/* Hardware Autonomous Width Disable */␊ |
555 | #define PCI_EXP_LNKCTL_BWMIE␉␉␉␉0x0400␉␉␉/* Bandwidth Mgmt Interrupt Enable */␊ |
556 | #define PCI_EXP_LNKCTL_AUTBWIE␉␉␉␉0x0800␉␉␉/* Autonomous Bandwidth Mgmt Interrupt Enable */␊ |
557 | #define PCI_EXP_LNKSTA␉␉␉␉␉␉0x12␉␉␉/* Link Status */␊ |
558 | #define PCI_EXP_LNKSTA_SPEED␉␉␉␉0x000f␉␉␉/* Negotiated Link Speed */␊ |
559 | #define PCI_EXP_LNKSTA_WIDTH␉␉␉␉0x03f0␉␉␉/* Negotiated Link Width */␊ |
560 | #define PCI_EXP_LNKSTA_TR_ERR␉␉␉␉0x0400␉␉␉/* Training Error (obsolete) */␊ |
561 | #define PCI_EXP_LNKSTA_TRAIN␉␉␉␉0x0800␉␉␉/* Link Training */␊ |
562 | #define PCI_EXP_LNKSTA_SL_CLK␉␉␉␉0x1000␉␉␉/* Slot Clock Configuration */␊ |
563 | #define PCI_EXP_LNKSTA_DL_ACT␉␉␉␉0x2000␉␉␉/* Data Link Layer in DL_Active State */␊ |
564 | #define PCI_EXP_LNKSTA_BWMGMT␉␉␉␉0x4000␉␉␉/* Bandwidth Mgmt Status */␊ |
565 | #define PCI_EXP_LNKSTA_AUTBW␉␉␉␉0x8000␉␉␉/* Autonomous Bandwidth Mgmt Status */␊ |
566 | #define PCI_EXP_SLTCAP␉␉␉␉␉␉0x14␉␉␉/* Slot Capabilities */␊ |
567 | #define PCI_EXP_SLTCAP_ATNB␉␉␉␉␉0x0001␉␉␉/* Attention Button Present */␊ |
568 | #define PCI_EXP_SLTCAP_PWRC␉␉␉␉␉0x0002␉␉␉/* Power Controller Present */␊ |
569 | #define PCI_EXP_SLTCAP_MRL␉␉␉␉␉0x0004␉␉␉/* MRL Sensor Present */␊ |
570 | #define PCI_EXP_SLTCAP_ATNI␉␉␉␉␉0x0008␉␉␉/* Attention Indicator Present */␊ |
571 | #define PCI_EXP_SLTCAP_PWRI␉␉␉␉␉0x0010␉␉␉/* Power Indicator Present */␊ |
572 | #define PCI_EXP_SLTCAP_HPS␉␉␉␉␉0x0020␉␉␉/* Hot-Plug Surprise */␊ |
573 | #define PCI_EXP_SLTCAP_HPC␉␉␉␉␉0x0040␉␉␉/* Hot-Plug Capable */␊ |
574 | #define PCI_EXP_SLTCAP_PWR_VAL␉␉␉␉0x00007f80␉␉/* Slot Power Limit Value */␊ |
575 | #define PCI_EXP_SLTCAP_PWR_SCL␉␉␉␉0x00018000␉␉/* Slot Power Limit Scale */␊ |
576 | #define PCI_EXP_SLTCAP_INTERLOCK␉␉␉0x020000␉␉/* Electromechanical Interlock Present */␊ |
577 | #define PCI_EXP_SLTCAP_NOCMDCOMP␉␉␉0x040000␉␉/* No Command Completed Support */␊ |
578 | #define PCI_EXP_SLTCAP_PSN␉␉␉␉␉0xfff80000␉␉/* Physical Slot Number */␊ |
579 | #define PCI_EXP_SLTCTL␉␉␉␉␉␉0x18␉␉␉/* Slot Control */␊ |
580 | #define PCI_EXP_SLTCTL_ATNB␉␉␉␉␉0x0001␉␉␉/* Attention Button Pressed Enable */␊ |
581 | #define PCI_EXP_SLTCTL_PWRF␉␉␉␉␉0x0002␉␉␉/* Power Fault Detected Enable */␊ |
582 | #define PCI_EXP_SLTCTL_MRLS␉␉␉␉␉0x0004␉␉␉/* MRL Sensor Changed Enable */␊ |
583 | #define PCI_EXP_SLTCTL_PRSD␉␉␉␉␉0x0008␉␉␉/* Presence Detect Changed Enable */␊ |
584 | #define PCI_EXP_SLTCTL_CMDC␉␉␉␉␉0x0010␉␉␉/* Command Completed Interrupt Enable */␊ |
585 | #define PCI_EXP_SLTCTL_HPIE␉␉␉␉␉0x0020␉␉␉/* Hot-Plug Interrupt Enable */␊ |
586 | #define PCI_EXP_SLTCTL_ATNI␉␉␉␉␉0x00c0␉␉␉/* Attention Indicator Control */␊ |
587 | #define PCI_EXP_SLTCTL_PWRI␉␉␉␉␉0x0300␉␉␉/* Power Indicator Control */␊ |
588 | #define PCI_EXP_SLTCTL_PWRC␉␉␉␉␉0x0400␉␉␉/* Power Controller Control */␊ |
589 | #define PCI_EXP_SLTCTL_INTERLOCK␉␉␉0x0800␉␉␉/* Electromechanical Interlock Control */␊ |
590 | #define PCI_EXP_SLTCTL_LLCHG␉␉␉␉0x1000␉␉␉/* Data Link Layer State Changed Enable */␊ |
591 | #define PCI_EXP_SLTSTA␉␉␉␉␉␉0x1a␉␉␉/* Slot Status */␊ |
592 | #define PCI_EXP_SLTSTA_ATNB␉␉␉␉␉0x0001␉␉␉/* Attention Button Pressed */␊ |
593 | #define PCI_EXP_SLTSTA_PWRF␉␉␉␉␉0x0002␉␉␉/* Power Fault Detected */␊ |
594 | #define PCI_EXP_SLTSTA_MRLS␉␉␉␉␉0x0004␉␉␉/* MRL Sensor Changed */␊ |
595 | #define PCI_EXP_SLTSTA_PRSD␉␉␉␉␉0x0008␉␉␉/* Presence Detect Changed */␊ |
596 | #define PCI_EXP_SLTSTA_CMDC␉␉␉␉␉0x0010␉␉␉/* Command Completed */␊ |
597 | #define PCI_EXP_SLTSTA_MRL_ST␉␉␉␉0x0020␉␉␉/* MRL Sensor State */␊ |
598 | #define PCI_EXP_SLTSTA_PRES␉␉␉␉␉0x0040␉␉␉/* Presence Detect State */␊ |
599 | #define PCI_EXP_SLTSTA_INTERLOCK␉␉␉0x0080␉␉␉/* Electromechanical Interlock Status */␊ |
600 | #define PCI_EXP_SLTSTA_LLCHG␉␉␉␉0x0100␉␉␉/* Data Link Layer State Changed */␊ |
601 | #define PCI_EXP_RTCTL␉␉␉␉␉␉0x1c␉␉␉/* Root Control */␊ |
602 | #define PCI_EXP_RTCTL_SECEE␉␉␉␉␉0x0001␉␉␉/* System Error on Correctable Error */␊ |
603 | #define PCI_EXP_RTCTL_SENFEE␉␉␉␉0x0002␉␉␉/* System Error on Non-Fatal Error */␊ |
604 | #define PCI_EXP_RTCTL_SEFEE␉␉␉␉␉0x0004␉␉␉/* System Error on Fatal Error */␊ |
605 | #define PCI_EXP_RTCTL_PMEIE␉␉␉␉␉0x0008␉␉␉/* PME Interrupt Enable */␊ |
606 | #define PCI_EXP_RTCTL_CRSVIS␉␉␉␉0x0010␉␉␉/* Configuration Request Retry Status Visible to SW */␊ |
607 | #define PCI_EXP_RTCAP␉␉␉␉␉␉0x1e␉␉␉/* Root Capabilities */␊ |
608 | #define PCI_EXP_RTCAP_CRSVIS␉␉␉␉0x0010␉␉␉/* Configuration Request Retry Status Visible to SW */␊ |
609 | #define PCI_EXP_RTSTA␉␉␉␉␉␉0x20␉␉␉/* Root Status */␊ |
610 | #define PCI_EXP_RTSTA_PME_REQID␉␉␉␉0x0000ffff␉␉/* PME Requester ID */␊ |
611 | #define PCI_EXP_RTSTA_PME_STATUS␉␉␉0x00010000␉␉/* PME Status */␊ |
612 | #define PCI_EXP_RTSTA_PME_PENDING␉␉␉0x00020000␉␉/* PME is Pending */␊ |
613 | #define PCI_EXP_DEVCAP2␉␉␉␉␉␉0x24␉␉␉/* Device capabilities 2 */␊ |
614 | #define PCI_EXP_DEVCTL2␉␉␉␉␉␉0x28␉␉␉/* Device Control */␊ |
615 | #define PCI_EXP_DEV2_TIMEOUT_RANGE(x)␉␉((x) & 0xf)␉␉/* Completion Timeout Ranges Supported */␊ |
616 | #define PCI_EXP_DEV2_TIMEOUT_VALUE(x)␉␉((x) & 0xf)␉␉/* Completion Timeout Value */␊ |
617 | #define PCI_EXP_DEV2_TIMEOUT_DIS␉␉␉0x0010␉␉␉/* Completion Timeout Disable Supported */␊ |
618 | #define PCI_EXP_DEV2_ARI␉␉␉␉␉0x0020␉␉␉/* ARI Forwarding */␊ |
619 | #define PCI_EXP_DEVSTA2␉␉␉␉␉␉0x2a␉␉␉/* Device Status */␊ |
620 | #define PCI_EXP_LNKCAP2␉␉␉␉␉␉0x2c␉␉␉/* Link Capabilities */␊ |
621 | #define PCI_EXP_LNKCTL2␉␉␉␉␉␉0x30␉␉␉/* Link Control */␊ |
622 | #define PCI_EXP_LNKCTL2_SPEED(x)␉␉␉((x) & 0xf)␉␉/* Target Link Speed */␊ |
623 | #define PCI_EXP_LNKCTL2_CMPLNC␉␉␉␉0x0010␉␉␉/* Enter Compliance */␊ |
624 | #define PCI_EXP_LNKCTL2_SPEED_DIS␉␉␉0x0020␉␉␉/* Hardware Autonomous Speed Disable */␊ |
625 | #define PCI_EXP_LNKCTL2_DEEMPHASIS(x)␉␉(((x) >> 6) & 1)␉/* Selectable De-emphasis */␊ |
626 | #define PCI_EXP_LNKCTL2_MARGIN(x)␉␉␉(((x) >> 7) & 7)␉/* Transmit Margin */␊ |
627 | #define PCI_EXP_LNKCTL2_MOD_CMPLNC␉␉␉0x0400␉␉␉/* Enter Modified Compliance */␊ |
628 | #define PCI_EXP_LNKCTL2_CMPLNC_SOS␉␉␉0x0800␉␉␉/* Compliance SOS */␊ |
629 | #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x)␉(((x) >> 12) & 1)␉/* Compliance De-emphasis */␊ |
630 | #define PCI_EXP_LNKSTA2␉␉␉␉␉␉0x32␉␉␉/* Link Status */␊ |
631 | #define PCI_EXP_LINKSTA2_DEEMPHASIS(x)␉␉((x) & 1)␉␉/* Current De-emphasis Level */␊ |
632 | #define PCI_EXP_SLTCAP2␉␉␉␉␉␉0x34␉␉␉/* Slot Capabilities */␊ |
633 | #define PCI_EXP_SLTCTL2␉␉␉␉␉␉0x38␉␉␉/* Slot Control */␊ |
634 | #define PCI_EXP_SLTSTA2␉␉␉␉␉␉0x3a␉␉␉/* Slot Status */␊ |
635 | ␊ |
636 | /* MSI-X */␊ |
637 | #define PCI_MSIX_ENABLE␉␉␉␉␉␉0x8000␊ |
638 | #define PCI_MSIX_MASK␉␉␉␉␉␉0x4000␊ |
639 | #define PCI_MSIX_TABSIZE␉␉␉␉␉0x03ff␊ |
640 | #define PCI_MSIX_TABLE␉␉␉␉␉␉4␊ |
641 | #define PCI_MSIX_PBA␉␉␉␉␉␉8␊ |
642 | #define PCI_MSIX_BIR␉␉␉␉␉␉0x7␊ |
643 | ␊ |
644 | /* Subsystem vendor/device ID for PCI bridges */␊ |
645 | #define PCI_SSVID_VENDOR␉␉␉␉␉4␊ |
646 | #define PCI_SSVID_DEVICE␉␉␉␉␉6␊ |
647 | ␊ |
648 | /* Advanced Error Reporting */␊ |
649 | #define PCI_ERR_UNCOR_STATUS␉␉␉␉4 /* Uncorrectable Error Status */␊ |
650 | #define PCI_ERR_UNC_TRAIN␉␉␉␉␉0x00000001␉␉/* Undefined in PCIe rev1.1 & 2.0 spec */␊ |
651 | #define PCI_ERR_UNC_DLP␉␉␉␉␉␉0x00000010␉␉/* Data Link Protocol */␊ |
652 | #define PCI_ERR_UNC_SDES␉␉␉␉␉0x00000020␉␉/* Surprise Down Error */␊ |
653 | #define PCI_ERR_UNC_POISON_TLP␉␉␉␉0x00001000␉␉/* Poisoned TLP */␊ |
654 | #define PCI_ERR_UNC_FCP␉␉␉␉␉␉0x00002000␉␉/* Flow Control Protocol */␊ |
655 | #define PCI_ERR_UNC_COMP_TIME␉␉␉␉0x00004000␉␉/* Completion Timeout */␊ |
656 | #define PCI_ERR_UNC_COMP_ABORT␉␉␉␉0x00008000␉␉/* Completer Abort */␊ |
657 | #define PCI_ERR_UNC_UNX_COMP␉␉␉␉0x00010000␉␉/* Unexpected Completion */␊ |
658 | #define PCI_ERR_UNC_RX_OVER␉␉␉␉␉0x00020000␉␉/* Receiver Overflow */␊ |
659 | #define PCI_ERR_UNC_MALF_TLP␉␉␉␉0x00040000␉␉/* Malformed TLP */␊ |
660 | #define PCI_ERR_UNC_ECRC␉␉␉␉␉0x00080000␉␉/* ECRC Error Status */␊ |
661 | #define PCI_ERR_UNC_UNSUP␉␉␉␉␉0x00100000␉␉/* Unsupported Request */␊ |
662 | #define PCI_ERR_UNC_ACS_VIOL␉␉␉␉0x00200000␉␉/* ACS Violation */␊ |
663 | #define PCI_ERR_UNCOR_MASK␉␉␉␉␉8␉␉␉/* Uncorrectable Error Mask */␊ |
664 | /* Same bits as above */␊ |
665 | #define PCI_ERR_UNCOR_SEVER␉␉␉␉␉12␉␉␉/* Uncorrectable Error Severity */␊ |
666 | /* Same bits as above */␊ |
667 | #define PCI_ERR_COR_STATUS␉␉␉␉␉16␉␉␉/* Correctable Error Status */␊ |
668 | #define PCI_ERR_COR_RCVR␉␉␉␉␉0x00000001␉␉/* Receiver Error Status */␊ |
669 | #define PCI_ERR_COR_BAD_TLP␉␉␉␉␉0x00000040␉␉/* Bad TLP Status */␊ |
670 | #define PCI_ERR_COR_BAD_DLLP␉␉␉␉0x00000080␉␉/* Bad DLLP Status */␊ |
671 | #define PCI_ERR_COR_REP_ROLL␉␉␉␉0x00000100␉␉/* REPLAY_NUM Rollover */␊ |
672 | #define PCI_ERR_COR_REP_TIMER␉␉␉␉0x00001000␉␉/* Replay Timer Timeout */␊ |
673 | #define PCI_ERR_COR_REP_ANFE␉␉␉␉0x00002000␉␉/* Advisory Non-Fatal Error */␊ |
674 | #define PCI_ERR_COR_MASK␉␉␉␉␉20␉␉␉/* Correctable Error Mask */␊ |
675 | /* Same bits as above */␊ |
676 | #define PCI_ERR_CAP 24␉␉␉/* Advanced Error Capabilities */␊ |
677 | #define PCI_ERR_CAP_FEP(x)␉␉␉␉␉((x) & 31)␉␉/* First Error Pointer */␊ |
678 | #define PCI_ERR_CAP_ECRC_GENC␉␉␉␉0x00000020␉␉/* ECRC Generation Capable */␊ |
679 | #define PCI_ERR_CAP_ECRC_GENE␉␉␉␉0x00000040␉␉/* ECRC Generation Enable */␊ |
680 | #define PCI_ERR_CAP_ECRC_CHKC␉␉␉␉0x00000080␉␉/* ECRC Check Capable */␊ |
681 | #define PCI_ERR_CAP_ECRC_CHKE␉␉␉␉0x00000100␉␉/* ECRC Check Enable */␊ |
682 | #define PCI_ERR_HEADER_LOG␉␉␉␉␉28␉␉␉/* Header Log Register (16 bytes) */␊ |
683 | #define PCI_ERR_ROOT_COMMAND␉␉␉␉44␉␉␉/* Root Error Command */␊ |
684 | #define PCI_ERR_ROOT_STATUS␉␉␉␉␉48␊ |
685 | #define PCI_ERR_ROOT_COR_SRC␉␉␉␉52␊ |
686 | #define PCI_ERR_ROOT_SRC␉␉␉␉␉54␊ |
687 | ␊ |
688 | /* Virtual Channel */␊ |
689 | #define PCI_VC_PORT_REG1␉␉␉␉␉4␊ |
690 | #define PCI_VC_PORT_REG2␉␉␉␉␉8␊ |
691 | #define PCI_VC_PORT_CTRL␉␉␉␉␉12␊ |
692 | #define PCI_VC_PORT_STATUS␉␉␉␉␉14␊ |
693 | #define PCI_VC_RES_CAP␉␉␉␉␉␉16␊ |
694 | #define PCI_VC_RES_CTRL␉␉␉␉␉␉20␊ |
695 | #define PCI_VC_RES_STATUS␉␉␉␉␉26␊ |
696 | ␊ |
697 | /* Power Budgeting */␊ |
698 | #define PCI_PWR_DSR 4 /* Data Select Register */␊ |
699 | #define PCI_PWR_DATA␉␉␉␉␉␉8 /* Data Register */␊ |
700 | #define PCI_PWR_DATA_BASE(x)␉␉␉␉((x) & 0xff)␉␉/* Base Power */␊ |
701 | #define PCI_PWR_DATA_SCALE(x)␉␉␉␉(((x) >> 8) & 3)␉/* Data Scale */␊ |
702 | #define PCI_PWR_DATA_PM_SUB(x)␉␉␉␉(((x) >> 10) & 7)␉/* PM Sub State */␊ |
703 | #define PCI_PWR_DATA_PM_STATE(x)␉␉␉(((x) >> 13) & 3)␉/* PM State */␊ |
704 | #define PCI_PWR_DATA_TYPE(x)␉␉␉␉(((x) >> 15) & 7)␉/* Type */␊ |
705 | #define PCI_PWR_DATA_RAIL(x)␉␉␉␉(((x) >> 18) & 7)␉/* Power Rail */␊ |
706 | #define PCI_PWR_CAP 12 /* Capability */␊ |
707 | #define PCI_PWR_CAP_BUDGET(x)␉␉␉␉((x) & 1) /* Included in system budget */␊ |
708 | ␊ |
709 | /* Access Control Services */␊ |
710 | #define PCI_ACS_CAP 0x04␉␉␉/* ACS Capability Register */␊ |
711 | #define PCI_ACS_CAP_VALID␉␉␉␉␉0x0001␉␉␉/* ACS Source Validation */␊ |
712 | #define PCI_ACS_CAP_BLOCK␉␉␉␉␉0x0002␉␉␉/* ACS Translation Blocking */␊ |
713 | #define PCI_ACS_CAP_REQ_RED␉␉␉␉␉0x0004␉␉␉/* ACS P2P Request Redirect */␊ |
714 | #define PCI_ACS_CAP_CMPLT_RED␉␉␉␉0x0008␉␉␉/* ACS P2P Completion Redirect */␊ |
715 | #define PCI_ACS_CAP_FORWARD␉␉␉␉␉0x0010␉␉␉/* ACS Upstream Forwarding */␊ |
716 | #define PCI_ACS_CAP_EGRESS␉␉␉␉␉0x0020␉␉␉/* ACS P2P Egress Control */␊ |
717 | #define PCI_ACS_CAP_TRANS␉␉␉␉␉0x0040␉␉␉/* ACS Direct Translated P2P */␊ |
718 | #define PCI_ACS_CAP_VECTOR(x)␉␉␉␉(((x) >> 8) & 0xff)␉/* Egress Control Vector Size */␊ |
719 | #define PCI_ACS_CTRL␉␉␉␉␉␉0x06␉␉␉/* ACS Control Register */␊ |
720 | #define PCI_ACS_CTRL_VALID␉␉␉␉␉0x0001␉␉␉/* ACS Source Validation Enable */␊ |
721 | #define PCI_ACS_CTRL_BLOCK␉␉␉␉␉0x0002␉␉␉/* ACS Translation Blocking Enable */␊ |
722 | #define PCI_ACS_CTRL_REQ_RED␉␉␉␉0x0004␉␉␉/* ACS P2P Request Redirect Enable */␊ |
723 | #define PCI_ACS_CTRL_CMPLT_RED␉␉␉␉0x0008␉␉␉/* ACS P2P Completion Redirect Enable */␊ |
724 | #define PCI_ACS_CTRL_FORWARD␉␉␉␉0x0010␉␉␉/* ACS Upstream Forwarding Enable */␊ |
725 | #define PCI_ACS_CTRL_EGRESS␉␉␉␉␉0x0020␉␉␉/* ACS P2P Egress Control Enable */␊ |
726 | #define PCI_ACS_CTRL_TRANS␉␉␉␉␉0x0040␉␉␉/* ACS Direct Translated P2P Enable */␊ |
727 | #define PCI_ACS_EGRESS_CTRL␉␉␉␉␉0x08␉␉␉/* Egress Control Vector */␊ |
728 | ␊ |
729 | /* Alternative Routing-ID Interpretation */␊ |
730 | #define PCI_ARI_CAP 0x04␉␉␉/* ARI Capability Register */␊ |
731 | #define PCI_ARI_CAP_MFVC␉␉␉␉␉0x0001␉␉␉/* MFVC Function Groups Capability */␊ |
732 | #define PCI_ARI_CAP_ACS␉␉␉␉␉␉0x0002␉␉␉/* ACS Function Groups Capability */␊ |
733 | #define PCI_ARI_CAP_NFN(x)␉␉␉␉␉(((x) >> 8) & 0xff)␉/* Next Function Number */␊ |
734 | #define PCI_ARI_CTRL␉␉␉␉␉␉0x06␉␉␉/* ARI Control Register */␊ |
735 | #define PCI_ARI_CTRL_MFVC␉␉␉␉␉0x0001␉␉␉/* MFVC Function Groups Enable */␊ |
736 | #define PCI_ARI_CTRL_ACS␉␉␉␉␉0x0002␉␉␉/* ACS Function Groups Enable */␊ |
737 | #define PCI_ARI_CTRL_FG(x)␉␉␉␉␉(((x) >> 4) & 7)␉/* Function Group */␊ |
738 | ␊ |
739 | /* Address Translation Service */␊ |
740 | #define PCI_ATS_CAP 0x04␉␉␉/* ATS Capability Register */␊ |
741 | #define PCI_ATS_CAP_IQD(x)␉␉␉␉␉((x) & 0x1f)␉␉/* Invalidate Queue Depth */␊ |
742 | #define PCI_ATS_CTRL␉␉␉␉␉␉0x06␉␉␉/* ATS Control Register */␊ |
743 | #define PCI_ATS_CTRL_STU(x)␉␉␉␉␉((x) & 0x1f)␉␉/* Smallest Translation Unit */␊ |
744 | #define PCI_ATS_CTRL_ENABLE␉␉␉␉␉0x8000␉␉␉/* ATS Enable */␊ |
745 | ␊ |
746 | /* Single Root I/O Virtualization */␊ |
747 | #define PCI_IOV_CAP 0x04␉␉␉/* SR-IOV Capability Register */␊ |
748 | #define PCI_IOV_CAP_VFM␉␉␉␉␉␉0x00000001␉␉/* VF Migration Capable */␊ |
749 | #define PCI_IOV_CAP_IMN(x)␉␉␉␉␉((x) >> 21)␉␉/* VF Migration Interrupt Message Number */␊ |
750 | #define PCI_IOV_CTRL␉␉␉␉␉␉0x08␉␉␉/* SR-IOV Control Register */␊ |
751 | #define PCI_IOV_CTRL_VFE␉␉␉␉␉0x0001␉␉␉/* VF Enable */␊ |
752 | #define PCI_IOV_CTRL_VFME␉␉␉␉␉0x0002␉␉␉/* VF Migration Enable */␊ |
753 | #define PCI_IOV_CTRL_VFMIE␉␉␉␉␉0x0004␉␉␉/* VF Migration Interrupt Enable */␊ |
754 | #define PCI_IOV_CTRL_MSE␉␉␉␉␉0x0008␉␉␉/* VF MSE */␊ |
755 | #define PCI_IOV_CTRL_ARI␉␉␉␉␉0x0010␉␉␉/* ARI Capable Hierarchy */␊ |
756 | #define PCI_IOV_STATUS␉␉␉␉␉␉0x0a␉␉␉/* SR-IOV Status Register */␊ |
757 | #define PCI_IOV_STATUS_MS␉␉␉␉␉0x0001␉␉␉/* VF Migration Status */␊ |
758 | #define PCI_IOV_INITIALVF␉␉␉␉␉0x0c␉␉␉/* Number of VFs that are initially associated */␊ |
759 | #define PCI_IOV_TOTALVF␉␉␉␉␉␉0x0e␉␉␉/* Maximum number of VFs that could be associated */␊ |
760 | #define PCI_IOV_NUMVF␉␉␉␉␉␉0x10␉␉␉/* Number of VFs that are available */␊ |
761 | #define PCI_IOV_FDL 0x12␉␉␉/* Function Dependency Link */␊ |
762 | #define PCI_IOV_OFFSET␉␉␉␉␉␉0x14␉␉␉/* First VF Offset */␊ |
763 | #define PCI_IOV_STRIDE␉␉␉␉␉␉0x16␉␉␉/* Routing ID offset from one VF to the next one */␊ |
764 | #define PCI_IOV_DID 0x1a␉␉␉/* VF Device ID */␊ |
765 | #define PCI_IOV_SUPPS␉␉␉␉␉␉0x1c␉␉␉/* Supported Page Sizes */␊ |
766 | #define PCI_IOV_SYSPS␉␉␉␉␉␉0x20␉␉␉/* System Page Size */␊ |
767 | #define PCI_IOV_BAR_BASE␉␉␉␉␉0x24␉␉␉/* VF BAR0, VF BAR1, ... VF BAR5 */␊ |
768 | #define PCI_IOV_NUM_BAR␉␉␉␉␉␉6␉␉␉/* Number of VF BARs */␊ |
769 | #define PCI_IOV_MSAO␉␉␉␉␉␉0x3c␉␉␉/* VF Migration State Array Offset */␊ |
770 | #define PCI_IOV_MSA_BIR(x)␉␉␉␉␉((x) & 7)␉␉/* VF Migration State BIR */␊ |
771 | #define PCI_IOV_MSA_OFFSET(x)␉␉␉␉␉((x) & 0xfffffff8)␉/* VF Migration State Offset */␊ |
772 | ␊ |
773 | /*␊ |
774 | * The PCI interface treats multi-function devices as independent␊ |
775 | * devices. The slot/function address of each device is encoded␊ |
776 | * in a single byte as follows:␊ |
777 | *␊ |
778 | *␉7:3 = slot␊ |
779 | *␉2:0 = function␊ |
780 | */␊ |
781 | #define PCI_DEVFN(slot,func)␉␉␉␉␉((((slot) & 0x1f) << 3) | ((func) & 0x07))␊ |
782 | #define PCI_SLOT(devfn)␉␉␉␉␉␉(((devfn) >> 3) & 0x1f)␊ |
783 | #define PCI_FUNC(devfn)␉␉␉␉␉␉((devfn) & 0x07)␊ |
784 | ␊ |
785 | /* Device classes and subclasses */␊ |
786 | #define PCI_CLASS_NOT_DEFINED␉␉␉␉␉0x0000␊ |
787 | #define PCI_CLASS_NOT_DEFINED_VGA␉␉␉␉0x0001␊ |
788 | ␊ |
789 | // values for the class_sub field for class_base = 0x00 (Device was built prior definition of the class code field)␊ |
790 | ␊ |
791 | // values for the class_sub field for class_base = 0x01 (Mass Storage Controller)␊ |
792 | #define PCI_BASE_CLASS_STORAGE␉␉␉␉␉0x01␊ |
793 | #define PCI_CLASS_STORAGE_SCSI␉␉␉␉␉0x0100␊ |
794 | #define PCI_CLASS_STORAGE_IDE␉␉␉␉␉0x0101␊ |
795 | #define PCI_CLASS_STORAGE_FLOPPY␉␉␉␉0x0102␊ |
796 | #define PCI_CLASS_STORAGE_IPI␉␉␉␉␉0x0103␊ |
797 | #define PCI_CLASS_STORAGE_RAID␉␉␉␉␉0x0104␊ |
798 | #define PCI_CLASS_STORAGE_ATA␉␉␉␉␉0x0105␊ |
799 | #define PCI_CLASS_STORAGE_SATA␉␉␉␉␉0x0106␊ |
800 | #define PCI_CLASS_STORAGE_SATA_AHCI␉␉␉␉0x010601␊ |
801 | #define PCI_CLASS_STORAGE_SAS␉␉␉␉␉0x0107␊ |
802 | #define PCI_CLASS_STORAGE_OTHER␉␉␉␉␉0x0180␊ |
803 | ␊ |
804 | // values for the class_sub field for class_base = 0x02 (Network Controller)␊ |
805 | #define PCI_BASE_CLASS_NETWORK␉␉␉␉␉0x02␊ |
806 | #define PCI_CLASS_NETWORK_ETHERNET␉␉␉␉0x0200␊ |
807 | #define PCI_CLASS_NETWORK_TOKEN_RING␉␉␉0x0201␊ |
808 | #define PCI_CLASS_NETWORK_FDDI␉␉␉␉␉0x0202␊ |
809 | #define PCI_CLASS_NETWORK_ATM␉␉␉␉␉0x0203␊ |
810 | #define PCI_CLASS_NETWORK_ISDN␉␉␉␉␉0x0204␊ |
811 | #define PCI_CLASS_NETWORK_OTHER␉␉␉␉␉0x0280␊ |
812 | ␊ |
813 | // values for the class_sub field for class_base = 0x03 (Display Controller)␊ |
814 | #define PCI_BASE_CLASS_DISPLAY␉␉␉␉␉0x03␊ |
815 | #define PCI_CLASS_DISPLAY_VGA␉␉␉␉␉0x0300␊ |
816 | #define PCI_CLASS_DISPLAY_XGA␉␉␉␉␉0x0301␊ |
817 | #define PCI_CLASS_DISPLAY_3D␉␉␉␉␉0x0302␊ |
818 | #define PCI_CLASS_DISPLAY_OTHER␉␉␉␉␉0x0380␊ |
819 | ␊ |
820 | // values for the class_sub field for class_base = 0x04 (Multimedia Controller)␊ |
821 | #define PCI_BASE_CLASS_MULTIMEDIA␉␉␉␉0x04␊ |
822 | #define PCI_CLASS_MULTIMEDIA_VIDEO␉␉␉␉0x0400 /* video */␊ |
823 | #define PCI_CLASS_MULTIMEDIA_AUDIO␉␉␉␉0x0401 /* audio */␊ |
824 | #define PCI_CLASS_MULTIMEDIA_PHONE␉␉␉␉0x0402␊ |
825 | #define PCI_CLASS_MULTIMEDIA_AUDIO_DEV␉␉␉0x0403 /* HD audio */␊ |
826 | #define PCI_CLASS_MULTIMEDIA_OTHER␉␉␉␉0x0480␊ |
827 | ␊ |
828 | // values for the class_sub field for class_base = 0x05 (Memory Controller)␊ |
829 | #define PCI_BASE_CLASS_MEMORY␉␉␉␉␉0x05␊ |
830 | #define PCI_CLASS_MEMORY_RAM␉␉␉␉␉0x0500␊ |
831 | #define PCI_CLASS_MEMORY_FLASH␉␉␉␉␉0x0501␊ |
832 | #define PCI_CLASS_MEMORY_OTHER␉␉␉␉␉0x0580␊ |
833 | ␊ |
834 | // values for the class_sub field for class_base = 0x06 (Bridge Device)␊ |
835 | #define PCI_BASE_CLASS_BRIDGE␉␉␉␉␉0x06␊ |
836 | #define PCI_CLASS_BRIDGE_HOST␉␉␉␉␉0x0600␊ |
837 | #define PCI_CLASS_BRIDGE_ISA␉␉␉␉␉0x0601␊ |
838 | #define PCI_CLASS_BRIDGE_EISA␉␉␉␉␉0x0602␊ |
839 | #define PCI_CLASS_BRIDGE_MC␉␉␉␉␉0x0603␊ |
840 | #define PCI_CLASS_BRIDGE_PCI␉␉␉␉␉0x0604␊ |
841 | #define PCI_CLASS_BRIDGE_PCMCIA␉␉␉␉␉0x0605␊ |
842 | #define PCI_CLASS_BRIDGE_NUBUS␉␉␉␉␉0x0606␊ |
843 | #define PCI_CLASS_BRIDGE_CARDBUS␉␉␉␉0x0607␊ |
844 | #define PCI_CLASS_BRIDGE_RACEWAY␉␉␉␉0x0608␊ |
845 | #define PCI_CLASS_BRIDGE_PCI_SEMI␉␉␉␉0x0609␊ |
846 | #define PCI_CLASS_BRIDGE_IB_TO_PCI␉␉␉␉0x060a␊ |
847 | #define PCI_CLASS_BRIDGE_OTHER␉␉␉␉␉0x0680␊ |
848 | ␊ |
849 | // values for the class_sub field for class_base = 0x07 (Simple Communications Controllers)␊ |
850 | #define PCI_BASE_CLASS_COMMUNICATION␉␉␉␉0x07␊ |
851 | #define PCI_CLASS_COMMUNICATION_SERIAL␉␉␉␉0x0700␊ |
852 | #define PCI_CLASS_COMMUNICATION_PARALLEL␉␉␉0x0701␊ |
853 | #define PCI_CLASS_COMMUNICATION_MSERIAL␉␉␉␉0x0702␊ |
854 | #define PCI_CLASS_COMMUNICATION_MODEM␉␉␉␉0x0703␊ |
855 | #define PCI_CLASS_COMMUNICATION_OTHER␉␉␉␉0x0780␊ |
856 | ␊ |
857 | // values for the class_sub field for class_base = 0x08 (Base System Peripherals)␊ |
858 | #define PCI_BASE_CLASS_SYSTEM␉␉␉␉␉0x08 //␊ |
859 | #define PCI_CLASS_SYSTEM_PIC␉␉␉␉␉0x0800 //␊ |
860 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC␉␉␉␉0x080010␊ |
861 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC␉␉␉0x080020 // I/O APIC interrupt controller , 32 bye none-prefectable memory.␊ |
862 | #define PCI_CLASS_SYSTEM_DMA␉␉␉␉␉0x0801␊ |
863 | #define PCI_CLASS_SYSTEM_TIMER␉␉␉␉␉0x0802␊ |
864 | #define PCI_CLASS_SYSTEM_RTC␉␉␉␉␉0x0803␊ |
865 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG␉␉␉0x0804 // HotPlug Controller␊ |
866 | #define PCI_CLASS_SYSTEM_SDHCI␉␉␉␉␉0x0805␊ |
867 | #define PCI_CLASS_SYSTEM_OTHER␉␉␉␉␉0x0880␊ |
868 | ␊ |
869 | // values for the class_sub field for class_base = 0x09 (Input Devices)␊ |
870 | #define PCI_BASE_CLASS_INPUT␉␉␉␉␉0x09␊ |
871 | #define PCI_CLASS_INPUT_KEYBOARD␉␉␉␉0x0900␊ |
872 | #define PCI_CLASS_INPUT_PEN␉␉␉␉␉0x0901␊ |
873 | #define PCI_CLASS_INPUT_MOUSE␉␉␉␉␉0x0902␊ |
874 | #define PCI_CLASS_INPUT_SCANNER␉␉␉␉␉0x0903␊ |
875 | #define PCI_CLASS_INPUT_GAMEPORT␉␉␉␉0x0904␊ |
876 | #define PCI_CLASS_INPUT_OTHER␉␉␉␉␉0x0980␊ |
877 | ␊ |
878 | // values for the class_sub field for class_base = 0x0a (Docking Stations)␊ |
879 | #define PCI_BASE_CLASS_DOCKING␉␉␉␉␉0x0a␊ |
880 | #define PCI_CLASS_DOCKING_GENERIC␉␉␉␉0x0a00␊ |
881 | #define PCI_CLASS_DOCKING_OTHER␉␉␉␉␉0x0a80␊ |
882 | ␊ |
883 | // values for the class_sub field for class_base = 0x0b (processor)␊ |
884 | #define PCI_BASE_CLASS_PROCESSOR␉␉␉␉0x0b␊ |
885 | #define PCI_CLASS_PROCESSOR_386␉␉␉␉␉0x0b00␊ |
886 | #define PCI_CLASS_PROCESSOR_486␉␉␉␉␉0x0b01␊ |
887 | #define PCI_CLASS_PROCESSOR_PENTIUM␉␉␉␉0x0b02␊ |
888 | #define PCI_CLASS_PROCESSOR_ALPHA␉␉␉␉0x0b10␊ |
889 | #define PCI_CLASS_PROCESSOR_POWERPC␉␉␉␉0x0b20␊ |
890 | #define PCI_CLASS_PROCESSOR_MIPS␉␉␉␉0x0b30␊ |
891 | #define PCI_CLASS_PROCESSOR_CO␉␉␉␉␉0x0b40 // Co-Processor␊ |
892 | ␊ |
893 | // values for the class_sub field for class_base = 0x0c (serial bus controller)␊ |
894 | #define PCI_BASE_CLASS_SERIAL␉␉␉␉␉0x0c␊ |
895 | #define PCI_CLASS_SERIAL_FIREWIRE␉␉␉␉0x0c00 /* FireWire (IEEE 1394) */␊ |
896 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI␉␉␉0x0c10␊ |
897 | #define PCI_CLASS_SERIAL_ACCESS␉␉␉␉␉0x0c01␊ |
898 | #define PCI_CLASS_SERIAL_SSA␉␉␉␉␉0x0c02␊ |
899 | #define PCI_CLASS_SERIAL_USB␉␉␉␉␉0x0c03 /* Universal Serial Bus */␊ |
900 | #define PCI_IF_UHCI 0x00 /* Universal Host Controller Interface */␊ |
901 | #define PCI_IF_OHCI 0x10 /* Open Host Controller Interface */␊ |
902 | #define PCI_IF_EHCI 0x20 /* Enhanced Host Controller Interface */␊ |
903 | #define PCI_IF_XHCI 0x30 /* Extensible Host Controller Interface */␊ |
904 | #define PCI_CLASS_SERIAL_FIBER␉␉␉␉␉0x0c04␊ |
905 | #define PCI_CLASS_SERIAL_SMBUS␉␉␉␉␉0x0c05␊ |
906 | #define PCI_CLASS_SERIAL_INFINIBAND␉␉␉␉0x0c06␊ |
907 | ␊ |
908 | // values for the class_sub field for class_base = 0x0d (Wireless Controller)␊ |
909 | #define PCI_BASE_CLASS_WIRELESS␉␉␉␉␉0x0d␊ |
910 | #define PCI_CLASS_WIRELESS_IRDA␉␉␉␉␉0x0d00␊ |
911 | #define PCI_CLASS_WIRELESS_IR␉␉␉␉␉0x0d01␊ |
912 | #define PCI_CLASS_WIRELESS_RF␉␉␉␉␉0x0d10␊ |
913 | #define PCI_CLASS_WIRELESS_BLUETOOTH␉␉␉0x0d11␊ |
914 | #define PCI_CLASS_WIRELESS_BROADBAND␉␉␉0x0d12␊ |
915 | #define PCI_CLASS_WIRELESS_80211A␉␉␉␉0x0d20␊ |
916 | #define PCI_CLASS_WIRELESS_80211B␉␉␉␉0x0d21␊ |
917 | #define PCI_CLASS_WIRELESS_WHCI␉␉␉␉␉0x0d1010␊ |
918 | #define PCI_CLASS_WIRELESS_OTHER␉␉␉␉0x80␊ |
919 | ␊ |
920 | // values for the class_sub field for class_base = 0x0e (Intelligent I/O Controller)␊ |
921 | #define PCI_BASE_CLASS_INTELLIGENT␉␉␉␉0x0e␊ |
922 | #define PCI_CLASS_INTELLIGENT_I2O␉␉␉␉0x0e00␊ |
923 | ␊ |
924 | // values for the class_sub field for class_base = 0x0f (Satellite Communication Controller)␊ |
925 | #define PCI_BASE_CLASS_SATELLITE␉␉␉␉0x0f␊ |
926 | #define PCI_CLASS_SATELLITE_TV␉␉␉␉␉0x0f00␊ |
927 | #define PCI_CLASS_SATELLITE_AUDIO␉␉␉␉0x0f01␊ |
928 | #define PCI_CLASS_SATELLITE_VOICE␉␉␉␉0x0f03␊ |
929 | #define PCI_CLASS_SATELLITE_DATA␉␉␉␉0x0f04␊ |
930 | ␊ |
931 | // values for the class_sub field for class_base = 0x10 (Encryption and decryption controller)␊ |
932 | #define PCI_BASE_CLASS_CRYPT␉␉␉␉␉0x10␊ |
933 | #define PCI_CLASS_CRYPT_NETWORK␉␉␉␉␉0x1000␊ |
934 | #define PCI_CLASS_CRYPT_ENTERTAINMENT␉␉␉␉0x1010␊ |
935 | #define PCI_CLASS_CRYPT_OTHER␉␉␉␉␉0x1080␊ |
936 | // values for the class_sub field for class_base = 0x12 (Data Acquisition and Signal Processing Controllers)␊ |
937 | #define PCI_BASE_CLASS_SIGNAL␉␉␉␉␉0x11␊ |
938 | #define PCI_CLASS_SIGNAL_DPIO␉␉␉␉␉0x1100␊ |
939 | #define PCI_CLASS_SIGNAL_PERF_CTR␉␉␉␉0x1101␊ |
940 | #define PCI_CLASS_SIGNAL_SYNCHRONIZER␉␉␉␉0x1110␊ |
941 | #define PCI_CLASS_SIGNAL_OTHER␉␉␉␉␉0x1180␊ |
942 | ␊ |
943 | // values for the class_sub field for class_base = 0xff (Device does not fit any defined class)␊ |
944 | #define PCI_CLASS_OTHERS 0xff␊ |
945 | ␊ |
946 | /* Several ID's we need in the library */␊ |
947 | #define PCI_VENDOR_ID_LOGITECH 0x046d␊ |
948 | #define PCI_VENDOR_ID_WACOM 0x056a␊ |
949 | #define PCI_VENDOR_ID_COMPAQ 0x0e11␊ |
950 | #define PCI_VENDOR_ID_NCR 0x1000␊ |
951 | #define PCI_VENDOR_ID_ATI 0x1002␊ |
952 | #define PCI_VENDOR_ID_NS 0x100b␊ |
953 | #define PCI_VENDOR_ID_TSENG 0x100c␊ |
954 | #define PCI_VENDOR_ID_WEITEK 0x100e␊ |
955 | #define PCI_VENDOR_ID_DEC 0x1011␊ |
956 | #define PCI_VENDOR_ID_CIRRUS 0x1013␊ |
957 | #define PCI_VENDOR_ID_IBM 0x1014␊ |
958 | #define PCI_VENDOR_ID_AMD 0x1022␊ |
959 | #define PCI_VENDOR_ID_DELL 0x1028␊ |
960 | #define PCI_VENDOR_ID_MATROX 0x102B␊ |
961 | #define PCI_VENDOR_ID_NEC 0x1033␊ |
962 | #define PCI_VENDOR_ID_FD 0x1036␊ |
963 | #define PCI_VENDOR_ID_SI 0x1039␊ |
964 | #define PCI_VENDOR_ID_HP 0x103c␊ |
965 | #define PCI_VENDOR_ID_ASUS 0x1043␊ |
966 | #define PCI_VENDOR_ID_TI 0x104c // Texas Istruments␊ |
967 | #define PCI_VENDOR_ID_SONY 0x104d␊ |
968 | #define PCI_VENDOR_ID_HITACHI 0x1054␊ |
969 | #define PCI_VENDOR_ID_MOTOROLA 0x1057␊ |
970 | #define PCI_VENDOR_ID_APPLE 0x106b␊ |
971 | #define PCI_VENDOR_ID_SUN 0x108e␊ |
972 | #define PCI_VENDOR_ID_CMD 0x1095␊ |
973 | #define PCI_VENDOR_ID_NVIDIA 0x10de␊ |
974 | #define PCI_VENDOR_ID_REALTEK 0x10ec␊ |
975 | #define PCI_VENDOR_ID_VIA 0x1106␊ |
976 | #define PCI_VENDOR_ID_DLINK 0x1186␊ |
977 | #define PCI_VENDOR_ID_MARVELL 0x11ab␊ |
978 | #define PCI_VENDOR_ID_NETGEAR 0x1385␊ |
979 | #define PCI_VENDOR_ID_IOMEGA 0x13ca␊ |
980 | #define PCI_VENDOR_ID_SAMSUNG 0x144d␊ |
981 | #define PCI_VENDOR_ID_GIGABYTE 0x1458␊ |
982 | #define PCI_VENDOR_ID_BROADCOM 0x14e4␊ |
983 | #define PCI_VENDOR_ID_ATHEROS 0x168c␊ |
984 | #define PCI_VENDOR_ID_LINKSYS 0x1737␊ |
985 | #define PCI_VENDOR_ID_BELKIN 0x1799␊ |
986 | #define PCI_VENDOR_ID_LENOVO 0x17aa␊ |
987 | #define PCI_VENDOR_ID_RALINK 0x1814␊ |
988 | #define PCI_VENDOR_ID_SITECOM 0x182d␊ |
989 | #define PCI_VENDOR_ID_JMICRON 0x197B␊ |
990 | #define PCI_VENDOR_ID_OCZ 0x1b85␊ |
991 | #define PCI_VENDOR_ID_INTEL 0x8086␊ |
992 | ␊ |
993 | #endif /* !__LIBSAIO_PCI_H */␊ |
994 | |