1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
34 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
36 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
37 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
38 | ␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊ |
39 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
40 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
41 | ␊ |
42 | ␉␉␉␉␉␉value->word = 0;␊ |
43 | ␉␉␉␉␉␉break;␊ |
44 | ␉␉␉␉␉default:␊ |
45 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊ |
46 | ␉␉␉␉}␊ |
47 | ␉␉␉}␊ |
48 | ␉␉␉␉break;␊ |
49 | ␊ |
50 | ␉␉␉default:␊ |
51 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊ |
52 | ␉␉}␊ |
53 | ␉}␊ |
54 | ␉else␊ |
55 | ␉{␊ |
56 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊ |
57 | ␉}␊ |
58 | ␊ |
59 | ␉return true;␊ |
60 | }␊ |
61 | ␊ |
62 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
63 | {␊ |
64 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000);␊ |
65 | ␉return true;␊ |
66 | }␊ |
67 | ␊ |
68 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
69 | {␊ |
70 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
71 | ␉{␉␉␊ |
72 | ␉␉switch (Platform.CPU.Family) ␊ |
73 | ␉␉{␊ |
74 | ␉␉␉case 0x06:␊ |
75 | ␉␉␉{␊ |
76 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
77 | ␉␉␉␉{␊ |
78 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
79 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
80 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
81 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
82 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
83 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
84 | ␉␉␉␉␉␉return false;␊ |
85 | ␊ |
86 | ␉␉␉␉␉case 0x19:␊ |
87 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
88 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
89 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
90 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
91 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
92 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
93 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
94 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
95 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
96 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
97 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
98 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
99 | ␉␉␉␉␉{␊ |
100 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
101 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
102 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
103 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
104 | ␉␉␉␉␉␉unsigned int i;␊ |
105 | ␉␉␉␉␉␉␊ |
106 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
107 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
108 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
109 | ␉␉␉␉␉␉{␊ |
110 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
111 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
112 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
113 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
114 | ␉␉␉␉␉␉␉␊ |
115 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
116 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
117 | ␉␉␉␉␉␉}␊ |
118 | ␊ |
119 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
120 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
121 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
122 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
123 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
124 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
125 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
126 | ␉␉␉␉␉␉{␊ |
127 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
128 | ␉␉␉␉␉␉}␊ |
129 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
130 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
131 | ␉␉␉␉␉␉return true;␊ |
132 | ␉␉␉␉␉}␊ |
133 | ␉␉␉␉␉default:␊ |
134 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
135 | ␉␉␉␉}␊ |
136 | ␉␉␉}␊ |
137 | ␉␉␉default:␊ |
138 | ␉␉␉␉break;␊ |
139 | ␉␉}␊ |
140 | ␉}␊ |
141 | ␉return false;␊ |
142 | }␊ |
143 | ␊ |
144 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
145 | {␊ |
146 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
147 | ␉{␊ |
148 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
149 | ␉}␊ |
150 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
151 | ␉{␊ |
152 | ␉␉return 0x0201;␉// Core Solo␊ |
153 | ␉};␊ |
154 | ␉␊ |
155 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
156 | }␊ |
157 | ␊ |
158 | bool getSMBOemProcessorType(returnType *value)␊ |
159 | {␊ |
160 | ␉static bool done = false;␉␉␊ |
161 | ␊ |
162 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
163 | ␊ |
164 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
165 | ␉{␊ |
166 | ␉␉if (!done)␊ |
167 | ␉␉{␊ |
168 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
169 | ␉␉␉done = true;␊ |
170 | ␉␉}␊ |
171 | ␊ |
172 | ␉␉switch (Platform.CPU.Family) ␊ |
173 | ␉␉{␊ |
174 | ␉␉␉case 0x06:␊ |
175 | ␉␉␉{␊ |
176 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
177 | ␉␉␉␉{␊ |
178 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
179 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊ |
180 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
181 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
182 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
183 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
184 | ␉␉␉␉␉␉return true;␊ |
185 | ␊ |
186 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
187 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
188 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
189 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
190 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
191 | ␉␉␉␉␉␉{␊ |
192 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊ |
193 | ␉␉␉␉␉␉}␊ |
194 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
195 | ␉␉␉␉␉␉{␊ |
196 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
197 | ␉␉␉␉␉␉}␊ |
198 | ␉␉␉␉␉␉return true;␊ |
199 | ␊ |
200 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
201 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
202 | ␉␉␉␉␉␉{␊ |
203 | ␉␉␉␉␉␉␉value->word = 0x501;// Xeon␊ |
204 | ␉␉␉␉␉␉}␊ |
205 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
206 | ␉␉␉␉␉␉{␊ |
207 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
208 | ␉␉␉␉␉␉}␊ |
209 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
210 | ␉␉␉␉␉␉{␊ |
211 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊ |
212 | ␉␉␉␉␉␉}␊ |
213 | ␊ |
214 | ␉␉␉␉␉␉return true;␊ |
215 | ␊ |
216 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
217 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
218 | ␉␉␉␉␉␉{␊ |
219 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
220 | ␉␉␉␉␉␉}␊ |
221 | ␉␉␉␉␉␉else␊ |
222 | ␉␉␉␉␉␉{␊ |
223 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
224 | ␉␉␉␉␉␉}␊ |
225 | ␉␉␉␉␉␉return true;␊ |
226 | ␊ |
227 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
228 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
229 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
230 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
231 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
232 | ␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊ |
233 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
234 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
235 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
236 | ␉␉␉␉␉␉{␊ |
237 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉// Xeon␊ |
238 | ␉␉␉␉␉␉}␊ |
239 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
240 | ␉␉␉␉␉␉{␊ |
241 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊ |
242 | ␉␉␉␉␉␉}␊ |
243 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
244 | ␉␉␉␉␉␉{␊ |
245 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
246 | ␉␉␉␉␉␉}␊ |
247 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
248 | ␉␉␉␉␉␉{␊ |
249 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
250 | ␉␉␉␉␉␉}␊ |
251 | ␉␉␉␉␉␉return true;␊ |
252 | ␊ |
253 | ␊ |
254 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
255 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
256 | ␉␉␉␉␉␉return true;␊ |
257 | ␉␉␉␉␉default:␊ |
258 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
259 | ␉␉␉␉}␊ |
260 | ␉␉␉}␊ |
261 | ␉␉␉default:␊ |
262 | ␉␉␉␉break; ␊ |
263 | ␉␉}␊ |
264 | ␉}␊ |
265 | ␉␊ |
266 | ␉return false;␊ |
267 | }␊ |
268 | ␊ |
269 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
270 | {␊ |
271 | ␉static int idx = -1;␊ |
272 | ␉int␉map;␊ |
273 | ␊ |
274 | ␉idx++;␊ |
275 | ␉if (idx < MAX_RAM_SLOTS)␊ |
276 | ␉{␊ |
277 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
278 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
279 | ␉␉{␊ |
280 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
281 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
282 | ␉␉␉return true;␊ |
283 | ␉␉}␊ |
284 | ␉}␊ |
285 | ␉␊ |
286 | ␉return false;␊ |
287 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
288 | //␉return true;␊ |
289 | }␊ |
290 | ␊ |
291 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
292 | {␊ |
293 | ␉value->word = 0xFFFF;␊ |
294 | ␉return true;␊ |
295 | }␊ |
296 | ␊ |
297 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
298 | {␊ |
299 | ␉static int idx = -1;␊ |
300 | ␉int␉map;␊ |
301 | ␊ |
302 | ␉idx++;␊ |
303 | ␉if (idx < MAX_RAM_SLOTS)␊ |
304 | ␉{␊ |
305 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
306 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
307 | ␉␉{␊ |
308 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
309 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
310 | ␉␉␉return true;␊ |
311 | ␉␉}␊ |
312 | ␉}␊ |
313 | ␊ |
314 | ␉return false;␊ |
315 | //␉value->dword = 800;␊ |
316 | //␉return true;␊ |
317 | }␊ |
318 | ␊ |
319 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
320 | {␊ |
321 | ␉static int idx = -1;␊ |
322 | ␉int␉map;␊ |
323 | ␊ |
324 | ␉idx++;␊ |
325 | ␉if (idx < MAX_RAM_SLOTS)␊ |
326 | ␉{␊ |
327 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
328 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
329 | ␉␉{␊ |
330 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
331 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
332 | ␉␉␉return true;␊ |
333 | ␉␉}␊ |
334 | ␉}␊ |
335 | ␊ |
336 | ␉if (!bootInfo->memDetect)␊ |
337 | ␉{␊ |
338 | ␉␉return false;␊ |
339 | ␉}␊ |
340 | ␉value->string = NOT_AVAILABLE;␊ |
341 | ␉return true;␊ |
342 | }␊ |
343 | ␊ |
344 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
345 | {␊ |
346 | ␉static int idx = -1;␊ |
347 | ␉int␉map;␊ |
348 | ␊ |
349 | ␉idx++;␊ |
350 | ␊ |
351 | ␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
352 | ␊ |
353 | ␉if (idx < MAX_RAM_SLOTS)␊ |
354 | ␉{␊ |
355 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
356 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
357 | ␉␉{␊ |
358 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
359 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
360 | ␉␉␉return true;␊ |
361 | ␉␉}␊ |
362 | ␉}␊ |
363 | ␊ |
364 | ␉if (!bootInfo->memDetect)␊ |
365 | ␉{␊ |
366 | ␉␉return false;␊ |
367 | ␉}␊ |
368 | ␉value->string = NOT_AVAILABLE;␊ |
369 | ␉return true;␊ |
370 | }␊ |
371 | ␊ |
372 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
373 | {␊ |
374 | ␉static int idx = -1;␊ |
375 | ␉int␉map;␊ |
376 | ␊ |
377 | ␉idx++;␊ |
378 | ␉if (idx < MAX_RAM_SLOTS)␊ |
379 | ␉{␊ |
380 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
381 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
382 | ␉␉{␊ |
383 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
384 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
385 | ␉␉␉return true;␊ |
386 | ␉␉}␊ |
387 | ␉}␊ |
388 | ␊ |
389 | ␉if (!bootInfo->memDetect)␊ |
390 | ␉{␊ |
391 | ␉␉return false;␊ |
392 | ␉}␊ |
393 | ␉value->string = NOT_AVAILABLE;␊ |
394 | ␉return true;␊ |
395 | }␊ |
396 | ␊ |
397 | ␊ |
398 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
399 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
400 | static const char * const SMTAG = "_SM_";␊ |
401 | static const char* const DMITAG = "_DMI_";␊ |
402 | ␊ |
403 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
404 | {␊ |
405 | ␉SMBEntryPoint␉*smbios;␊ |
406 | ␉/* ␊ |
407 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
408 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
409 | ␉ */␊ |
410 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
411 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
412 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
413 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
414 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
415 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
416 | ␉ {␊ |
417 | ␉␉␉return smbios;␊ |
418 | ␉ }␊ |
419 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
420 | ␉}␊ |
421 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
422 | ␉pause();␊ |
423 | ␉return NULL;␊ |
424 | }␊ |
425 | ␊ |
426 | |