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Root/branches/Bungo/i386/libsaio/dram_controllers.c

1/*␊
2 * dram controller access and scan from the pci host controller␊
3 * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work␊
4 * original source comes from:␊
5 *␊
6 * memtest86␊
7 *␊
8 * Released under version 2 of the Gnu Public License.␊
9 * By Chris Brady, cbrady@sgi.com␊
10 * ----------------------------------------------------␊
11 * MemTest86+ V4.00 Specific code (GPL V2.0)␊
12 * By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊
13 * http://www.canardpc.com - http://www.memtest.org␊
14 */␊
15␊
16#include "libsaio.h"␊
17#include "bootstruct.h"␊
18#include "pci.h"␊
19#include "platform.h"␊
20#include "dram_controllers.h"␊
21␊
22#ifndef DEBUG_DRAM␊
23#define DEBUG_DRAM 0␊
24#endif␊
25␊
26#if DEBUG_DRAM␊
27#define DBG(x...) printf(x)␊
28#else␊
29#define DBG(x...)␊
30#endif␊
31␊
32/*␊
33 * Initialise memory controller functions␊
34 */␊
35␊
36// Setup P35 Memory Controller␊
37static void setup_p35(pci_dt_t *dram_dev)␊
38{␊
39␉uint32_t dev0;␊
40␉␊
41␉// Activate MMR I/O␊
42␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
43␉if (!(dev0 & 0x1))␊
44␉{␊
45␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊
46␉}␊
47}␊
48␊
49int nhm_bus = 0x3F;␊
50␊
51// Setup Nehalem Integrated Memory Controller␊
52static void setup_nhm(pci_dt_t *dram_dev)␊
53{␊
54␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
55␉unsigned long did, vid;␊
56␉int i;␊
57␊
58␉// Nehalem supports Scrubbing␊
59␉// First, locate the PCI bus where the MCH is located␊
60␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
61␉{␊
62␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊
63␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊
64␉␉vid &= 0xFFFF;␊
65␉␉did &= 0xFF00;␊
66␉␉␊
67␉␉if(vid == 0x8086 && did >= 0x2C00)␊
68␉␉{␊
69␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
70␉␉}␊
71␉}␊
72}␊
73␊
74/*␊
75 * Retrieve memory controller fsb functions␊
76 */␊
77␊
78␊
79// Get i965 Memory Speed␊
80static void get_fsb_i965(pci_dt_t *dram_dev)␊
81{␊
82␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
83␊
84␉long *ptr;␊
85␉␊
86␉// Find Ratio␊
87␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
88␉dev0 &= 0xFFFFC000;␊
89␉ptr = (long*)(dev0 + 0xC00);␊
90␉mch_cfg = *ptr & 0xFFFF;␊
91␉␊
92␉mch_ratio = 100000;␊
93␉␊
94␉switch (mch_cfg & 7)␊
95␉{␊
96␉␉case 0: mch_fsb = 1066; break;␊
97␉␉case 1: mch_fsb = 533; break;␊
98␉␉default: ␊
99␉␉case 2: mch_fsb = 800; break;␊
100␉␉case 3: mch_fsb = 667; break;␉␉␊
101␉␉case 4: mch_fsb = 1333; break;␊
102␉␉case 6: mch_fsb = 1600; break;␉␉␉␉␉␊
103␉}␊
104␉␊
105␉DBG("mch_fsb %d\n", mch_fsb);␊
106␉␊
107␉switch (mch_fsb)␊
108␉{␊
109␉␉case 533:␊
110␉␉switch ((mch_cfg >> 4) & 7)␊
111␉␉{␊
112␉␉␉case 1:␉mch_ratio = 200000; break;␊
113␉␉␉case 2:␉mch_ratio = 250000; break;␊
114␉␉␉case 3:␉mch_ratio = 300000; break;␊
115␉␉}␊
116␉␉break;␊
117␉␉␉␊
118␉␉default:␊
119␉␉case 800:␊
120␉␉switch ((mch_cfg >> 4) & 7)␊
121␉␉{␊
122␉␉␉case 0:␉mch_ratio = 100000; break;␊
123␉␉␉case 1:␉mch_ratio = 125000; break;␊
124␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊
125␉␉␉case 3:␉mch_ratio = 200000; break;␊
126␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊
127␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊
128␉␉}␊
129␉␉break;␊
130␉␉␉␊
131␉␉case 1066:␊
132␉␉switch ((mch_cfg >> 4) & 7)␊
133␉␉{␊
134␉␉␉case 1:␉mch_ratio = 100000; break;␊
135␉␉␉case 2:␉mch_ratio = 125000; break;␊
136␉␉␉case 3:␉mch_ratio = 150000; break;␊
137␉␉␉case 4:␉mch_ratio = 200000; break;␊
138␉␉␉case 5:␉mch_ratio = 250000; break;␊
139␉␉}␊
140␉␉break;␊
141␉␉␉␊
142␉␉case 1333:␊
143␉␉switch ((mch_cfg >> 4) & 7)␊
144␉␉{␊
145␉␉␉case 2:␉mch_ratio = 100000; break;␊
146␉␉␉case 3:␉mch_ratio = 120000; break;␊
147␉␉␉case 4:␉mch_ratio = 160000; break;␊
148␉␉␉case 5:␉mch_ratio = 200000; break;␊
149␉␉}␊
150␉␉break;␊
151␉␉␉␊
152␉␉case 1600:␊
153␉␉switch ((mch_cfg >> 4) & 7)␊
154␉␉{␊
155␉␉␉case 3:␉mch_ratio = 100000; break;␊
156␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊
157␉␉␉case 5:␉mch_ratio = 150000; break;␊
158␉␉␉case 6:␉mch_ratio = 200000; break;␊
159␉␉}␊
160␉␉break;␊
161␉}␊
162␉␊
163␉DBG("mch_ratio %d\n", mch_ratio);␊
164␊
165␉// Compute RAM Frequency␊
166␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
167␉␊
168␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊
169␊
170}␊
171␊
172// Get i965m Memory Speed␊
173static void get_fsb_im965(pci_dt_t *dram_dev)␊
174{␊
175␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊
176␊
177␉long *ptr;␊
178␉␊
179␉// Find Ratio␊
180␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
181␉dev0 &= 0xFFFFC000;␊
182␉ptr = (long*)(dev0 + 0xC00);␊
183␉mch_cfg = *ptr & 0xFFFF;␊
184␉␊
185␉mch_ratio = 100000;␊
186␉␊
187␉switch (mch_cfg & 7)␊
188␉{␊
189␉␉case 1: mch_fsb = 533; break;␊
190␉␉default: ␊
191␉␉case 2:␉mch_fsb = 800; break;␊
192␉␉case 3:␉mch_fsb = 667; break;␉␉␉␉␊
193␉␉case 6:␉mch_fsb = 1066; break;␉␉␉␊
194␉}␊
195␉␊
196␉switch (mch_fsb)␊
197␉{␊
198␉␉case 533:␊
199␉␉␉switch ((mch_cfg >> 4) & 7)␊
200␉␉␉{␊
201␉␉␉␉case 1:␉mch_ratio = 125000; break;␊
202␉␉␉␉case 2:␉mch_ratio = 150000; break;␊
203␉␉␉␉case 3:␉mch_ratio = 200000; break;␊
204␉␉␉}␊
205␉␉␉break;␊
206␉␉␉␊
207␉␉case 667:␊
208␉␉␉switch ((mch_cfg >> 4)& 7)␊
209␉␉␉{␊
210␉␉␉␉case 1:␉mch_ratio = 100000; break;␊
211␉␉␉␉case 2:␉mch_ratio = 120000; break;␊
212␉␉␉␉case 3:␉mch_ratio = 160000; break;␊
213␉␉␉␉case 4:␉mch_ratio = 200000; break;␊
214␉␉␉␉case 5:␉mch_ratio = 240000; break;␊
215␉␉␉}␊
216␉␉␉break;␊
217␉␉␉␊
218␉␉default:␊
219␉␉case 800:␊
220␉␉␉switch ((mch_cfg >> 4) & 7)␊
221␉␉␉{␊
222␉␉␉␉case 1:␉mch_ratio = 83333; break; // 0.833333333␊
223␉␉␉␉case 2:␉mch_ratio = 100000; break;␊
224␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊
225␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊
226␉␉␉␉case 5:␉mch_ratio = 200000; break;␊
227␉␉␉}␊
228␉␉␉break;␊
229␉␉case 1066:␊
230␉␉␉switch ((mch_cfg >> 4)&7)␊
231␉␉␉{␊
232␉␉␉␉case 5:␉mch_ratio = 150000; break;␊
233␉␉␉␉case 6:␉mch_ratio = 200000; break;␊
234␉␉␉}␊
235␉␉␉␊
236␉}␊
237␉␊
238␉// Compute RAM Frequency␊
239␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊
240}␊
241␊
242␊
243// Get iCore7 Memory Speed␊
244static void get_fsb_nhm(pci_dt_t *dram_dev)␊
245{␊
246␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊
247␉␊
248␉// Get the clock ratio␊
249␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊
250␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊
251␉␊
252␉// Compute RAM Frequency␊
253␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊
254}␊
255/*␊
256// Get iCore 32nn Memory Speed␊
257static void get_fsb_nhm32(pci_dt_t *dram_dev)␊
258{␊
259␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊
260␉␊
261␉// Get the clock ratio␊
262␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊
263␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊
264␉␊
265␉// Compute RAM Frequency␊
266␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊
267}*/␊
268␊
269/*␊
270 * Retrieve memory controller info functions␊
271 */␊
272␊
273// Get i965 Memory Timings␊
274static void get_timings_i965(pci_dt_t *dram_dev)␊
275{ ␊
276␉// Thanks for CDH optis␊
277␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊
278␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
279␊
280␉long *ptr;␊
281␉␊
282␉// Read MMR Base Address␊
283␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
284␉dev0 &= 0xFFFFC000;␊
285␉␊
286␉ptr = (long*)(dev0 + 0x260);␊
287␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
288␉␊
289␉ptr = (long*)(dev0 + 0x660);␊
290␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
291␉␊
292␉// If DIMM 0 not populated, check DIMM 1␊
293␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
294␉␊
295␉ptr = (long*)(dev0 + offset + 0x29C);␊
296␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
297␉␊
298␉ptr = (long*)(dev0 + offset + 0x250);␉␊
299␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
300␉␊
301␉ptr = (long*)(dev0 + offset + 0x252);␊
302␉ACT_Register = *ptr & 0xFFFFFFFF;␊
303␉␊
304␉ptr = (long*)(dev0 + offset + 0x258);␊
305␉Read_Register = *ptr & 0xFFFFFFFF;␊
306␉␊
307␉ptr = (long*)(dev0 + offset + 0x244);␊
308␉Misc_Register = *ptr & 0xFFFFFFFF;␊
309␉␊
310␉// 965 Series only support DDR2␊
311␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
312␉␊
313␉// CAS Latency (tCAS)␊
314␉Platform.RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3;␊
315␉␊
316␉// RAS-To-CAS (tRCD)␊
317␉Platform.RAM.TRC = (Read_Register >> 16) & 0xF;␊
318␉␊
319␉// RAS Precharge (tRP)␊
320␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
321␉␊
322␉// RAS Active to precharge (tRAS)␊
323␉Platform.RAM.RAS = (Precharge_Register >> 11) & 0x1F;␊
324␉␊
325␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊
326␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
327␉} else {␊
328␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
329␉}␊
330}␊
331␊
332// Get im965 Memory Timings␊
333static void get_timings_im965(pci_dt_t *dram_dev)␊
334{␊
335␉// Thanks for CDH optis␊
336␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊
337␉long *ptr;␊
338␉␊
339␉// Read MMR Base Address␊
340␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
341␉dev0 &= 0xFFFFC000;␊
342␉␊
343␉ptr = (long*)(dev0 + 0x1200);␊
344␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
345␉␊
346␉ptr = (long*)(dev0 + 0x1300);␊
347␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
348␉␊
349␉// If DIMM 0 not populated, check DIMM 1␊
350␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊
351␉␊
352␉ptr = (long*)(dev0 + offset + 0x121C);␊
353␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
354␉␊
355␉ptr = (long*)(dev0 + offset + 0x1214);␉␊
356␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
357␉␊
358␉// Series only support DDR2␊
359␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
360␉␊
361␉// CAS Latency (tCAS)␊
362␉Platform.RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3;␊
363␉␊
364␉// RAS-To-CAS (tRCD)␊
365␉Platform.RAM.TRC = ((Precharge_Register >> 5) & 7) + 2;␊
366␉␊
367␉// RAS Precharge (tRP)␊
368␉Platform.RAM.TRP= (Precharge_Register & 7) + 2;␊
369␉␊
370␉// RAS Active to precharge (tRAS)␊
371␉Platform.RAM.RAS = (Precharge_Register >> 21) & 0x1F;␊
372␉␊
373␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊
374␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
375␉} else {␊
376␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
377␉}␊
378}␊
379␊
380// Get P35 Memory Timings␊
381static void get_timings_p35(pci_dt_t *dram_dev)␊
382{ ␊
383␉// Thanks for CDH optis␊
384␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊
385␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊
386␉long *ptr;␊
387␉␊
388␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊
389␉//Device_ID &= 0xFFFF;␊
390␉␊
391␉// Now, read MMR Base Address␊
392␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
393␉dev0 &= 0xFFFFC000;␊
394␉␊
395␉ptr = (long*)(dev0 + 0x260);␊
396␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊
397␉␊
398␉ptr = (long*)(dev0 + 0x660);␊
399␉c1ckectrl = *ptr & 0xFFFFFFFF;␊
400␉␊
401␉// If DIMM 0 not populated, check DIMM 1␊
402␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊
403␉␊
404␉ptr = (long*)(dev0 + offset + 0x265);␊
405␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊
406␉␊
407␉ptr = (long*)(dev0 + offset + 0x25D);␉␊
408␉Precharge_Register = *ptr & 0xFFFFFFFF;␊
409␉␊
410␉ptr = (long*)(dev0 + offset + 0x252);␊
411␉ACT_Register = *ptr & 0xFFFFFFFF;␊
412␉␊
413␉ptr = (long*)(dev0 + offset + 0x258);␊
414␉Read_Register = *ptr & 0xFFFFFFFF;␊
415␉␊
416␉ptr = (long*)(dev0 + offset + 0x244);␊
417␉Misc_Register = *ptr & 0xFFFFFFFF;␊
418␉␊
419␉ptr = (long*)(dev0 + offset + 0x1E8);␊
420␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
421␉␊
422␉// On P45, check 1A8␊
423␉if(dram_dev->device_id > 0x2E00) {␊
424␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊
425␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␊
426␉␉Memory_Check >>= 2;␊
427␉␉Memory_Check &= 1;␊
428␉␉Memory_Check = !Memory_Check;␊
429␉} else {␊
430␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊
431␉␉Memory_Check = *ptr & 0xFFFFFFFF;␉␉␊
432␉}␊
433␉␊
434␉// Determine DDR-II or DDR-III␊
435␉if (Memory_Check & 1) {␊
436␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
437␉} else {␊
438␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
439␉}␊
440␊
441␉// CAS Latency (tCAS)␊
442␉if(dram_dev->device_id > 0x2E00) {␊
443␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊
444␉} else {␊
445␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊
446␉}␊
447␊
448␉// RAS-To-CAS (tRCD)␊
449␉Platform.RAM.TRC = (Read_Register >> 17) & 0xF;␊
450␉␊
451␉// RAS Precharge (tRP)␊
452␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊
453␉␊
454␉// RAS Active to precharge (tRAS)␊
455␉Platform.RAM.RAS = Precharge_Register & 0x3F;␊
456␉␊
457␉// Channel configuration␊
458␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) {␊
459␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
460␉} else {␊
461␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
462␉}␊
463}␊
464␊
465// Get Nehalem Memory Timings␊
466static void get_timings_nhm(pci_dt_t *dram_dev)␊
467{␊
468␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊
469␉int fvc_bn = 4;␊
470␉␊
471␉// Find which channels are populated␊
472␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊
473␉mc_control = (mc_control >> 8) & 0x7;␊
474␉␊
475␉// DDR-III␊
476␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
477␉␊
478␉// Get the first valid channel␊
479␉if(mc_control & 1) {␊
480␉␉fvc_bn = 4; ␊
481␉} else if(mc_control & 2) {␊
482␉␉fvc_bn = 5; ␊
483␉} else if(mc_control & 7) {␊
484␉␉fvc_bn = 6; ␊
485␉}␊
486␊
487␉// Now, detect timings␊
488␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊
489␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊
490␉␊
491␉// CAS Latency (tCAS)␊
492␉Platform.RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4;␊
493␉␊
494␉// RAS-To-CAS (tRCD)␊
495␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
496␉␊
497␉// RAS Active to precharge (tRAS)␊
498␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
499␉␊
500␉// RAS Precharge (tRP)␊
501␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
502␉␊
503␉// Single , Dual or Triple Channels␊
504␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) {␊
505␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊
506␉} else if (mc_control == 7) {␊
507␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_TRIPLE;␊
508␉} else ␉{␊
509␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊
510␉}␊
511}␊
512␊
513static struct mem_controller_t dram_controllers[] = {␊
514␊
515␉// Default unknown chipset␊
516␉{ 0, 0, "",␉NULL, NULL, NULL },␊
517␊
518␉// Intel␊
519//␉{ 0x8086, 0x0100, "2rd Gen Core processor",␉NULL, NULL, NULL },␊
520//␉{ 0x8086, 0x0104, "2rd Gen Core processor",␉NULL, NULL, NULL },␊
521//␉{ 0x8086, 0x010C, "Xeon E3-1200/2rd Gen Core processor",␉NULL, NULL, NULL },␊
522//␉{ 0x8086, 0x0150, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊
523//␉{ 0x8086, 0x0154, "3rd Gen Core processor",␉NULL, NULL, NULL },␊
524//␉{ 0x8086, 0x0158, "Xeon E3-1200 v2/Ivy Bridge",␉NULL, NULL, NULL },␊
525//␉{ 0x8086, 0x015C, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊
526␊
527//␉{ 0x8086, 0x0BF0, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
528//␉{ 0x8086, 0x0BF1, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
529//␉{ 0x8086, 0x0BF2, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
530//␉{ 0x8086, 0x0BF3, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
531//␉{ 0x8086, 0x0BF4, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
532//␉{ 0x8086, 0x0BF5, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
533//␉{ 0x8086, 0x0BF6, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
534//␉{ 0x8086, 0x0BF7, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊
535␊
536//␉{ 0x8086, 0x0C00, "Haswell",␉NULL, NULL, NULL },␊
537//␉{ 0x8086, 0x0C04, "Haswell",␉NULL, NULL, NULL },␊
538//␉{ 0x8086, 0x0C08, "Haswell",␉NULL, NULL, NULL },␊
539␊
540␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊
541␊
542␉{ 0x8086, 0x1A30, "82845 845 [Brookdale]",␉NULL, NULL, NULL },␊
543␉␊
544␉{ 0x8086, 0x2970, "82946GZ/PL/GL",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
545␉{ 0x8086, 0x2990, "82Q963/Q965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
546␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊
547␊
548␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
549␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
550␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊
551␊
552␉{ 0x8086, 0x29B0, "82Q35 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
553␉{ 0x8086, 0x29C0, "82G33/G31/P35/P31",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
554␉{ 0x8086, 0x29D0, "82Q33 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
555␉{ 0x8086, 0x29E0, "82X38/X48 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
556//␉{ 0x8086, 0x29F0, "3200/3210 Chipset",␉NULL, NULL, NULL },␊
557␊
558␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
559␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
560␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
561␉{ 0x8086, 0x2E30, "G41",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊
562//␉{ 0x8086, 0x2E40, "4 Series Chipset",␉␉NULL, NULL, NULL },␊
563//␉{ 0x8086, 0x2E90, "4 Series Chipset",␉␉NULL, NULL, NULL },␊
564␊
565␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
566␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
567␉{ 0x8086, 0x3400, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
568␉{ 0x8086, 0x3401, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
569␉{ 0x8086, 0x3402, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
570␉{ 0x8086, 0x3403, "5500",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
571␉{ 0x8086, 0x3404, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
572␉{ 0x8086, 0x3405, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
573␉{ 0x8086, 0x3406, "5520",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
574␉{ 0x8086, 0x3407, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊
575};␊
576␊
577static const char *memory_channel_types[] =␊
578{␊
579␉"Unknown", "Single", "Dual", "Triple"␊
580};␉␉␉␊
581␊
582void scan_dram_controller(pci_dt_t *dram_dev)␊
583{␊
584␉int i;␊
585␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++)␊
586␉{␊
587␉␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) && (dram_controllers[i].device == dram_dev->device_id))␊
588␉␉{␊
589␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊
590␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel Corporation " : "" ,␊
591␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊
592␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊
593␉␉␉␊
594␉␉␉if (dram_controllers[i].initialise != NULL)␊
595␉␉␉{␊
596␉␉␉␉dram_controllers[i].initialise(dram_dev);␊
597␉␉␉}␊
598␊
599␉␉␉if (dram_controllers[i].poll_timings != NULL)␊
600␉␉␉{␊
601␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊
602␉␉␉}␊
603␊
604␉␉␉if (dram_controllers[i].poll_speed != NULL)␊
605␉␉␉{␊
606␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊
607␉␉␉}␊
608␊
609␉␉␉verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", ␊
610␉␉␉␉(uint32_t)Platform.RAM.Frequency / 1000000,␊
611␉␉␉␉(uint32_t)Platform.RAM.Frequency / 500000,␊
612␉␉␉␉memory_channel_types[Platform.RAM.Channels]␊
613␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
614␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS);␊
615//␉␉␉getchar();␉␉␊
616␉␉}␊
617␉}␊
618}␊
619

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