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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9#include "bootstruct.h"␊
10␊
11#ifndef DEBUG_SMBIOS␊
12#define DEBUG_SMBIOS 0␊
13#endif␊
14␊
15#if DEBUG_SMBIOS␊
16#define DBG(x...)␉printf(x)␊
17#else␊
18#define DBG(x...)␊
19#endif␊
20␊
21␊
22bool getProcessorInformationExternalClock(returnType *value)␊
23{␊
24␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
25␉{␊
26␉␉switch (Platform.CPU.Family)␊
27␉␉{␊
28␉␉␉case 0x06:␊
29␉␉␉{␊
30␉␉␉␉switch (Platform.CPU.Model)␊
31␉␉␉␉{␊
32␉␉␉␉␉␉// set external clock to 0 for SANDY␊
33␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
34␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
35␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
36␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
37␉␉␉␉␉case CPU_MODEL_HASWELL:␊
38␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
39␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
40␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
41␊
42␉␉␉␉␉␉value->word = 0;␊
43␉␉␉␉␉␉break;␊
44␉␉␉␉␉default:␊
45␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
46␉␉␉␉}␊
47␉␉␉}␊
48␉␉␉␉break;␊
49␊
50␉␉␉default:␊
51␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
52␉␉}␊
53␉}␊
54␉else␊
55␉{␊
56␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000);␊
57␉}␊
58␊
59␉return true;␊
60}␊
61␊
62bool getProcessorInformationMaximumClock(returnType *value)␊
63{␊
64␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000);␊
65␉return true;␊
66}␊
67␊
68bool getSMBOemProcessorBusSpeed(returnType *value)␊
69{␊
70␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
71␉{␊
72␉␉switch (Platform.CPU.Family)␊
73␉␉{␊
74␉␉␉case 0x06:␊
75␉␉␉{␊
76␉␉␉␉switch (Platform.CPU.Model)␊
77␉␉␉␉{␊
78␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊
79␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊
80␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊
81␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
82␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
83␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊
84␉␉␉␉␉␉return false;␊
85␊
86␉␉␉␉␉case 0x19:␊
87␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
88␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
89␉␉␉␉␉case CPU_MODEL_DALES:␊
90␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
91␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
92␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
93␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
94␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
95␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
96␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
97␉␉␉␉␉case CPU_MODEL_HASWELL:␊
98␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
99␉␉␉␉␉{␊
100␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
101␉␉␉␉␉␉int nhm_bus = 0x3F;␊
102␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
103␉␉␉␉␉␉unsigned long did, vid;␊
104␉␉␉␉␉␉unsigned int i;␊
105␉␉␉␉␉␉␊
106␉␉␉␉␉␉// Nehalem supports Scrubbing␊
107␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
108␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊
109␉␉␉␉␉␉{␊
110␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
111␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
112␉␉␉␉␉␉␉vid &= 0xFFFF;␊
113␉␉␉␉␉␉␉did &= 0xFF00;␊
114␉␉␉␉␉␉␉␊
115␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
116␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊
117␉␉␉␉␉␉}␊
118␊
119␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
120␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
121␉␉␉␉␉␉qpimult &= 0x7F;␊
122␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
123␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
124␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
125␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊
126␉␉␉␉␉␉{␊
127␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊
128␉␉␉␉␉␉}␊
129␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
130␉␉␉␉␉␉value->word = qpibusspeed;␊
131␉␉␉␉␉␉return true;␊
132␉␉␉␉␉}␊
133␉␉␉␉␉default:␊
134␉␉␉␉␉␉break; //Unsupported CPU type␊
135␉␉␉␉}␊
136␉␉␉}␊
137␉␉␉default:␊
138␉␉␉␉break;␊
139␉␉}␊
140␉}␊
141␉return false;␊
142}␊
143␊
144uint16_t simpleGetSMBOemProcessorType(void)␊
145{␊
146␉if (Platform.CPU.NoCores >= 4)␊
147␉{␊
148␉␉return 0x0501;␉// Quad-Core Xeon␊
149␉}␊
150␉else if (Platform.CPU.NoCores == 1)␊
151␉{␊
152␉␉return 0x0201;␉// Core Solo␊
153␉};␊
154␉␊
155␉return 0x0301;␉␉// Core 2 Duo␊
156}␊
157␊
158bool getSMBOemProcessorType(returnType *value)␊
159{␊
160␉static bool done = false;␊
161␊
162␉value->word = simpleGetSMBOemProcessorType();␊
163␊
164␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊
165␉{␊
166␉␉if (!done)␊
167␉␉{␊
168␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊
169␉␉␉done = true;␊
170␉␉}␊
171␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊
172␉␉switch (Platform.CPU.Family)␊
173␉␉{␊
174␉␉␉case 0x06:␊
175␉␉␉{␊
176␉␉␉␉switch (Platform.CPU.Model)␊
177␉␉␉␉{␊
178␊
179␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊
180␉␉␉␉␉␉value->word = 0x101;␊
181␉␉␉␉␉␉return true;␊
182␊
183␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊
184␉␉␉␉␉case CPU_MODEL_CELERON:␊
185␉␉␉␉␉␉value->word = 0x201;␊
186␉␉␉␉␉␉return true;␊
187␊
188␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊
189␉␉␉␉␉␉value->word = 0x401;␊
190␉␉␉␉␉␉return true;␊
191␊
192␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
193␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
194␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
195␉␉␉␉␉␉{␊
196␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// Xeon␊
197␉␉␉␉␉␉}␊
198␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊
199␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊
200␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊
201␉␉␉␉␉␉return true;␊
202␊
203␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊
204␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
205␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
206␉␉␉␉␉␉{␊
207␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Xeon␊
208␉␉␉␉␉␉}␊
209␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
210␉␉␉␉␉␉{␊
211␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
212␉␉␉␉␉␉}␊
213␉␉␉␉␉␉return true;␊
214␊
215␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
216␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
217␉␉␉␉␉␉{␊
218␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// Lynnfiled Quad-Core Xeon␊
219␉␉␉␉␉␉}␊
220␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
221␉␉␉␉␉␉{␊
222␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊
223␉␉␉␉␉␉}␊
224␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
225␉␉␉␉␉␉{␊
226␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
227␉␉␉␉␉␉}␊
228␉␉␉␉␉␉return true;␊
229␊
230␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
231␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
232␉␉␉␉␉␉{␊
233␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
234␉␉␉␉␉␉}␊
235␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
236␉␉␉␉␉␉{␊
237␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
238␉␉␉␉␉␉}␊
239␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
240␉␉␉␉␉␉{␊
241␉␉␉␉␉␉␉value->word = 0x702;␉␉␉// Core i7␊
242␉␉␉␉␉␉}␊
243␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
244␉␉␉␉␉␉{␊
245␉␉␉␉␉␉␉value->word = 0x602;␉␉␉// Core i5␊
246␉␉␉␉␉␉}␊
247␉␉␉␉␉␉return true;␊
248␊
249␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊
250␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
251␉␉␉␉␉␉{␊
252␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
253␉␉␉␉␉␉}␊
254␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
255␉␉␉␉␉␉{␊
256␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
257␉␉␉␉␉␉}␊
258␉␉␉␉␉␉if(strstr(Platform.CPU.BrandString, "Core(TM) i5 CPU M 540"))␊
259␉␉␉␉␉␉{␊
260␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
261␉␉␉␉␉␉}␊
262␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
263␉␉␉␉␉␉{␊
264␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
265␉␉␉␉␉␉}␊
266␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
267␉␉␉␉␉␉{␊
268␉␉␉␉␉␉␉value->word = 0x602;␉␉// Core i5␊
269␉␉␉␉␉␉}␊
270␉␉␉␉␉␉return true;␊
271␊
272␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
273␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊
274␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
275␉␉␉␉␉␉{␊
276␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
277␉␉␉␉␉␉}␊
278␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
279␉␉␉␉␉␉{␊
280␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
281␉␉␉␉␉␉}␊
282␉␉␉␉␉␉return true;␊
283␊
284␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
285␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊
286␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
287␉␉␉␉␉␉{␊
288␉␉␉␉␉␉␉value->word = 0x501;␉␉// Xeon␊
289␉␉␉␉␉␉}␊
290␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
291␉␉␉␉␉␉{␊
292␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3␊
293␉␉␉␉␉␉}␊
294␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
295␉␉␉␉␉␉{␊
296␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
297␉␉␉␉␉␉}␊
298␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
299␉␉␉␉␉␉{␊
300␉␉␉␉␉␉␉value->word = 0x703;␉␉// Core i7␊
301␉␉␉␉␉␉}␊
302␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
303␉␉␉␉␉␉{␊
304␉␉␉␉␉␉␉value->word = 0x603;␉␉// Core i5␊
305␉␉␉␉␉␉}␊
306␉␉␉␉␉␉return true;␊
307␊
308␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊
309␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
310␉␉␉␉␉␉{␊
311␉␉␉␉␉␉␉value->word = 0x903;␉␉// Core i3 - Apple doesn't use it␊
312␉␉␉␉␉␉}␊
313␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
314␉␉␉␉␉␉{␊
315␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
316␉␉␉␉␉␉}␊
317␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
318␉␉␉␉␉␉{␊
319␉␉␉␉␉␉␉value->word = 0x704;␉␉// Core i7␊
320␉␉␉␉␉␉}␊
321␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
322␉␉␉␉␉␉{␊
323␉␉␉␉␉␉␉value->word = 0x604;␉␉// Core i5␊
324␉␉␉␉␉␉}␊
325␉␉␉␉␉␉return true;␊
326␊
327␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E -␊
328␉␉␉␉␉␉value->word = 0xA01;␊
329␉␉␉␉␉␉return true;␊
330␊
331␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
332␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉␉␉// 0x3F -␊
333␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
334␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
335␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
336␉␉␉␉␉␉{␊
337␉␉␉␉␉␉␉value->word = 0x905;␉␉// Core i3 - Apple doesn't use it␊
338␉␉␉␉␉␉}␊
339␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
340␉␉␉␉␉␉{␊
341␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
342␉␉␉␉␉␉}␊
343␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊
344␉␉␉␉␉␉{␊
345␉␉␉␉␉␉␉value->word = 0x705;␉␉// Core i7␊
346␉␉␉␉␉␉}␊
347␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊
348␉␉␉␉␉␉{␊
349␉␉␉␉␉␉␉value->word = 0x605;␉␉// Core i5␊
350␉␉␉␉␉␉}␊
351␉␉␉␉␉␉return true;␊
352␊
353␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊
354␉␉␉␉␉␉value->word = 0x301;␉␉␉//␊
355␉␉␉␉␉␉return true;␊
356␊
357␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊
358␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
359␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
360␉␉␉␉␉␉return true;␊
361␉␉␉␉␉default:␊
362␉␉␉␉␉␉break; //Unsupported CPU type␊
363␉␉␉␉}␊
364␉␉␉}␊
365␉␉␉default:␊
366␉␉␉␉break;␊
367␉␉}␊
368␉}␊
369␉␊
370␉return false;␊
371}␊
372␊
373bool getSMBMemoryDeviceMemoryType(returnType *value)␊
374{␊
375␉static int idx = -1;␊
376␉int␉map;␊
377␊
378␉idx++;␊
379␉if (idx < MAX_RAM_SLOTS)␊
380␉{␊
381␉␉map = Platform.DMI.DIMM[idx];␊
382␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
383␉␉{␊
384␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
385␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
386␉␉␉return true;␊
387␉␉}␊
388␉}␊
389␉␊
390␉return false;␊
391//␉value->byte = SMB_MEM_TYPE_DDR2;␊
392//␉return true;␊
393}␊
394␊
395bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
396{␊
397␉value->word = 0xFFFF;␊
398␉return true;␊
399}␊
400␊
401bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
402{␊
403␉static int idx = -1;␊
404␉int␉map;␊
405␊
406␉idx++;␊
407␉if (idx < MAX_RAM_SLOTS)␊
408␉{␊
409␉␉map = Platform.DMI.DIMM[idx];␊
410␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
411␉␉{␊
412␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
413␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
414␉␉␉return true;␊
415␉␉}␊
416␉}␊
417␊
418␉return false;␊
419//␉value->dword = 800;␊
420//␉return true;␊
421}␊
422␊
423bool getSMBMemoryDeviceManufacturer(returnType *value)␊
424{␊
425␉static int idx = -1;␊
426␉int␉map;␊
427␊
428␉idx++;␊
429␉if (idx < MAX_RAM_SLOTS)␊
430␉{␊
431␉␉map = Platform.DMI.DIMM[idx];␊
432␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
433␉␉{␊
434␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
435␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
436␉␉␉return true;␊
437␉␉}␊
438␉}␊
439␊
440␉if (!bootInfo->memDetect)␊
441␉{␊
442␉␉return false;␊
443␉}␊
444␉value->string = NOT_AVAILABLE;␊
445␉return true;␊
446}␊
447␊
448bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
449{␊
450␉static int idx = -1;␊
451␉int␉map;␊
452␊
453␉idx++;␊
454␊
455␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊
456␊
457␉if (idx < MAX_RAM_SLOTS)␊
458␉{␊
459␉␉map = Platform.DMI.DIMM[idx];␊
460␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
461␉␉{␊
462␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊
463␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
464␉␉␉return true;␊
465␉␉}␊
466␉}␊
467␊
468␉if (!bootInfo->memDetect)␊
469␉{␊
470␉␉return false;␊
471␉}␊
472␉value->string = NOT_AVAILABLE;␊
473␉return true;␊
474}␊
475␊
476bool getSMBMemoryDevicePartNumber(returnType *value)␊
477{␊
478␉static int idx = -1;␊
479␉int␉map;␊
480␊
481␉idx++;␊
482␉if (idx < MAX_RAM_SLOTS)␊
483␉{␊
484␉␉map = Platform.DMI.DIMM[idx];␊
485␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
486␉␉{␊
487␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊
488␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
489␉␉␉return true;␊
490␉␉}␊
491␉}␊
492␊
493␉if (!bootInfo->memDetect)␊
494␉{␊
495␉␉return false;␊
496␉}␊
497␉value->string = NOT_AVAILABLE;␊
498␉return true;␊
499}␊
500␊
501␊
502// getting smbios addr with fast compare ops, late checksum testing ...␊
503#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
504static const char * const SMTAG = "_SM_";␊
505static const char* const DMITAG = "_DMI_";␊
506␊
507SMBEntryPoint *getAddressOfSmbiosTable(void)␊
508{␊
509␉SMBEntryPoint␉*smbios;␊
510␉/*␊
511␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
512␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
513␉ */␊
514␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
515␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
516␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊
517␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
518␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
519␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
520␉ {␊
521␉␉␉return smbios;␊
522␉ }␊
523␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
524␉}␊
525␉printf("ERROR: Unable to find SMBIOS!\n");␊
526␉pause();␊
527␉return NULL;␊
528}␊
529␊
530

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