1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␉␉␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's. ␊ |
34 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE: ␊ |
35 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
36 | case CPU_MODEL_HASWELL:␊ |
37 | ␉␉␉␉␉␉value->word = 0;␊ |
38 | ␉␉␉␉␉␉break;␊ |
39 | ␉␉␉␉␉default:␊ |
40 | ␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
41 | ␉␉␉␉}␊ |
42 | ␉␉␉}␊ |
43 | ␉␉␉␉break;␊ |
44 | ␉␉␉␉␊ |
45 | ␉␉␉default:␊ |
46 | ␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
47 | ␉␉}␊ |
48 | ␉}␊ |
49 | ␉else␊ |
50 | ␉{␊ |
51 | ␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
52 | ␉}␊ |
53 | ␊ |
54 | ␉return true;␊ |
55 | }␊ |
56 | ␊ |
57 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
58 | {␊ |
59 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
60 | ␉return true;␊ |
61 | }␊ |
62 | ␊ |
63 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
64 | {␊ |
65 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
66 | ␉{␉␉␊ |
67 | ␉␉switch (Platform.CPU.Family) ␊ |
68 | ␉␉{␊ |
69 | ␉␉␉case 0x06:␊ |
70 | ␉␉␉{␊ |
71 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
72 | ␉␉␉␉{␊ |
73 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
74 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
75 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
76 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
77 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
78 | ␉␉␉␉␉␉return false;␊ |
79 | ␊ |
80 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
81 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
82 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
83 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
84 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
85 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
86 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
87 | ␉␉␉␉␉{␊ |
88 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
89 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
90 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
91 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
92 | ␉␉␉␉␉␉int i;␊ |
93 | ␉␉␉␉␉␉␊ |
94 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
95 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
96 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
97 | ␉␉␉␉␉␉{␊ |
98 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
99 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
100 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
101 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
102 | ␉␉␉␉␉␉␉␊ |
103 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
104 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
105 | ␉␉␉␉␉␉}␊ |
106 | ␉␉␉␉␉␉␊ |
107 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
108 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
109 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
110 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
111 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
112 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
113 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
114 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
115 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
116 | ␉␉␉␉␉␉return true;␊ |
117 | ␉␉␉␉␉}␊ |
118 | ␉␉␉␉}␊ |
119 | ␉␉␉}␊ |
120 | ␉␉}␊ |
121 | ␉}␊ |
122 | ␉return false;␊ |
123 | }␊ |
124 | ␊ |
125 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
126 | {␊ |
127 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
128 | ␉{␊ |
129 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
130 | ␉}␊ |
131 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
132 | ␉{␊ |
133 | ␉␉return 0x0201;␉// Core Solo␊ |
134 | ␉};␊ |
135 | ␉␊ |
136 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
137 | }␊ |
138 | ␊ |
139 | bool getSMBOemProcessorType(returnType *value)␊ |
140 | {␊ |
141 | ␉static bool done = false;␉␉␊ |
142 | ␉␉␊ |
143 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
144 | ␊ |
145 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
146 | ␉{␊ |
147 | ␉␉if (!done)␊ |
148 | ␉␉{␊ |
149 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
150 | ␉␉␉done = true;␊ |
151 | ␉␉}␊ |
152 | ␉␉␊ |
153 | ␉␉switch (Platform.CPU.Family) ␊ |
154 | ␉␉{␊ |
155 | ␉␉␉case 0x06:␊ |
156 | ␉␉␉{␊ |
157 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
158 | ␉␉␉␉{␊ |
159 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊ |
160 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
161 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
162 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
163 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
164 | ␉␉␉␉␉␉return true;␊ |
165 | ␊ |
166 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
167 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
168 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
169 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
170 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
171 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊ |
172 | ␉␉␉␉␉␉else␊ |
173 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
174 | ␉␉␉␉␉␉return true;␊ |
175 | ␊ |
176 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
177 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
178 | ␉␉␉␉␉␉␉value->word = 0x0501;// Xeon␊ |
179 | ␉␉␉␉␉␉else␊ |
180 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
181 | ␉␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
182 | ␉␉␉␉␉␉␉else␊ |
183 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
184 | ␉␉␉␉␉␉return true;␊ |
185 | ␊ |
186 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
187 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
188 | ␉␉␉␉␉␉␉value->word = 0x0601;␉␉␉// Core i5␊ |
189 | ␉␉␉␉␉␉else␊ |
190 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
191 | ␉␉␉␉␉␉return true;␊ |
192 | ␊ |
193 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
194 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
195 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
196 | case CPU_MODEL_HASWELL: // Intel Core i3, i5, i7, Xeon E3 LGA1155 (22nm)␊ |
197 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
198 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon␊ |
199 | ␉␉␉␉␉␉else␊ |
200 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
201 | ␉␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊ |
202 | else␊ |
203 | if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
204 | value->word = 0x0601;␉␉// Core i5␊ |
205 | else␊ |
206 | value->word = 0x0701;␉␉// Core i7␊ |
207 | return true;␊ |
208 | }␊ |
209 | ␉␉␉}␊ |
210 | ␉␉}␊ |
211 | ␉}␊ |
212 | ␉␊ |
213 | ␉return false;␊ |
214 | }␊ |
215 | ␊ |
216 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
217 | {␊ |
218 | ␉static int idx = -1;␊ |
219 | ␉int␉map;␊ |
220 | ␊ |
221 | ␉idx++;␊ |
222 | ␉if (idx < MAX_RAM_SLOTS)␊ |
223 | ␉{␊ |
224 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
225 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
226 | ␉␉{␊ |
227 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
228 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
229 | ␉␉␉return true;␊ |
230 | ␉␉}␊ |
231 | ␉}␊ |
232 | ␉␊ |
233 | ␉return false;␊ |
234 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
235 | //␉return true;␊ |
236 | }␊ |
237 | ␊ |
238 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
239 | {␊ |
240 | ␉static int idx = -1;␊ |
241 | ␉int␉map;␊ |
242 | ␊ |
243 | ␉idx++;␊ |
244 | ␉if (idx < MAX_RAM_SLOTS)␊ |
245 | ␉{␊ |
246 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
247 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
248 | ␉␉{␊ |
249 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
250 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
251 | ␉␉␉return true;␊ |
252 | ␉␉}␊ |
253 | ␉}␊ |
254 | ␊ |
255 | ␉return false;␊ |
256 | //␉value->dword = 800;␊ |
257 | //␉return true;␊ |
258 | }␊ |
259 | ␊ |
260 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
261 | {␊ |
262 | ␉static int idx = -1;␊ |
263 | ␉int␉map;␊ |
264 | ␊ |
265 | ␉idx++;␊ |
266 | ␉if (idx < MAX_RAM_SLOTS)␊ |
267 | ␉{␊ |
268 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
269 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
270 | ␉␉{␊ |
271 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
272 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
273 | ␉␉␉return true;␊ |
274 | ␉␉}␊ |
275 | ␉}␊ |
276 | ␊ |
277 | ␉if (!bootInfo->memDetect)␊ |
278 | ␉␉return false;␊ |
279 | ␉value->string = NOT_AVAILABLE;␊ |
280 | ␉return true;␊ |
281 | }␊ |
282 | ␉␊ |
283 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
284 | {␊ |
285 | ␉static int idx = -1;␊ |
286 | ␉int␉map;␊ |
287 | ␊ |
288 | ␉idx++;␊ |
289 | ␊ |
290 | DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
291 | ␊ |
292 | ␉if (idx < MAX_RAM_SLOTS)␊ |
293 | ␉{␊ |
294 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
295 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
296 | ␉␉{␊ |
297 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
298 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
299 | ␉␉␉return true;␊ |
300 | ␉␉}␊ |
301 | ␉}␊ |
302 | ␊ |
303 | ␉if (!bootInfo->memDetect)␊ |
304 | ␉␉return false;␊ |
305 | ␉value->string = NOT_AVAILABLE;␊ |
306 | ␉return true;␊ |
307 | }␊ |
308 | ␊ |
309 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
310 | {␊ |
311 | ␉static int idx = -1;␊ |
312 | ␉int␉map;␊ |
313 | ␊ |
314 | ␉idx++;␊ |
315 | ␉if (idx < MAX_RAM_SLOTS)␊ |
316 | ␉{␊ |
317 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
318 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
319 | ␉␉{␊ |
320 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
321 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
322 | ␉␉␉return true;␊ |
323 | ␉␉}␊ |
324 | ␉}␊ |
325 | ␊ |
326 | ␉if (!bootInfo->memDetect)␊ |
327 | ␉␉return false;␊ |
328 | ␉value->string = NOT_AVAILABLE;␊ |
329 | ␉return true;␊ |
330 | }␊ |
331 | ␊ |
332 | ␊ |
333 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
334 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
335 | static const char * const SMTAG = "_SM_";␊ |
336 | static const char* const DMITAG = "_DMI_";␊ |
337 | ␊ |
338 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
339 | {␊ |
340 | ␉SMBEntryPoint␉*smbios;␊ |
341 | ␉/* ␊ |
342 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
343 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
344 | ␉ */␊ |
345 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
346 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
347 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
348 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
349 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
350 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
351 | ␉ {␊ |
352 | ␉␉␉return smbios;␊ |
353 | ␉ }␊ |
354 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
355 | ␉}␊ |
356 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
357 | ␉pause();␊ |
358 | ␉return NULL;␊ |
359 | }␊ |
360 | ␊ |
361 | |