1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "bootstruct.h"␊ |
9 | #include "pci.h"␊ |
10 | #include "pci_root.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_PCI␊ |
13 | #define DEBUG_PCI 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_PCI␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␊ |
20 | #endif␊ |
21 | ␊ |
22 | pci_dt_t␉*root_pci_dev;␊ |
23 | ␊ |
24 | ␊ |
25 | uint8_t pci_config_read8(uint32_t pci_addr, uint8_t reg)␊ |
26 | {␊ |
27 | ␉pci_addr |= reg & ~3;␊ |
28 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
29 | ␉return inb(PCI_DATA_REG + (reg & 3));␊ |
30 | }␊ |
31 | ␊ |
32 | uint16_t pci_config_read16(uint32_t pci_addr, uint8_t reg)␊ |
33 | {␊ |
34 | ␉pci_addr |= reg & ~3;␊ |
35 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
36 | ␉return inw(PCI_DATA_REG + (reg & 2));␊ |
37 | }␊ |
38 | ␊ |
39 | uint32_t pci_config_read32(uint32_t pci_addr, uint8_t reg)␊ |
40 | {␊ |
41 | ␉pci_addr |= reg & ~3;␊ |
42 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
43 | ␉return inl(PCI_DATA_REG);␊ |
44 | }␊ |
45 | ␊ |
46 | void pci_config_write8(uint32_t pci_addr, uint8_t reg, uint8_t data)␊ |
47 | {␊ |
48 | ␉pci_addr |= reg & ~3;␊ |
49 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
50 | ␉outb(PCI_DATA_REG + (reg & 3), data);␊ |
51 | }␊ |
52 | ␊ |
53 | void pci_config_write16(uint32_t pci_addr, uint8_t reg, uint16_t data)␊ |
54 | {␊ |
55 | ␉pci_addr |= reg & ~3;␊ |
56 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
57 | ␉outw(PCI_DATA_REG + (reg & 2), data);␊ |
58 | }␊ |
59 | ␊ |
60 | void pci_config_write32(uint32_t pci_addr, uint8_t reg, uint32_t data)␊ |
61 | {␊ |
62 | ␉pci_addr |= reg & ~3;␊ |
63 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
64 | ␉outl(PCI_DATA_REG, data);␊ |
65 | }␊ |
66 | ␊ |
67 | void scan_pci_bus(pci_dt_t *start, uint8_t bus)␊ |
68 | {␊ |
69 | ␉pci_dt_t␉*new;␊ |
70 | ␉pci_dt_t␉**current = &start->children;␊ |
71 | ␉uint32_t␉id;␊ |
72 | ␉uint32_t␉pci_addr;␊ |
73 | ␉uint8_t␉␉dev = 0;␊ |
74 | ␉uint8_t␉␉func = 0;␊ |
75 | ␉uint8_t␉␉secondary_bus;␊ |
76 | ␉uint8_t␉␉header_type;␊ |
77 | ␊ |
78 | ␉for (dev = 0; dev < 32; dev++) {␊ |
79 | ␉␉for (func = 0; func < 8; func++) {␊ |
80 | ␉␉␉pci_addr = PCIADDR(bus, dev, func);␊ |
81 | ␉␉␉id = pci_config_read32(pci_addr, PCI_VENDOR_ID);␊ |
82 | ␉␉␉if (!id || id == 0xffffffff) {␊ |
83 | ␉␉␉␉continue;␊ |
84 | ␉␉␉}␊ |
85 | ␉␉␉new = (pci_dt_t*)malloc(sizeof(pci_dt_t));␊ |
86 | ␉␉␉bzero(new, sizeof(pci_dt_t));␊ |
87 | ␉␉␉new->dev.addr␉␉␉␉= pci_addr;␊ |
88 | ␉␉␉new->vendor_id␉␉␉␉= id & 0xffff;␊ |
89 | ␉␉␉new->device_id␉␉␉␉= (id >> 16) & 0xffff;␊ |
90 | ␉␉␉new->progif␉␉␉␉= pci_config_read8(pci_addr, PCI_CLASS_PROG);␊ |
91 | ␉␉␉new->revision_id␉␉␉= pci_config_read8(pci_addr, PCI_CLASS_REVISION);␊ |
92 | ␉␉␉new->subsys_id.subsys_id␉␉= pci_config_read32(pci_addr, PCI_SUBSYSTEM_VENDOR_ID);␊ |
93 | ␉␉␉new->class_id␉␉␉␉= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);␊ |
94 | ␉␉␉new->parent␉= start;␊ |
95 | ␊ |
96 | ␉␉␉header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);␊ |
97 | ␉␉␉switch (header_type & 0x7f) {␊ |
98 | ␉␉␉case PCI_HEADER_TYPE_BRIDGE:␊ |
99 | ␉␉␉case PCI_HEADER_TYPE_CARDBUS:␊ |
100 | ␉␉␉␉secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS);␊ |
101 | ␉␉␉␉if (secondary_bus != 0) {␊ |
102 | ␉␉␉␉␉scan_pci_bus(new, secondary_bus);␊ |
103 | ␉␉␉␉}␊ |
104 | ␉␉␉␉break;␊ |
105 | ␉␉␉}␊ |
106 | ␉␉␉*current = new;␊ |
107 | ␉␉␉current = &new->next;␊ |
108 | ␊ |
109 | ␉␉␉if ((func == 0) && ((header_type & 0x80) == 0)) {␊ |
110 | ␉␉␉␉break;␊ |
111 | ␉␉␉}␊ |
112 | ␉␉}␊ |
113 | ␉}␊ |
114 | }␊ |
115 | ␊ |
116 | void enable_pci_devs(void)␊ |
117 | {␊ |
118 | ␉uint16_t id;␊ |
119 | ␉uint32_t rcba, *fd;␊ |
120 | ␊ |
121 | ␉id = pci_config_read16(PCIADDR(0, 0x00, 0), 0x00);␊ |
122 | ␉/* make sure we're on Intel chipset */␊ |
123 | ␉if (id != 0x8086)␊ |
124 | ␉{␊ |
125 | ␉␉return;␊ |
126 | ␉}␊ |
127 | ␉rcba = pci_config_read32(PCIADDR(0, 0x1f, 0), 0xf0) & ~1;␊ |
128 | ␉fd = (uint32_t *)(rcba + 0x3418);␊ |
129 | ␉/* set SMBus Disable (SD) to 0 */␊ |
130 | ␉*fd &= ~0x8;␊ |
131 | ␉/* and all devices? */␊ |
132 | ␉//*fd = 0x1;␊ |
133 | }␊ |
134 | ␊ |
135 | ␊ |
136 | void build_pci_dt(void)␊ |
137 | {␊ |
138 | ␉root_pci_dev = malloc(sizeof(pci_dt_t));␊ |
139 | ␉bzero(root_pci_dev, sizeof(pci_dt_t));␊ |
140 | ␉enable_pci_devs();␊ |
141 | ␉scan_pci_bus(root_pci_dev, 0);␊ |
142 | ␊ |
143 | #if DEBUG_PCI␊ |
144 | ␉dump_pci_dt(root_pci_dev->children);␊ |
145 | ␉pause();␊ |
146 | #endif␊ |
147 | }␊ |
148 | ␊ |
149 | static char dev_path[256];␊ |
150 | char *get_pci_dev_path(pci_dt_t *pci_dt)␊ |
151 | {␊ |
152 | ␉pci_dt_t␉*current;␊ |
153 | ␉pci_dt_t␉*end;␊ |
154 | ␉char␉␉tmp[64];␊ |
155 | ␊ |
156 | ␉dev_path[0] = 0;␊ |
157 | ␉end = root_pci_dev;␊ |
158 | ␉␊ |
159 | ␉int uid = getPciRootUID();␊ |
160 | ␉while (end != pci_dt)␊ |
161 | ␉{␊ |
162 | ␉␉current = pci_dt;␊ |
163 | ␉␉while (current->parent != end)␊ |
164 | ␉␉␉current = current->parent;␉␉␉␊ |
165 | ␉␉end = current;␊ |
166 | ␉␉if (current->parent == root_pci_dev)␊ |
167 | ␉␉{␊ |
168 | ␉␉␉sprintf(tmp, "PciRoot(0x%x)/Pci(0x%x,0x%x)", uid, ␊ |
169 | ␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
170 | ␉␉} else {␊ |
171 | ␉␉␉sprintf(tmp, "/Pci(0x%x,0x%x)", ␊ |
172 | ␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
173 | ␉␉}␊ |
174 | ␉␉strcat(dev_path, tmp);␊ |
175 | ␉}␊ |
176 | ␉return dev_path;␊ |
177 | }␊ |
178 | ␊ |
179 | void dump_pci_dt(pci_dt_t *pci_dt)␊ |
180 | {␊ |
181 | ␉pci_dt_t␉*current;␊ |
182 | ␊ |
183 | ␉current = pci_dt;␊ |
184 | ␉while (current) {␊ |
185 | ␉␉printf("%02x:%02x.%x [%04x%02x] [%04x:%04x] (subsys [%04x:%04x]):: %s\n", ␊ |
186 | ␉␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊ |
187 | ␉␉␉current->class_id, current->vendor_id, current->device_id, ␊ |
188 | ␉␉␉current->subsys_id.subsys.vendor_id, current->subsys_id.subsys.device_id, ␊ |
189 | ␉␉␉get_pci_dev_path(current));␊ |
190 | ␉␉dump_pci_dt(current->children);␊ |
191 | ␉␉current = current->next;␊ |
192 | ␉}␊ |
193 | }␊ |
194 | |