1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PCI_H␊ |
8 | #define __LIBSAIO_PCI_H␊ |
9 | ␊ |
10 | /*␊ |
11 | * 31 24 16 15 11 10 8␊ |
12 | * +---------------------------------------------------------------+␊ |
13 | * |1| 0 | BUS | DEV |FUNC | 0 |␊ |
14 | * +---------------------------------------------------------------+␊ |
15 | */␊ |
16 | ␊ |
17 | typedef struct {␊ |
18 | ␉uint32_t␉␉:2;␊ |
19 | ␉uint32_t␉reg␉:6;␊ |
20 | ␉uint32_t␉func␉:3;␊ |
21 | ␉uint32_t␉dev␉:5;␊ |
22 | ␉uint32_t␉bus␉:8;␊ |
23 | ␉uint32_t␉␉:7;␊ |
24 | ␉uint32_t␉eb␉:1;␊ |
25 | } pci_addr_t;␊ |
26 | ␊ |
27 | typedef union {␊ |
28 | ␉pci_addr_t␉bits;␊ |
29 | ␉uint32_t␉addr;␊ |
30 | } pci_dev_t;␊ |
31 | ␊ |
32 | typedef struct pci_dt_t {␊ |
33 | ␉pci_dev_t␉dev;␊ |
34 | ␊ |
35 | ␉uint16_t␉vendor_id; /* Specifies a vendor ID. The PCI bus configuration code obtains this␊ |
36 | vendor ID from the vendor ID device register. */␊ |
37 | ␉uint16_t␉device_id; /* Specifies a device ID that identifies the specific device. The PCI␊ |
38 | bus configuration code obtains this device ID from the device ID␊ |
39 | device register. */␊ |
40 | ␊ |
41 | ␉union {␊ |
42 | ␉␉struct {␊ |
43 | ␉␉␉uint16_t␉vendor_id; /* Specifies a subsystem vendor ID. */␊ |
44 | ␉␉␉uint16_t␉device_id; /* Specifies a subsystem device ID that identifies the specific device. */␊ |
45 | ␉␉} subsys;␊ |
46 | ␉␉uint32_t␉subsys_id;␊ |
47 | ␉}subsys_id;␊ |
48 | ␊ |
49 | ␉uint8_t progif; /* A read-only register that specifies a register-level programming interface the device has, if it has any at all. */␊ |
50 | ␊ |
51 | ␉uint8_t revision_id; /* PCI revision ID. Specifies a revision identifier for a particular device. Where valid IDs are allocated by the vendor. */␊ |
52 | ␊ |
53 | ␉uint16_t␉class_id; /* Specifies a class code. This member is a data structure that stores information related to the device's class code device register. */␊ |
54 | ␊ |
55 | ␉struct pci_dt_t␉␉␉*parent;␊ |
56 | ␉struct pci_dt_t␉␉␉*children;␊ |
57 | ␉struct pci_dt_t␉␉␉*next;␊ |
58 | } pci_dt_t;␊ |
59 | ␊ |
60 | #define PCIADDR(bus, dev, func) ((1 << 31) | (bus << 16) | (dev << 11) | (func << 8))␊ |
61 | #define PCI_ADDR_REG␉␉0xcf8␊ |
62 | #define PCI_DATA_REG␉␉0xcfc␊ |
63 | ␊ |
64 | extern pci_dt_t␉␉*root_pci_dev;␊ |
65 | extern uint8_t␉␉pci_config_read8(uint32_t, uint8_t);␊ |
66 | extern uint16_t␉␉pci_config_read16(uint32_t, uint8_t);␊ |
67 | extern uint32_t␉␉pci_config_read32(uint32_t, uint8_t);␊ |
68 | extern void␉␉␉pci_config_write8(uint32_t, uint8_t, uint8_t);␊ |
69 | extern void␉␉␉pci_config_write16(uint32_t, uint8_t, uint16_t);␊ |
70 | extern void␉␉␉pci_config_write32(uint32_t, uint8_t, uint32_t);␊ |
71 | extern char␉␉␉*get_pci_dev_path(pci_dt_t *);␊ |
72 | extern void␉␉␉build_pci_dt(void);␊ |
73 | extern void␉␉␉dump_pci_dt(pci_dt_t *);␊ |
74 | ␊ |
75 | /* Option ROM header */␊ |
76 | typedef struct {␊ |
77 | ␉uint16_t␉␉signature;␉␉// 0xAA55␊ |
78 | ␉uint8_t␉␉␉rom_size;␊ |
79 | ␉uint32_t␉␉entry_point;␊ |
80 | ␉uint8_t␉␉␉reserved[15];␊ |
81 | ␉uint16_t␉␉pci_header_offset;␊ |
82 | ␉uint16_t␉␉expansion_header_offset;␊ |
83 | } option_rom_header_t;␊ |
84 | ␊ |
85 | /* Option ROM PCI Data Structure */␊ |
86 | typedef struct {␊ |
87 | ␉uint32_t␉␉signature;␉␉// ati - 0x52494350, nvidia - 0x50434952, 'PCIR'␊ |
88 | ␉uint16_t␉␉vendor_id;␊ |
89 | ␉uint16_t␉␉device_id;␊ |
90 | ␉uint16_t␉␉vital_product_data_offset;␊ |
91 | ␉uint16_t␉␉structure_length;␊ |
92 | ␉uint8_t␉␉␉structure_revision;␊ |
93 | ␉uint8_t␉␉␉class_code[3];␊ |
94 | ␉uint16_t␉␉image_length;␊ |
95 | ␉uint16_t␉␉image_revision;␊ |
96 | ␉uint8_t␉␉␉code_type;␊ |
97 | ␉uint8_t␉␉␉indicator;␊ |
98 | ␉uint16_t␉␉reserved;␊ |
99 | } option_rom_pci_header_t;␊ |
100 | ␊ |
101 | //-----------------------------------------------------------------------------␊ |
102 | // added by iNDi␊ |
103 | ␊ |
104 | typedef struct {␊ |
105 | ␉uint32_t␉␉signature;␉␉// 0x24506E50 '$PnP'␊ |
106 | ␉uint8_t␉␉␉revision;␉␉//␉1␊ |
107 | ␉uint8_t␉␉␉length;␊ |
108 | ␉uint16_t␉␉offset;␉␉␉␉␊ |
109 | ␉uint8_t␉␉␉checksum;␊ |
110 | ␉uint32_t␉␉identifier;␊ |
111 | ␉uint16_t␉␉manufacturer;␊ |
112 | ␉uint16_t␉␉product;␊ |
113 | ␉uint8_t␉␉␉class[3];␊ |
114 | ␉uint8_t␉␉␉indicators;␊ |
115 | ␉uint16_t␉␉boot_vector;␊ |
116 | ␉uint16_t␉␉disconnect_vector;␊ |
117 | ␉uint16_t␉␉bootstrap_vector;␊ |
118 | ␉uint16_t␉␉reserved;␊ |
119 | ␉uint16_t␉␉resource_vector;␊ |
120 | } option_rom_pnp_header_t;␊ |
121 | ␊ |
122 | /*␊ |
123 | * Under PCI, each device has 256 bytes of configuration address space,␊ |
124 | * of which the first 64 bytes are standardized as follows:␊ |
125 | *␊ |
126 | * register name offset␊ |
127 | *******************************************************/␊ |
128 | #define PCI_VENDOR_ID␉␉␉␉␉␉0x00␉␉/* 16 bits */␊ |
129 | #define PCI_DEVICE_ID␉␉␉␉␉␉0x02␉␉/* 16 bits */␊ |
130 | #define PCI_COMMAND␉␉␉␉␉␉␉0x04␉␉/* 16 bits */␊ |
131 | #define PCI_COMMAND_IO␉␉␉␉␉␉0x1␉␉␉/* Enable response in I/O space */␊ |
132 | #define PCI_COMMAND_MEMORY␉␉␉␉␉0x2␉␉␉/* Enable response in Memory space */␊ |
133 | #define PCI_COMMAND_MASTER␉␉␉␉␉0x4␉␉␉/* Enable bus mastering */␊ |
134 | #define PCI_COMMAND_SPECIAL␉␉␉␉␉0x8␉␉␉/* Enable response to special cycles */␊ |
135 | #define PCI_COMMAND_INVALIDATE␉␉␉␉0x10␉␉/* Use memory write and invalidate */␊ |
136 | #define PCI_COMMAND_VGA_PALETTE␉␉␉␉0x20␉␉/* Enable palette snooping */␊ |
137 | #define PCI_COMMAND_PARITY␉␉␉␉␉0x40␉␉/* Enable parity checking */␊ |
138 | #define PCI_COMMAND_WAIT␉␉␉␉␉0x80␉␉/* Enable address/data stepping */␊ |
139 | #define PCI_COMMAND_SERR␉␉␉␉␉0x100␉␉/* Enable SERR */␊ |
140 | #define PCI_COMMAND_FAST_BACK␉␉␉␉0x200␉␉/* Enable back-to-back writes */␊ |
141 | #define PCI_COMMAND_DISABLE_INTx␉␉␉0x400␉␉/* PCIE: Disable INTx interrupts */␊ |
142 | ␊ |
143 | #define PCI_STATUS␉␉␉␉␉␉␉0x06␉␉/* 16 bits */␊ |
144 | #define PCI_STATUS_INTx␉␉␉␉␉␉0x08␉␉/* PCIE: INTx interrupt pending */␊ |
145 | #define PCI_STATUS_CAP_LIST␉␉␉␉␉0x10␉␉/* Support Capability List */␊ |
146 | #define PCI_STATUS_66MHZ␉␉␉␉␉0x20␉␉/* Support 66 Mhz PCI 2.1 bus */␊ |
147 | #define PCI_STATUS_UDF␉␉␉␉␉␉0x40␉␉/* Support User Definable Features [obsolete] */␊ |
148 | #define PCI_STATUS_FAST_BACK␉␉␉␉0x80␉␉/* Accept fast-back to back */␊ |
149 | #define PCI_STATUS_PARITY␉␉␉␉␉0x100␉␉/* Detected parity error */␊ |
150 | #define PCI_STATUS_DEVSEL_MASK␉␉␉␉0x600␉␉/* DEVSEL timing */␊ |
151 | #define PCI_STATUS_DEVSEL_FAST␉␉␉␉0x000␊ |
152 | #define PCI_STATUS_DEVSEL_MEDIUM␉␉␉0x200␊ |
153 | #define PCI_STATUS_DEVSEL_SLOW␉␉␉␉0x400␊ |
154 | #define PCI_STATUS_SIG_TARGET_ABORT ␉␉0x800␉␉/* Set on target abort */␊ |
155 | #define PCI_STATUS_REC_TARGET_ABORT ␉␉0x1000␉␉/* Master ack of " */␊ |
156 | #define PCI_STATUS_REC_MASTER_ABORT ␉␉0x2000␉␉/* Set on master abort */␊ |
157 | #define PCI_STATUS_SIG_SYSTEM_ERROR ␉␉0x4000␉␉/* Set when we drive SERR */␊ |
158 | #define PCI_STATUS_DETECTED_PARITY␉␉␉0x8000␉␉/* Set on parity error */␊ |
159 | ␊ |
160 | #define PCI_CLASS_REVISION␉␉␉␉␉0x08␉␉␉/* High 24 bits are class, low 8 revision */␊ |
161 | #define PCI_CLASS_PROG␉␉␉␉␉␉0x09␉␉␉/* Reg. Level Programming Interface know also as PCI_PROG_IF */␊ |
162 | #define PCI_CLASS_DEVICE␉␉␉␉␉0x0a␉␉␉/* Device subclass */␊ |
163 | //#define PCI_SUBCLASS_DEVICE␉␉␉␉0x0b␉␉␉/* Device class */␊ |
164 | ␊ |
165 | #define PCI_CACHE_LINE_SIZE␉␉␉␉␉0x0c␉␉/* 8 bits */␊ |
166 | #define PCI_LATENCY_TIMER␉␉␉␉␉0x0d␉␉/* 8 bits */␊ |
167 | #define PCI_HEADER_TYPE␉␉␉␉␉␉0x0e␉␉/* 8 bits */␊ |
168 | #define PCI_HEADER_TYPE_NORMAL␉␉␉␉0␊ |
169 | #define PCI_HEADER_TYPE_BRIDGE␉␉␉␉1␊ |
170 | #define PCI_HEADER_TYPE_CARDBUS␉␉␉␉2␉␊ |
171 | ␊ |
172 | #define PCI_BIST␉␉␉␉␉␉␉0x0f␉␉/* 8 bits */␊ |
173 | #define PCI_BIST_CODE_MASK␉␉␉␉␉0x0f␉␉/* Return result */␊ |
174 | #define PCI_BIST_START␉␉␉␉␉␉0x40␉␉/* 1 to start BIST, 2 secs or less */␊ |
175 | #define PCI_BIST_CAPABLE␉␉␉␉␉0x80␉␉/* 1 if BIST capable */␊ |
176 | ␊ |
177 | /*␊ |
178 | * Base addresses specify locations in memory or I/O space.␊ |
179 | * Decoded size can be determined by writing a value of␊ |
180 | * 0xffffffff to the register, and reading it back. Only␊ |
181 | * 1 bits are decoded.␊ |
182 | */␊ |
183 | #define PCI_BASE_ADDRESS_0␉␉␉␉␉0x10␉␉/* 32 bits */␊ |
184 | #define PCI_BASE_ADDRESS_1␉␉␉␉␉0x14␉␉/* 32 bits [htype 0,1 only] */␊ |
185 | #define PCI_BASE_ADDRESS_2␉␉␉␉␉0x18␉␉/* 32 bits [htype 0 only] */␊ |
186 | #define PCI_BASE_ADDRESS_3␉␉␉␉␉0x1c␉␉/* 32 bits */␊ |
187 | #define PCI_BASE_ADDRESS_4␉␉␉␉␉0x20␉␉/* 32 bits */␊ |
188 | #define PCI_BASE_ADDRESS_5␉␉␉␉␉0x24␉␉/* 32 bits */␊ |
189 | #define PCI_BASE_ADDRESS_SPACE␉␉␉␉0x01␉␉/* 0 = memory, 1 = I/O */␊ |
190 | #define PCI_BASE_ADDRESS_SPACE_IO␉␉␉0x01␊ |
191 | #define PCI_BASE_ADDRESS_SPACE_MEMORY␉␉0x00␊ |
192 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK␉␉0x06␊ |
193 | #define PCI_BASE_ADDRESS_MEM_TYPE_32␉␉0x00␉␉/* 32 bit address */␊ |
194 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M␉␉0x02␉␉/* Below 1M [obsolete] */␊ |
195 | #define PCI_BASE_ADDRESS_MEM_TYPE_64␉␉0x04␉␉/* 64 bit address */␊ |
196 | #define PCI_BASE_ADDRESS_MEM_PREFETCH␉␉0x08␉␉/* prefetchable? */␊ |
197 | #define PCI_BASE_ADDRESS_MEM_MASK␉␉␉(~(pciaddr_t)0x0f)␊ |
198 | #define PCI_BASE_ADDRESS_IO_MASK␉␉␉(~(pciaddr_t)0x03)␊ |
199 | /* bit 1 is reserved if address_space = 1 */␊ |
200 | ␊ |
201 | /* Header type 0 (normal devices) */␊ |
202 | #define PCI_CARDBUS_CIS␉␉␉␉␉␉0x28␊ |
203 | #define PCI_SUBSYSTEM_VENDOR_ID␉␉␉␉0x2c␊ |
204 | #define PCI_SUBSYSTEM_ID␉␉␉␉␉0x2e␊ |
205 | #define PCI_ROM_ADDRESS␉␉␉␉␉␉0x30␉␉/* Bits 31..11 are address, 10..1 reserved */␊ |
206 | #define PCI_ROM_ADDRESS_ENABLE␉␉␉␉0x01␊ |
207 | #define PCI_ROM_ADDRESS_MASK␉␉␉␉(~(pciaddr_t)0x7ff)␊ |
208 | ␊ |
209 | #define PCI_CAPABILITY_LIST␉␉␉␉␉0x34␉␉/* Offset of first capability list entry */␊ |
210 | ␊ |
211 | /* 0x35-0x3b are reserved */␊ |
212 | #define PCI_INTERRUPT_LINE␉␉␉␉␉0x3c␉␉/* 8 bits */␊ |
213 | #define PCI_INTERRUPT_PIN␉␉␉␉␉0x3d␉␉/* 8 bits */␊ |
214 | #define PCI_MIN_GNT␉␉␉␉␉␉␉0x3e␉␉/* 8 bits */␊ |
215 | #define PCI_MAX_LAT␉␉␉␉␉␉␉0x3f␉␉/* 8 bits */␊ |
216 | ␊ |
217 | /* Header type 1 (PCI-to-PCI bridges) */␊ |
218 | #define PCI_PRIMARY_BUS␉␉␉␉␉␉0x18␉␉/* Primary bus number */␊ |
219 | #define PCI_SECONDARY_BUS␉␉␉␉␉0x19␉␉/* Secondary bus number */␊ |
220 | #define PCI_SUBORDINATE_BUS␉␉␉␉␉0x1a␉␉/* Highest bus number behind the bridge */␊ |
221 | #define PCI_SEC_LATENCY_TIMER␉␉␉␉0x1b␉␉/* Latency timer for secondary interface */␊ |
222 | #define PCI_IO_BASE␉␉␉␉␉␉␉0x1c␉␉/* I/O range behind the bridge */␊ |
223 | #define PCI_IO_LIMIT␉␉␉␉␉␉0x1d␊ |
224 | #define PCI_IO_RANGE_TYPE_MASK␉␉␉␉0x0f␉␉/* I/O bridging type */␊ |
225 | #define PCI_IO_RANGE_TYPE_16␉␉␉␉0x00␊ |
226 | #define PCI_IO_RANGE_TYPE_32␉␉␉␉0x01␊ |
227 | #define PCI_IO_RANGE_MASK␉␉␉␉␉~0x0f␊ |
228 | #define PCI_SEC_STATUS␉␉␉␉␉␉0x1e␉␉/* Secondary status register */␊ |
229 | #define PCI_MEMORY_BASE␉␉␉␉␉␉0x20␉␉/* Memory range behind */␊ |
230 | #define PCI_MEMORY_LIMIT␉␉␉␉␉0x22␊ |
231 | #define PCI_MEMORY_RANGE_TYPE_MASK␉␉␉0x0f␊ |
232 | #define PCI_MEMORY_RANGE_MASK␉␉␉␉~0x0f␊ |
233 | #define PCI_PREF_MEMORY_BASE␉␉␉␉0x24␉␉/* Prefetchable memory range behind */␊ |
234 | #define PCI_PREF_MEMORY_LIMIT␉␉␉␉0x26␊ |
235 | #define PCI_PREF_RANGE_TYPE_MASK␉␉␉0x0f␊ |
236 | #define PCI_PREF_RANGE_TYPE_32␉␉␉␉0x00␊ |
237 | #define PCI_PREF_RANGE_TYPE_64␉␉␉␉0x01␊ |
238 | #define PCI_PREF_RANGE_MASK␉␉␉␉␉~0x0f␊ |
239 | #define PCI_PREF_BASE_UPPER32␉␉␉␉0x28␉␉/* Upper half of prefetchable memory range */␊ |
240 | #define PCI_PREF_LIMIT_UPPER32␉␉␉␉0x2c␊ |
241 | #define PCI_IO_BASE_UPPER16␉␉␉␉␉0x30␉␉/* Upper half of I/O addresses */␊ |
242 | #define PCI_IO_LIMIT_UPPER16␉␉␉␉0x32␊ |
243 | /* 0x34 same as for htype 0 */␊ |
244 | /* 0x35-0x3b is reserved */␊ |
245 | #define PCI_ROM_ADDRESS1␉␉␉␉␉0x38␉␉/* Same as PCI_ROM_ADDRESS, but for htype 1 */␊ |
246 | /* 0x3c-0x3d are same as for htype 0 */␊ |
247 | #define PCI_BRIDGE_CONTROL␉␉␉␉␉0x3e␊ |
248 | #define PCI_BRIDGE_CTL_PARITY␉␉␉␉0x01␉␉/* Enable parity detection on secondary interface */␊ |
249 | #define PCI_BRIDGE_CTL_SERR␉␉␉␉␉0x02␉␉/* The same for SERR forwarding */␊ |
250 | #define PCI_BRIDGE_CTL_NO_ISA␉␉␉␉0x04␉␉/* Disable bridging of ISA ports */␊ |
251 | #define PCI_BRIDGE_CTL_VGA␉␉␉␉␉0x08␉␉/* Forward VGA addresses */␊ |
252 | #define PCI_BRIDGE_CTL_MASTER_ABORT␉␉␉0x20␉␉/* Report master aborts */␊ |
253 | #define PCI_BRIDGE_CTL_BUS_RESET␉␉␉0x40␉␉/* Secondary bus reset */␊ |
254 | #define PCI_BRIDGE_CTL_FAST_BACK␉␉␉0x80␉␉/* Fast Back2Back enabled on secondary interface */␊ |
255 | #define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER ␉0x100␉␉/* PCI-X? */␊ |
256 | #define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER ␉0x200␉␉/* PCI-X? */␊ |
257 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400␉␉/* PCI-X? */␊ |
258 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800␉␉/* PCI-X? */␊ |
259 | ␊ |
260 | /* Header type 2 (CardBus bridges) */␊ |
261 | /* 0x14-0x15 reserved */␊ |
262 | #define PCI_CB_SEC_STATUS␉␉␉␉␉0x16␉␉/* Secondary status */␊ |
263 | #define PCI_CB_PRIMARY_BUS␉␉␉␉␉0x18␉␉/* PCI bus number */␊ |
264 | #define PCI_CB_CARD_BUS␉␉␉␉␉␉0x19␉␉/* CardBus bus number */␊ |
265 | #define PCI_CB_SUBORDINATE_BUS␉␉␉␉0x1a␉␉/* Subordinate bus number */␊ |
266 | #define PCI_CB_LATENCY_TIMER␉␉␉␉0x1b␉␉/* CardBus latency timer */␊ |
267 | #define PCI_CB_MEMORY_BASE_0␉␉␉␉0x1c␊ |
268 | #define PCI_CB_MEMORY_LIMIT_0␉␉␉␉0x20␊ |
269 | #define PCI_CB_MEMORY_BASE_1␉␉␉␉0x24␊ |
270 | #define PCI_CB_MEMORY_LIMIT_1␉␉␉␉0x28␊ |
271 | #define PCI_CB_IO_BASE_0␉␉␉␉␉0x2c␊ |
272 | #define PCI_CB_IO_BASE_0_HI␉␉␉␉␉0x2e␊ |
273 | #define PCI_CB_IO_LIMIT_0␉␉␉␉␉0x30␊ |
274 | #define PCI_CB_IO_LIMIT_0_HI␉␉␉␉0x32␊ |
275 | #define PCI_CB_IO_BASE_1␉␉␉␉␉0x34␊ |
276 | #define PCI_CB_IO_BASE_1_HI␉␉␉␉␉0x36␊ |
277 | #define PCI_CB_IO_LIMIT_1␉␉␉␉␉0x38␊ |
278 | #define PCI_CB_IO_LIMIT_1_HI␉␉␉␉0x3a␊ |
279 | #define␉ PCI_CB_IO_RANGE_MASK␉␉␉␉~0x03␊ |
280 | /* 0x3c-0x3d are same as for htype 0 */␊ |
281 | #define PCI_CB_BRIDGE_CONTROL␉␉␉␉0x3e␊ |
282 | #define PCI_CB_BRIDGE_CTL_PARITY␉␉␉0x01␉␉/* Similar to standard bridge control register */␊ |
283 | #define PCI_CB_BRIDGE_CTL_SERR␉␉␉␉0x02␊ |
284 | #define PCI_CB_BRIDGE_CTL_ISA␉␉␉␉0x04␊ |
285 | #define PCI_CB_BRIDGE_CTL_VGA␉␉␉␉0x08␊ |
286 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT␉␉0x20␊ |
287 | #define PCI_CB_BRIDGE_CTL_CB_RESET␉␉␉0x40␉␉/* CardBus reset */␊ |
288 | #define PCI_CB_BRIDGE_CTL_16BIT_INT␉␉␉0x80␉␉/* Enable interrupt for 16-bit cards */␊ |
289 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 ␉0x100␉␉/* Prefetch enable for both memory regions */␊ |
290 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 ␉0x200␊ |
291 | #define PCI_CB_BRIDGE_CTL_POST_WRITES␉␉0x400␊ |
292 | #define PCI_CB_SUBSYSTEM_VENDOR_ID␉␉␉0x40␊ |
293 | #define PCI_CB_SUBSYSTEM_ID␉␉␉␉␉0x42␊ |
294 | #define PCI_CB_LEGACY_MODE_BASE␉␉␉␉0x44␉␉/* 16-bit PC Card legacy mode base address (ExCa) */␊ |
295 | /* 0x48-0x7f reserved */␊ |
296 | ␊ |
297 | /* Capability Identification Numbers list */␊ |
298 | #define PCI_CAP_LIST_ID␉␉␉␉␉␉0␉␉␉/* Capability ID */␊ |
299 | #define PCI_CAP_ID_PM␉␉␉␉␉␉0x01␉␉/* Power Management */␊ |
300 | #define PCI_CAP_ID_AGP␉␉␉␉␉␉0x02␉␉/* Accelerated Graphics Port */␊ |
301 | #define PCI_CAP_ID_VPD␉␉␉␉␉␉0x03␉␉/* Vital Product Data */␊ |
302 | #define PCI_CAP_ID_SLOTID␉␉␉␉␉0x04␉␉/* Slot Identification */␊ |
303 | #define PCI_CAP_ID_MSI␉␉␉␉␉␉0x05␉␉/* Message Signaled Interrupts */␊ |
304 | #define PCI_CAP_ID_CHSWP␉␉␉␉␉0x06␉␉/* CompactPCI HotSwap */␊ |
305 | #define PCI_CAP_ID_PCIX␉␉␉␉␉␉0x07␉␉/* PCI-X */␊ |
306 | #define PCI_CAP_ID_HT␉␉␉␉␉␉0x08␉␉/* HyperTransport */␊ |
307 | #define PCI_CAP_ID_VNDR␉␉␉␉␉␉0x09␉␉/* Vendor specific */␊ |
308 | #define PCI_CAP_ID_DBG␉␉␉␉␉␉0x0A␉␉/* Debug port */␊ |
309 | #define PCI_CAP_ID_CCRC␉␉␉␉␉␉0x0B␉␉/* CompactPCI Central Resource Control */␊ |
310 | #define PCI_CAP_ID_HOTPLUG␉␉␉␉␉0x0C␉␉/* PCI hot-plug */␊ |
311 | #define PCI_CAP_ID_SSVID␉␉␉␉␉0x0D␉␉/* Bridge subsystem vendor/device ID */␊ |
312 | #define PCI_CAP_ID_AGP3␉␉␉␉␉␉0x0E␉␉/* AGP 8x */␊ |
313 | #define PCI_CAP_ID_SECURE␉␉␉␉␉0x0F␉␉/* Secure device (?) */␊ |
314 | #define PCI_CAP_ID_EXP␉␉␉␉␉␉0x10␉␉/* PCI Express */␊ |
315 | #define PCI_CAP_ID_MSIX␉␉␉␉␉␉0x11␉␉/* MSI-X */␊ |
316 | #define PCI_CAP_ID_SATA␉␉␉␉␉␉0x12␉␉/* Serial-ATA HBA */␊ |
317 | #define PCI_CAP_ID_AF␉␉␉␉␉␉0x13␉␉/* Advanced features of PCI devices integrated in PCIe root cplx */␊ |
318 | #define PCI_CAP_LIST_NEXT␉␉␉␉␉1␉␉␉/* Next capability in the list */␊ |
319 | #define PCI_CAP_FLAGS␉␉␉␉␉␉2␉␉␉/* Capability defined flags (16 bits) */␊ |
320 | #define PCI_CAP_SIZEOF␉␉␉␉␉␉4␊ |
321 | ␊ |
322 | /* Capabilities residing in the␊ |
323 | PCI Express extended configuration space */␊ |
324 | #define PCI_EXT_CAP_ID_AER␉␉␉␉␉0x01␉␉/* Advanced Error Reporting */␊ |
325 | #define PCI_EXT_CAP_ID_VC␉␉␉␉␉0x02␉␉/* Virtual Channel */␊ |
326 | #define PCI_EXT_CAP_ID_DSN␉␉␉␉␉0x03␉␉/* Device Serial Number */␊ |
327 | #define PCI_EXT_CAP_ID_PB␉␉␉␉␉0x04␉␉/* Power Budgeting */␊ |
328 | #define PCI_EXT_CAP_ID_RCLINK␉␉␉␉0x05␉␉/* Root Complex Link Declaration */␊ |
329 | #define PCI_EXT_CAP_ID_RCILINK␉␉␉␉0x06␉␉/* Root Complex Internal Link Declaration */␊ |
330 | #define PCI_EXT_CAP_ID_RCECOLL␉␉␉␉0x07␉␉/* Root Complex Event Collector */␊ |
331 | #define PCI_EXT_CAP_ID_MFVC␉␉␉␉␉0x08␉␉/* Multi-Function Virtual Channel */␊ |
332 | #define PCI_EXT_CAP_ID_RBCB␉␉␉␉␉0x0a␉␉/* Root Bridge Control Block */␊ |
333 | #define PCI_EXT_CAP_ID_VNDR␉␉␉␉␉0x0b␉␉/* Vendor specific */␊ |
334 | #define PCI_EXT_CAP_ID_ACS␉␉␉␉␉0x0d␉␉/* Access Controls */␊ |
335 | #define PCI_EXT_CAP_ID_ARI␉␉␉␉␉0x0e␉␉/* Alternative Routing-ID Interpretation */␊ |
336 | #define PCI_EXT_CAP_ID_ATS␉␉␉␉␉0x0f␉␉/* Address Translation Service */␊ |
337 | #define PCI_EXT_CAP_ID_SRIOV␉␉␉␉0x10␉␉/* Single Root I/O Virtualization */␊ |
338 | ␊ |
339 | /* Power Management Registers */␊ |
340 | #define PCI_PM_CAP_VER_MASK␉␉␉␉␉0x0007␉␉/* Version (2=PM1.1) */␊ |
341 | #define PCI_PM_CAP_PME_CLOCK␉␉␉␉0x0008␉␉/* Clock required for PME generation */␊ |
342 | #define PCI_PM_CAP_DSI␉␉␉␉␉␉0x0020␉␉/* Device specific initialization required */␊ |
343 | #define PCI_PM_CAP_AUX_C_MASK␉␉␉␉0x01c0␉␉/* Maximum aux current required in D3cold */␊ |
344 | #define PCI_PM_CAP_D1␉␉␉␉␉␉0x0200␉␉/* D1 power state support */␊ |
345 | #define PCI_PM_CAP_D2␉␉␉␉␉␉0x0400␉␉/* D2 power state support */␊ |
346 | #define PCI_PM_CAP_PME_D0␉␉␉␉␉0x0800␉␉/* PME can be asserted from D0 */␊ |
347 | #define PCI_PM_CAP_PME_D1␉␉␉␉␉0x1000␉␉/* PME can be asserted from D1 */␊ |
348 | #define PCI_PM_CAP_PME_D2␉␉␉␉␉0x2000␉␉/* PME can be asserted from D2 */␊ |
349 | #define PCI_PM_CAP_PME_D3_HOT␉␉␉␉0x4000␉␉/* PME can be asserted from D3hot */␊ |
350 | #define PCI_PM_CAP_PME_D3_COLD␉␉␉␉0x8000␉␉/* PME can be asserted from D3cold */␊ |
351 | #define PCI_PM_CTRL␉␉␉␉␉␉␉4␉␉␉/* PM control and status register */␊ |
352 | #define PCI_PM_CTRL_STATE_MASK␉␉␉␉0x0003␉␉/* Current power state (D0 to D3) */␊ |
353 | #define PCI_PM_CTRL_PME_ENABLE␉␉␉␉0x0100␉␉/* PME pin enable */␊ |
354 | #define PCI_PM_CTRL_DATA_SEL_MASK␉␉␉0x1e00␉␉/* PM table data index */␊ |
355 | #define PCI_PM_CTRL_DATA_SCALE_MASK␉␉␉0x6000␉␉/* PM table data scaling factor */␊ |
356 | #define PCI_PM_CTRL_PME_STATUS␉␉␉␉0x8000␉␉/* PME pin status */␊ |
357 | #define PCI_PM_PPB_EXTENSIONS␉␉␉␉6␉␉␉/* PPB support extensions */␊ |
358 | #define PCI_PM_PPB_B2_B3␉␉␉␉␉0x40␉␉/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */␊ |
359 | #define PCI_PM_BPCC_ENABLE␉␉␉␉␉0x80␉␉/* Secondary bus is power managed */␊ |
360 | #define PCI_PM_DATA_REGISTER␉␉␉␉7␉␉␉/* PM table contents read here */␊ |
361 | #define PCI_PM_SIZEOF␉␉␉␉␉␉8␊ |
362 | ␊ |
363 | /* AGP registers */␊ |
364 | #define PCI_AGP_VERSION␉␉␉␉␉␉2␉␉␉/* BCD version number */␊ |
365 | #define PCI_AGP_RFU␉␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
366 | #define PCI_AGP_STATUS␉␉␉␉␉␉4␉␉␉/* Status register */␊ |
367 | #define PCI_AGP_STATUS_RQ_MASK␉␉␉␉0xff000000␉/* Maximum number of requests - 1 */␊ |
368 | #define PCI_AGP_STATUS_ISOCH␉␉␉␉0x10000␉␉/* Isochronous transactions supported */␊ |
369 | #define PCI_AGP_STATUS_ARQSZ_MASK␉␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
370 | #define PCI_AGP_STATUS_CAL_MASK␉␉␉␉0x1c00␉␉/* Calibration cycle timing */␊ |
371 | #define PCI_AGP_STATUS_SBA␉␉␉␉␉0x0200␉␉/* Sideband addressing supported */␊ |
372 | #define PCI_AGP_STATUS_ITA_COH␉␉␉␉0x0100␉␉/* In-aperture accesses always coherent */␊ |
373 | #define PCI_AGP_STATUS_GART64␉␉␉␉0x0080␉␉/* 64-bit GART entries supported */␊ |
374 | #define PCI_AGP_STATUS_HTRANS␉␉␉␉0x0040␉␉/* If 0, core logic can xlate host CPU accesses thru aperture */␊ |
375 | #define PCI_AGP_STATUS_64BIT␉␉␉␉0x0020␉␉/* 64-bit addressing cycles supported */␊ |
376 | #define PCI_AGP_STATUS_FW␉␉␉␉␉0x0010␉␉/* Fast write transfers supported */␊ |
377 | #define PCI_AGP_STATUS_AGP3␉␉␉␉␉0x0008␉␉/* AGP3 mode supported */␊ |
378 | #define PCI_AGP_STATUS_RATE4␉␉␉␉0x0004␉␉/* 4x transfer rate supported (RFU in AGP3 mode) */␊ |
379 | #define PCI_AGP_STATUS_RATE2␉␉␉␉0x0002␉␉/* 2x transfer rate supported (8x in AGP3 mode) */␊ |
380 | #define PCI_AGP_STATUS_RATE1␉␉␉␉0x0001␉␉/* 1x transfer rate supported (4x in AGP3 mode) */␊ |
381 | #define PCI_AGP_COMMAND␉␉␉␉␉␉8␉␉␉/* Control register */␊ |
382 | #define PCI_AGP_COMMAND_RQ_MASK␉␉␉␉0xff000000␉/* Master: Maximum number of requests */␊ |
383 | #define PCI_AGP_COMMAND_ARQSZ_MASK␉␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
384 | #define PCI_AGP_COMMAND_CAL_MASK␉␉␉0x1c00␉␉/* Calibration cycle timing */␊ |
385 | #define PCI_AGP_COMMAND_SBA␉␉␉␉␉0x0200␉␉/* Sideband addressing enabled */␊ |
386 | #define PCI_AGP_COMMAND_AGP␉␉␉␉␉0x0100␉␉/* Allow processing of AGP transactions */␊ |
387 | #define PCI_AGP_COMMAND_GART64␉␉␉␉0x0080␉␉/* 64-bit GART entries enabled */␊ |
388 | #define PCI_AGP_COMMAND_64BIT␉␉␉␉0x0020␉␉/* Allow generation of 64-bit addr cycles */␊ |
389 | #define PCI_AGP_COMMAND_FW␉␉␉␉␉0x0010␉␉/* Enable FW transfers */␊ |
390 | #define PCI_AGP_COMMAND_RATE4␉␉␉␉0x0004␉␉/* Use 4x rate (RFU in AGP3 mode) */␊ |
391 | #define PCI_AGP_COMMAND_RATE2␉␉␉␉0x0002␉␉/* Use 2x rate (8x in AGP3 mode) */␊ |
392 | #define PCI_AGP_COMMAND_RATE1␉␉␉␉0x0001␉␉/* Use 1x rate (4x in AGP3 mode) */␊ |
393 | #define PCI_AGP_SIZEOF␉␉␉␉␉␉12␊ |
394 | ␊ |
395 | /* Vital Product Data */␊ |
396 | #define PCI_VPD_ADDR␉␉␉␉␉␉2␉␉␉/* Address to access (15 bits!) */␊ |
397 | #define PCI_VPD_ADDR_MASK␉␉␉␉␉0x7fff␉␉/* Address mask */␊ |
398 | #define PCI_VPD_ADDR_F␉␉␉␉␉␉0x8000␉␉/* Write 0, 1 indicates completion */␊ |
399 | #define PCI_VPD_DATA␉␉␉␉␉␉4␉␉␉/* 32-bits of data returned here */␊ |
400 | ␊ |
401 | /* Slot Identification */␊ |
402 | #define PCI_SID_ESR␉␉␉␉␉␉␉2␉␉␉/* Expansion Slot Register */␊ |
403 | #define PCI_SID_ESR_NSLOTS␉␉␉␉␉0x1f␉␉/* Number of expansion slots available */␊ |
404 | #define PCI_SID_ESR_FIC␉␉␉␉␉␉0x20␉␉/* First In Chassis Flag */␊ |
405 | #define PCI_SID_CHASSIS_NR␉␉␉␉␉3␉␉␉/* Chassis Number */␊ |
406 | ␊ |
407 | /* Message Signaled Interrupts registers */␊ |
408 | #define PCI_MSI_FLAGS␉␉␉␉␉␉2␉␉␉/* Various flags */␊ |
409 | #define PCI_MSI_FLAGS_MASK_BIT␉␉␉␉0x100␉␉/* interrupt masking & reporting supported */␊ |
410 | #define PCI_MSI_FLAGS_64BIT␉␉␉␉␉0x080␉␉/* 64-bit addresses allowed */␊ |
411 | #define PCI_MSI_FLAGS_QSIZE␉␉␉␉␉0x070␉␉/* Message queue size configured */␊ |
412 | #define PCI_MSI_FLAGS_QMASK␉␉␉␉␉0x00e␉␉/* Maximum queue size available */␊ |
413 | #define PCI_MSI_FLAGS_ENABLE␉␉␉␉0x001␉␉/* MSI feature enabled */␊ |
414 | #define PCI_MSI_RFU␉␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
415 | #define PCI_MSI_ADDRESS_LO␉␉␉␉␉4␉␉␉/* Lower 32 bits */␊ |
416 | #define PCI_MSI_ADDRESS_HI␉␉␉␉␉8␉␉␉/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */␊ |
417 | #define PCI_MSI_DATA_32␉␉␉␉␉␉8␉␉␉/* 16 bits of data for 32-bit devices */␊ |
418 | #define PCI_MSI_DATA_64␉␉␉␉␉␉12␉␉␉/* 16 bits of data for 64-bit devices */␊ |
419 | #define PCI_MSI_MASK_BIT_32␉␉␉␉␉12␉␉␉/* per-vector masking for 32-bit devices */␊ |
420 | #define PCI_MSI_MASK_BIT_64␉␉␉␉␉16␉␉␉/* per-vector masking for 64-bit devices */␊ |
421 | #define PCI_MSI_PENDING_32␉␉␉␉␉16␉␉␉/* per-vector interrupt pending for 32-bit devices */␊ |
422 | #define PCI_MSI_PENDING_64␉␉␉␉␉20␉␉␉/* per-vector interrupt pending for 64-bit devices */␊ |
423 | ␊ |
424 | /* PCI-X */␊ |
425 | #define PCI_PCIX_COMMAND␉␉␉␉␉␉␉␉␉␉␉␉2 /* Command register offset */␊ |
426 | #define PCI_PCIX_COMMAND_DPERE␉␉␉␉␉␉␉␉␉ 0x0001 /* Data Parity Error Recover Enable */␊ |
427 | #define PCI_PCIX_COMMAND_ERO␉␉␉␉␉␉␉␉␉ 0x0002 /* Enable Relaxed Ordering */␊ |
428 | #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT␉␉␉␉ 0x000c /* Maximum Memory Read Byte Count */␊ |
429 | #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS␉␉␉ 0x0070␊ |
430 | #define PCI_PCIX_COMMAND_RESERVED␉␉␉␉␉␉␉␉␉0xf80␊ |
431 | #define PCI_PCIX_STATUS␉␉␉␉␉␉␉␉␉␉␉␉␉4 /* Status register offset */␊ |
432 | #define PCI_PCIX_STATUS_FUNCTION␉␉␉␉␉␉␉ 0x00000007␊ |
433 | #define PCI_PCIX_STATUS_DEVICE␉␉␉␉␉␉␉␉ 0x000000f8␊ |
434 | #define PCI_PCIX_STATUS_BUS␉␉␉␉␉␉␉␉␉ 0x0000ff00␊ |
435 | #define PCI_PCIX_STATUS_64BIT␉␉␉␉␉␉␉␉ 0x00010000␊ |
436 | #define PCI_PCIX_STATUS_133MHZ␉␉␉␉␉␉␉␉ 0x00020000␊ |
437 | #define PCI_PCIX_STATUS_SC_DISCARDED␉␉␉␉␉␉ 0x00040000 /* Split Completion Discarded */␊ |
438 | #define PCI_PCIX_STATUS_UNEXPECTED_SC␉␉␉␉␉␉ 0x00080000 /* Unexpected Split Completion */␊ |
439 | #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY␉␉␉␉␉ 0x00100000 /* 0 = simple device, 1 = bridge device */␊ |
440 | #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT␉ 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */␊ |
441 | #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000␊ |
442 | #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE␉ 0x1c000000␊ |
443 | #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS␉␉␉␉␉ 0x20000000 /* Received Split Completion Error Message */␊ |
444 | #define PCI_PCIX_STATUS_266MHZ␉␉␉␉␉␉␉␉ 0x40000000 /* 266 MHz capable */␊ |
445 | #define PCI_PCIX_STATUS_533MHZ␉␉␉␉␉␉␉␉ 0x80000000 /* 533 MHz capable */␊ |
446 | #define PCI_PCIX_SIZEOF␉␉4␊ |
447 | ␊ |
448 | ␊ |
449 | /* PCI-X Bridges */␊ |
450 | #define PCI_PCIX_BRIDGE_SEC_STATUS␉␉␉␉␉␉␉␉␉␉2 /* Secondary bus status register offset */␊ |
451 | #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT␉␉␉␉␉␉ 0x0001␊ |
452 | #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ␉␉␉␉␉␉ 0x0002␊ |
453 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED␉␉␉␉␉ 0x0004 /* Split Completion Discarded on secondary bus */␊ |
454 | #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC␉␉␉␉ 0x0008 /* Unexpected Split Completion on secondary bus */␊ |
455 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN␉␉␉␉␉ 0x0010 /* Split Completion Overrun on secondary bus */␊ |
456 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED␉␉ 0x0020␊ |
457 | #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ␉␉␉␉␉ 0x01c0␊ |
458 | #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED␉␉␉␉␉␉ 0xfe00␊ |
459 | #define PCI_PCIX_BRIDGE_STATUS␉␉␉␉␉␉␉␉␉␉␉4 /* Primary bus status register offset */␊ |
460 | #define PCI_PCIX_BRIDGE_STATUS_FUNCTION␉␉␉␉␉␉ 0x00000007␊ |
461 | #define PCI_PCIX_BRIDGE_STATUS_DEVICE␉␉␉␉␉␉ 0x000000f8␊ |
462 | #define PCI_PCIX_BRIDGE_STATUS_BUS␉␉␉␉␉␉␉ 0x0000ff00␊ |
463 | #define PCI_PCIX_BRIDGE_STATUS_64BIT␉␉␉␉␉␉ 0x00010000␊ |
464 | #define PCI_PCIX_BRIDGE_STATUS_133MHZ␉␉␉␉␉␉ 0x00020000␊ |
465 | #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED␉␉␉␉␉ 0x00040000 /* Split Completion Discarded */␊ |
466 | #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC␉␉␉␉ 0x00080000 /* Unexpected Split Completion */␊ |
467 | #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN␉␉␉␉␉ 0x00100000 /* Split Completion Overrun */␊ |
468 | #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED␉␉ 0x00200000␊ |
469 | #define PCI_PCIX_BRIDGE_STATUS_RESERVED␉␉␉␉␉␉ 0xffc00000␊ |
470 | #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL␉␉␉␉␉␉8 /* Upstream Split Transaction Register offset */␊ |
471 | #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL␉␉␉␉␉ 12 /* Downstream Split Transaction Register offset */␊ |
472 | #define PCI_PCIX_BRIDGE_STR_CAPACITY␉␉␉␉␉␉ 0x0000ffff␊ |
473 | #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT␉␉␉␉ 0xffff0000␊ |
474 | #define PCI_PCIX_BRIDGE_SIZEOF 12␊ |
475 | ␊ |
476 | /* PCI Express */␊ |
477 | #define PCI_EXP_FLAGS␉␉␉␉␉␉0x2␉␉␉/* Capabilities register */␊ |
478 | #define PCI_EXP_FLAGS_VERS␉␉␉␉␉0x000f␉␉/* Capability version */␊ |
479 | #define PCI_EXP_FLAGS_TYPE␉␉␉␉␉0x00f0␉␉/* Device/Port type */␊ |
480 | #define PCI_EXP_TYPE_ENDPOINT␉␉␉␉0x0 ␉␉/* Express Endpoint */␊ |
481 | #define PCI_EXP_TYPE_LEG_END␉␉␉␉0x1 ␉␉/* Legacy Endpoint */␊ |
482 | #define PCI_EXP_TYPE_ROOT_PORT␉␉␉␉0x4 ␉␉/* Root Port */␊ |
483 | #define PCI_EXP_TYPE_UPSTREAM␉␉␉␉0x5 ␉␉/* Upstream Port */␊ |
484 | #define PCI_EXP_TYPE_DOWNSTREAM␉␉␉␉0x6 ␉␉/* Downstream Port */␊ |
485 | #define PCI_EXP_TYPE_PCI_BRIDGE␉␉␉␉0x7 ␉␉/* PCI/PCI-X Bridge */␊ |
486 | #define PCI_EXP_TYPE_PCIE_BRIDGE␉␉␉0x8 ␉␉/* PCI/PCI-X to PCIE Bridge */␊ |
487 | #define PCI_EXP_TYPE_ROOT_INT_EP␉␉␉0x9 ␉␉/* Root Complex Integrated Endpoint */␊ |
488 | #define PCI_EXP_TYPE_ROOT_EC␉␉␉␉0xa ␉␉/* Root Complex Event Collector */␊ |
489 | #define PCI_EXP_FLAGS_SLOT␉␉␉␉␉0x0100␉␉/* Slot implemented */␊ |
490 | #define PCI_EXP_FLAGS_IRQ␉␉␉␉␉0x3e00␉␉/* Interrupt message number */␊ |
491 | #define PCI_EXP_DEVCAP␉␉␉␉␉␉0x4 ␉␉/* Device capabilities */␊ |
492 | #define PCI_EXP_DEVCAP_PAYLOAD␉␉␉␉0x07␉␉/* Max_Payload_Size */␊ |
493 | #define PCI_EXP_DEVCAP_PHANTOM␉␉␉␉0x18␉␉/* Phantom functions */␊ |
494 | #define PCI_EXP_DEVCAP_EXT_TAG␉␉␉␉0x20␉␉/* Extended tags */␊ |
495 | #define PCI_EXP_DEVCAP_L0S␉␉␉␉␉0x1c0␉␉/* L0s Acceptable Latency */␊ |
496 | #define PCI_EXP_DEVCAP_L1␉␉␉␉␉0xe00␉␉/* L1 Acceptable Latency */␊ |
497 | #define PCI_EXP_DEVCAP_ATN_BUT␉␉␉␉0x1000␉␉/* Attention Button Present */␊ |
498 | #define PCI_EXP_DEVCAP_ATN_IND␉␉␉␉0x2000␉␉/* Attention Indicator Present */␊ |
499 | #define PCI_EXP_DEVCAP_PWR_IND␉␉␉␉0x4000␉␉/* Power Indicator Present */␊ |
500 | #define PCI_EXP_DEVCAP_RBE␉␉␉␉␉0x8000␉␉/* Role-Based Error Reporting */␊ |
501 | #define PCI_EXP_DEVCAP_PWR_VAL␉␉␉␉0x3fc0000␉/* Slot Power Limit Value */␊ |
502 | #define PCI_EXP_DEVCAP_PWR_SCL␉␉␉␉0xc000000␉/* Slot Power Limit Scale */␊ |
503 | #define PCI_EXP_DEVCAP_FLRESET␉␉␉␉0x10000000␉/* Function-Level Reset */␊ |
504 | #define PCI_EXP_DEVCTL␉␉␉␉␉␉0x8␉␉␉/* Device Control */␊ |
505 | #define PCI_EXP_DEVCTL_CERE␉␉␉␉␉0x0001␉␉/* Correctable Error Reporting En. */␊ |
506 | #define PCI_EXP_DEVCTL_NFERE␉␉␉␉0x0002␉␉/* Non-Fatal Error Reporting Enable */␊ |
507 | #define PCI_EXP_DEVCTL_FERE␉␉␉␉␉0x0004␉␉/* Fatal Error Reporting Enable */␊ |
508 | #define PCI_EXP_DEVCTL_URRE␉␉␉␉␉0x0008␉␉/* Unsupported Request Reporting En. */␊ |
509 | #define PCI_EXP_DEVCTL_RELAXED␉␉␉␉0x0010␉␉/* Enable Relaxed Ordering */␊ |
510 | #define PCI_EXP_DEVCTL_PAYLOAD␉␉␉␉0x00e0␉␉/* Max_Payload_Size */␊ |
511 | #define PCI_EXP_DEVCTL_EXT_TAG␉␉␉␉0x0100␉␉/* Extended Tag Field Enable */␊ |
512 | #define PCI_EXP_DEVCTL_PHANTOM␉␉␉␉0x0200␉␉/* Phantom Functions Enable */␊ |
513 | #define PCI_EXP_DEVCTL_AUX_PME␉␉␉␉0x0400␉␉/* Auxiliary Power PM Enable */␊ |
514 | #define PCI_EXP_DEVCTL_NOSNOOP␉␉␉␉0x0800␉␉/* Enable No Snoop */␊ |
515 | #define PCI_EXP_DEVCTL_READRQ␉␉␉␉0x7000␉␉/* Max_Read_Request_Size */␊ |
516 | #define PCI_EXP_DEVCTL_BCRE␉␉␉␉␉0x8000␉␉/* Bridge Configuration Retry Enable */␊ |
517 | #define PCI_EXP_DEVCTL_FLRESET␉␉␉␉0x8000␉␉/* Function-Level Reset [bit shared with BCRE] */␊ |
518 | #define PCI_EXP_DEVSTA␉␉␉␉␉␉0xa ␉␉/* Device Status */␊ |
519 | #define PCI_EXP_DEVSTA_CED␉␉␉␉␉0x01␉␉/* Correctable Error Detected */␊ |
520 | #define PCI_EXP_DEVSTA_NFED␉␉␉␉␉0x02␉␉/* Non-Fatal Error Detected */␊ |
521 | #define PCI_EXP_DEVSTA_FED␉␉␉␉␉0x04␉␉/* Fatal Error Detected */␊ |
522 | #define PCI_EXP_DEVSTA_URD␉␉␉␉␉0x08␉␉/* Unsupported Request Detected */␊ |
523 | #define PCI_EXP_DEVSTA_AUXPD␉␉␉␉0x10␉␉/* AUX Power Detected */␊ |
524 | #define PCI_EXP_DEVSTA_TRPND␉␉␉␉0x20␉␉/* Transactions Pending */␊ |
525 | #define PCI_EXP_LNKCAP␉␉␉␉␉␉0xc␉␉␉/* Link Capabilities */␊ |
526 | #define PCI_EXP_LNKCAP_SPEED␉␉␉␉0x0000f ␉/* Maximum Link Speed */␊ |
527 | #define PCI_EXP_LNKCAP_WIDTH␉␉␉␉0x003f0 ␉/* Maximum Link Width */␊ |
528 | #define PCI_EXP_LNKCAP_ASPM␉␉␉␉␉0x00c00 ␉/* Active State Power Management */␊ |
529 | #define PCI_EXP_LNKCAP_L0S␉␉␉␉␉0x07000 ␉/* L0s Acceptable Latency */␊ |
530 | #define PCI_EXP_LNKCAP_L1␉␉␉␉␉0x38000 ␉/* L1 Acceptable Latency */␊ |
531 | #define PCI_EXP_LNKCAP_CLOCKPM␉␉␉␉0x40000 ␉/* Clock Power Management */␊ |
532 | #define PCI_EXP_LNKCAP_SURPRISE␉␉␉␉0x80000 ␉/* Surprise Down Error Reporting */␊ |
533 | #define PCI_EXP_LNKCAP_DLLA␉␉␉␉␉0x100000␉/* Data Link Layer Active Reporting */␊ |
534 | #define PCI_EXP_LNKCAP_LBNC␉␉␉␉␉0x200000␉/* Link Bandwidth Notification Capability */␊ |
535 | #define PCI_EXP_LNKCAP_PORT␉␉␉␉␉0xff000000␉/* Port Number */␊ |
536 | #define PCI_EXP_LNKCTL␉␉␉␉␉␉0x10␉␉/* Link Control */␊ |
537 | #define PCI_EXP_LNKCTL_ASPM␉␉␉␉␉0x0003␉␉/* ASPM Control */␊ |
538 | #define PCI_EXP_LNKCTL_RCB␉␉␉␉␉0x0008␉␉/* Read Completion Boundary */␊ |
539 | #define PCI_EXP_LNKCTL_DISABLE␉␉␉␉0x0010␉␉/* Link Disable */␊ |
540 | #define PCI_EXP_LNKCTL_RETRAIN␉␉␉␉0x0020␉␉/* Retrain Link */␊ |
541 | #define PCI_EXP_LNKCTL_CLOCK␉␉␉␉0x0040␉␉/* Common Clock Configuration */␊ |
542 | #define PCI_EXP_LNKCTL_XSYNCH␉␉␉␉0x0080␉␉/* Extended Synch */␊ |
543 | #define PCI_EXP_LNKCTL_CLOCKPM␉␉␉␉0x0100␉␉/* Clock Power Management */␊ |
544 | #define PCI_EXP_LNKCTL_HWAUTWD␉␉␉␉0x0200␉␉/* Hardware Autonomous Width Disable */␊ |
545 | #define PCI_EXP_LNKCTL_BWMIE␉␉␉␉0x0400␉␉/* Bandwidth Mgmt Interrupt Enable */␊ |
546 | #define PCI_EXP_LNKCTL_AUTBWIE␉␉␉␉0x0800␉␉/* Autonomous Bandwidth Mgmt Interrupt Enable */␊ |
547 | #define PCI_EXP_LNKSTA␉␉␉␉␉␉0x12␉␉/* Link Status */␊ |
548 | #define PCI_EXP_LNKSTA_SPEED␉␉␉␉0x000f␉␉/* Negotiated Link Speed */␊ |
549 | #define PCI_EXP_LNKSTA_WIDTH␉␉␉␉0x03f0␉␉/* Negotiated Link Width */␊ |
550 | #define PCI_EXP_LNKSTA_TR_ERR␉␉␉␉0x0400␉␉/* Training Error (obsolete) */␊ |
551 | #define PCI_EXP_LNKSTA_TRAIN␉␉␉␉0x0800␉␉/* Link Training */␊ |
552 | #define PCI_EXP_LNKSTA_SL_CLK␉␉␉␉0x1000␉␉/* Slot Clock Configuration */␊ |
553 | #define PCI_EXP_LNKSTA_DL_ACT␉␉␉␉0x2000␉␉/* Data Link Layer in DL_Active State */␊ |
554 | #define PCI_EXP_LNKSTA_BWMGMT␉␉␉␉0x4000␉␉/* Bandwidth Mgmt Status */␊ |
555 | #define PCI_EXP_LNKSTA_AUTBW␉␉␉␉0x8000␉␉/* Autonomous Bandwidth Mgmt Status */␊ |
556 | #define PCI_EXP_SLTCAP␉␉␉␉␉␉0x14␉␉/* Slot Capabilities */␊ |
557 | #define PCI_EXP_SLTCAP_ATNB␉␉␉␉␉0x0001␉␉/* Attention Button Present */␊ |
558 | #define PCI_EXP_SLTCAP_PWRC␉␉␉␉␉0x0002␉␉/* Power Controller Present */␊ |
559 | #define PCI_EXP_SLTCAP_MRL␉␉␉␉␉0x0004␉␉/* MRL Sensor Present */␊ |
560 | #define PCI_EXP_SLTCAP_ATNI␉␉␉␉␉0x0008␉␉/* Attention Indicator Present */␊ |
561 | #define PCI_EXP_SLTCAP_PWRI␉␉␉␉␉0x0010␉␉/* Power Indicator Present */␊ |
562 | #define PCI_EXP_SLTCAP_HPS␉␉␉␉␉0x0020␉␉/* Hot-Plug Surprise */␊ |
563 | #define PCI_EXP_SLTCAP_HPC␉␉␉␉␉0x0040␉␉/* Hot-Plug Capable */␊ |
564 | #define PCI_EXP_SLTCAP_PWR_VAL␉␉␉␉0x00007f80␉/* Slot Power Limit Value */␊ |
565 | #define PCI_EXP_SLTCAP_PWR_SCL␉␉␉␉0x00018000␉/* Slot Power Limit Scale */␊ |
566 | #define PCI_EXP_SLTCAP_INTERLOCK␉␉␉0x020000␉/* Electromechanical Interlock Present */␊ |
567 | #define PCI_EXP_SLTCAP_NOCMDCOMP␉␉␉0x040000␉/* No Command Completed Support */␊ |
568 | #define PCI_EXP_SLTCAP_PSN␉␉␉␉␉0xfff80000␉/* Physical Slot Number */␊ |
569 | #define PCI_EXP_SLTCTL␉␉␉␉␉␉0x18␉␉/* Slot Control */␊ |
570 | #define PCI_EXP_SLTCTL_ATNB␉␉␉␉␉0x0001␉␉/* Attention Button Pressed Enable */␊ |
571 | #define PCI_EXP_SLTCTL_PWRF␉␉␉␉␉0x0002␉␉/* Power Fault Detected Enable */␊ |
572 | #define PCI_EXP_SLTCTL_MRLS␉␉␉␉␉0x0004␉␉/* MRL Sensor Changed Enable */␊ |
573 | #define PCI_EXP_SLTCTL_PRSD␉␉␉␉␉0x0008␉␉/* Presence Detect Changed Enable */␊ |
574 | #define PCI_EXP_SLTCTL_CMDC␉␉␉␉␉0x0010␉␉/* Command Completed Interrupt Enable */␊ |
575 | #define PCI_EXP_SLTCTL_HPIE␉␉␉␉␉0x0020␉␉/* Hot-Plug Interrupt Enable */␊ |
576 | #define PCI_EXP_SLTCTL_ATNI␉␉␉␉␉0x00c0␉␉/* Attention Indicator Control */␊ |
577 | #define PCI_EXP_SLTCTL_PWRI␉␉␉␉␉0x0300␉␉/* Power Indicator Control */␊ |
578 | #define PCI_EXP_SLTCTL_PWRC␉␉␉␉␉0x0400␉␉/* Power Controller Control */␊ |
579 | #define PCI_EXP_SLTCTL_INTERLOCK␉␉␉0x0800␉␉/* Electromechanical Interlock Control */␊ |
580 | #define PCI_EXP_SLTCTL_LLCHG␉␉␉␉0x1000␉␉/* Data Link Layer State Changed Enable */␊ |
581 | #define PCI_EXP_SLTSTA␉␉␉␉␉␉0x1a␉␉/* Slot Status */␊ |
582 | #define PCI_EXP_SLTSTA_ATNB␉␉␉␉␉0x0001␉␉/* Attention Button Pressed */␊ |
583 | #define PCI_EXP_SLTSTA_PWRF␉␉␉␉␉0x0002␉␉/* Power Fault Detected */␊ |
584 | #define PCI_EXP_SLTSTA_MRLS␉␉␉␉␉0x0004␉␉/* MRL Sensor Changed */␊ |
585 | #define PCI_EXP_SLTSTA_PRSD␉␉␉␉␉0x0008␉␉/* Presence Detect Changed */␊ |
586 | #define PCI_EXP_SLTSTA_CMDC␉␉␉␉␉0x0010␉␉/* Command Completed */␊ |
587 | #define PCI_EXP_SLTSTA_MRL_ST␉␉␉␉0x0020␉␉/* MRL Sensor State */␊ |
588 | #define PCI_EXP_SLTSTA_PRES␉␉␉␉␉0x0040␉␉/* Presence Detect State */␊ |
589 | #define PCI_EXP_SLTSTA_INTERLOCK␉␉␉0x0080␉␉/* Electromechanical Interlock Status */␊ |
590 | #define PCI_EXP_SLTSTA_LLCHG␉␉␉␉0x0100␉␉/* Data Link Layer State Changed */␊ |
591 | #define PCI_EXP_RTCTL␉␉␉␉␉␉0x1c␉␉/* Root Control */␊ |
592 | #define PCI_EXP_RTCTL_SECEE␉␉␉␉␉0x0001␉␉/* System Error on Correctable Error */␊ |
593 | #define PCI_EXP_RTCTL_SENFEE␉␉␉␉0x0002␉␉/* System Error on Non-Fatal Error */␊ |
594 | #define PCI_EXP_RTCTL_SEFEE␉␉␉␉␉0x0004␉␉/* System Error on Fatal Error */␊ |
595 | #define PCI_EXP_RTCTL_PMEIE␉␉␉␉␉0x0008␉␉/* PME Interrupt Enable */␊ |
596 | #define PCI_EXP_RTCTL_CRSVIS␉␉␉␉0x0010␉␉/* Configuration Request Retry Status Visible to SW */␊ |
597 | #define PCI_EXP_RTCAP␉␉␉␉␉␉0x1e␉␉/* Root Capabilities */␊ |
598 | #define PCI_EXP_RTCAP_CRSVIS␉␉␉␉0x0010␉␉/* Configuration Request Retry Status Visible to SW */␊ |
599 | #define PCI_EXP_RTSTA␉␉␉␉␉␉0x20␉␉/* Root Status */␊ |
600 | #define PCI_EXP_RTSTA_PME_REQID␉␉␉␉0x0000ffff␉/* PME Requester ID */␊ |
601 | #define PCI_EXP_RTSTA_PME_STATUS␉␉␉0x00010000␉/* PME Status */␊ |
602 | #define PCI_EXP_RTSTA_PME_PENDING␉␉␉0x00020000␉/* PME is Pending */␊ |
603 | #define PCI_EXP_DEVCAP2␉␉␉␉␉␉0x24␉␉/* Device capabilities 2 */␊ |
604 | #define PCI_EXP_DEVCTL2␉␉␉␉␉␉0x28␉␉/* Device Control */␊ |
605 | #define PCI_EXP_DEV2_TIMEOUT_RANGE(x)␉␉((x) & 0xf) /* Completion Timeout Ranges Supported */␊ |
606 | #define PCI_EXP_DEV2_TIMEOUT_VALUE(x)␉␉((x) & 0xf) /* Completion Timeout Value */␊ |
607 | #define PCI_EXP_DEV2_TIMEOUT_DIS␉␉␉0x0010␉␉/* Completion Timeout Disable Supported */␊ |
608 | #define PCI_EXP_DEV2_ARI␉␉␉␉␉0x0020␉␉/* ARI Forwarding */␊ |
609 | #define PCI_EXP_DEVSTA2␉␉␉␉␉␉0x2a␉␉/* Device Status */␊ |
610 | #define PCI_EXP_LNKCAP2␉␉␉␉␉␉0x2c␉␉/* Link Capabilities */␊ |
611 | #define PCI_EXP_LNKCTL2␉␉␉␉␉␉0x30␉␉/* Link Control */␊ |
612 | #define PCI_EXP_LNKCTL2_SPEED(x)␉␉␉((x) & 0xf) /* Target Link Speed */␊ |
613 | #define PCI_EXP_LNKCTL2_CMPLNC␉␉␉␉0x0010␉␉/* Enter Compliance */␊ |
614 | #define PCI_EXP_LNKCTL2_SPEED_DIS␉␉␉0x0020␉␉/* Hardware Autonomous Speed Disable */␊ |
615 | #define PCI_EXP_LNKCTL2_DEEMPHASIS(x)␉␉(((x) >> 6) & 1) /* Selectable De-emphasis */␊ |
616 | #define PCI_EXP_LNKCTL2_MARGIN(x)␉␉␉(((x) >> 7) & 7) /* Transmit Margin */␊ |
617 | #define PCI_EXP_LNKCTL2_MOD_CMPLNC␉␉␉0x0400␉␉/* Enter Modified Compliance */␊ |
618 | #define PCI_EXP_LNKCTL2_CMPLNC_SOS␉␉␉0x0800␉␉/* Compliance SOS */␊ |
619 | #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x)␉(((x) >> 12) & 1) /* Compliance De-emphasis */␊ |
620 | #define PCI_EXP_LNKSTA2␉␉␉␉␉␉0x32␉␉/* Link Status */␊ |
621 | #define PCI_EXP_LINKSTA2_DEEMPHASIS(x)␉␉((x) & 1)␉/* Current De-emphasis Level */␊ |
622 | #define PCI_EXP_SLTCAP2␉␉␉␉␉␉0x34␉␉/* Slot Capabilities */␊ |
623 | #define PCI_EXP_SLTCTL2␉␉␉␉␉␉0x38␉␉/* Slot Control */␊ |
624 | #define PCI_EXP_SLTSTA2␉␉␉␉␉␉0x3a␉␉/* Slot Status */␊ |
625 | ␊ |
626 | /* MSI-X */␊ |
627 | #define PCI_MSIX_ENABLE␉␉␉␉␉␉0x8000␊ |
628 | #define PCI_MSIX_MASK␉␉␉␉␉␉0x4000␊ |
629 | #define PCI_MSIX_TABSIZE␉␉␉␉␉0x03ff␊ |
630 | #define PCI_MSIX_TABLE␉␉␉␉␉␉4␊ |
631 | #define PCI_MSIX_PBA␉␉␉␉␉␉8␊ |
632 | #define PCI_MSIX_BIR␉␉␉␉␉␉0x7␊ |
633 | ␊ |
634 | /* Subsystem vendor/device ID for PCI bridges */␊ |
635 | #define PCI_SSVID_VENDOR␉␉␉␉␉4␊ |
636 | #define PCI_SSVID_DEVICE␉␉␉␉␉6␊ |
637 | ␊ |
638 | /* Advanced Error Reporting */␊ |
639 | #define PCI_ERR_UNCOR_STATUS␉␉␉␉4␉␉␉/* Uncorrectable Error Status */␊ |
640 | #define PCI_ERR_UNC_TRAIN␉␉␉␉␉0x00000001␉/* Undefined in PCIe rev1.1 & 2.0 spec */␊ |
641 | #define PCI_ERR_UNC_DLP␉␉␉␉␉␉0x00000010␉/* Data Link Protocol */␊ |
642 | #define PCI_ERR_UNC_SDES␉␉␉␉␉0x00000020␉/* Surprise Down Error */␊ |
643 | #define PCI_ERR_UNC_POISON_TLP␉␉␉␉0x00001000␉/* Poisoned TLP */␊ |
644 | #define PCI_ERR_UNC_FCP␉␉␉␉␉␉0x00002000␉/* Flow Control Protocol */␊ |
645 | #define PCI_ERR_UNC_COMP_TIME␉␉␉␉0x00004000␉/* Completion Timeout */␊ |
646 | #define PCI_ERR_UNC_COMP_ABORT␉␉␉␉0x00008000␉/* Completer Abort */␊ |
647 | #define PCI_ERR_UNC_UNX_COMP␉␉␉␉0x00010000␉/* Unexpected Completion */␊ |
648 | #define PCI_ERR_UNC_RX_OVER␉␉␉␉␉0x00020000␉/* Receiver Overflow */␊ |
649 | #define PCI_ERR_UNC_MALF_TLP␉␉␉␉0x00040000␉/* Malformed TLP */␊ |
650 | #define PCI_ERR_UNC_ECRC␉␉␉␉␉0x00080000␉/* ECRC Error Status */␊ |
651 | #define PCI_ERR_UNC_UNSUP␉␉␉␉␉0x00100000␉/* Unsupported Request */␊ |
652 | #define PCI_ERR_UNC_ACS_VIOL␉␉␉␉0x00200000␉/* ACS Violation */␊ |
653 | #define PCI_ERR_UNCOR_MASK␉␉␉␉␉8␉␉␉/* Uncorrectable Error Mask */␊ |
654 | /* Same bits as above */␊ |
655 | #define PCI_ERR_UNCOR_SEVER␉␉␉␉␉12␉␉␉/* Uncorrectable Error Severity */␊ |
656 | /* Same bits as above */␊ |
657 | #define PCI_ERR_COR_STATUS␉␉␉␉␉16␉␉␉/* Correctable Error Status */␊ |
658 | #define PCI_ERR_COR_RCVR␉␉␉␉␉0x00000001␉/* Receiver Error Status */␊ |
659 | #define PCI_ERR_COR_BAD_TLP␉␉␉␉␉0x00000040␉/* Bad TLP Status */␊ |
660 | #define PCI_ERR_COR_BAD_DLLP␉␉␉␉0x00000080␉/* Bad DLLP Status */␊ |
661 | #define PCI_ERR_COR_REP_ROLL␉␉␉␉0x00000100␉/* REPLAY_NUM Rollover */␊ |
662 | #define PCI_ERR_COR_REP_TIMER␉␉␉␉0x00001000␉/* Replay Timer Timeout */␊ |
663 | #define PCI_ERR_COR_REP_ANFE␉␉␉␉0x00002000␉/* Advisory Non-Fatal Error */␊ |
664 | #define PCI_ERR_COR_MASK␉␉␉␉␉20␉␉␉/* Correctable Error Mask */␊ |
665 | /* Same bits as above */␊ |
666 | #define PCI_ERR_CAP␉␉␉␉␉␉␉24␉␉␉/* Advanced Error Capabilities */␊ |
667 | #define PCI_ERR_CAP_FEP(x)␉␉␉␉␉((x) & 31)␉/* First Error Pointer */␊ |
668 | #define PCI_ERR_CAP_ECRC_GENC␉␉␉␉0x00000020␉/* ECRC Generation Capable */␊ |
669 | #define PCI_ERR_CAP_ECRC_GENE␉␉␉␉0x00000040␉/* ECRC Generation Enable */␊ |
670 | #define PCI_ERR_CAP_ECRC_CHKC␉␉␉␉0x00000080␉/* ECRC Check Capable */␊ |
671 | #define PCI_ERR_CAP_ECRC_CHKE␉␉␉␉0x00000100␉/* ECRC Check Enable */␊ |
672 | #define PCI_ERR_HEADER_LOG␉␉␉␉␉28␉␉␉/* Header Log Register (16 bytes) */␊ |
673 | #define PCI_ERR_ROOT_COMMAND␉␉␉␉44␉␉␉/* Root Error Command */␊ |
674 | #define PCI_ERR_ROOT_STATUS␉␉␉␉␉48␊ |
675 | #define PCI_ERR_ROOT_COR_SRC␉␉␉␉52␊ |
676 | #define PCI_ERR_ROOT_SRC␉␉␉␉␉54␊ |
677 | ␊ |
678 | /* Virtual Channel */␊ |
679 | #define PCI_VC_PORT_REG1␉␉␉␉␉4␊ |
680 | #define PCI_VC_PORT_REG2␉␉␉␉␉8␊ |
681 | #define PCI_VC_PORT_CTRL␉␉␉␉␉12␊ |
682 | #define PCI_VC_PORT_STATUS␉␉␉␉␉14␊ |
683 | #define PCI_VC_RES_CAP␉␉␉␉␉␉16␊ |
684 | #define PCI_VC_RES_CTRL␉␉␉␉␉␉20␊ |
685 | #define PCI_VC_RES_STATUS␉␉␉␉␉26␊ |
686 | ␊ |
687 | /* Power Budgeting */␊ |
688 | #define PCI_PWR_DSR␉␉␉␉␉␉␉4␉␉␉␉␉/* Data Select Register */␊ |
689 | #define PCI_PWR_DATA␉␉␉␉␉␉8␉␉␉␉␉/* Data Register */␊ |
690 | #define PCI_PWR_DATA_BASE(x)␉␉␉␉((x) & 0xff)␉␉/* Base Power */␊ |
691 | #define PCI_PWR_DATA_SCALE(x)␉␉␉␉(((x) >> 8) & 3)␉/* Data Scale */␊ |
692 | #define PCI_PWR_DATA_PM_SUB(x)␉␉␉␉(((x) >> 10) & 7)␉/* PM Sub State */␊ |
693 | #define PCI_PWR_DATA_PM_STATE(x)␉␉␉(((x) >> 13) & 3)␉/* PM State */␊ |
694 | #define PCI_PWR_DATA_TYPE(x)␉␉␉␉(((x) >> 15) & 7)␉/* Type */␊ |
695 | #define PCI_PWR_DATA_RAIL(x)␉␉␉␉(((x) >> 18) & 7)␉/* Power Rail */␊ |
696 | #define PCI_PWR_CAP␉␉␉␉␉␉␉12␉␉␉␉␉/* Capability */␊ |
697 | #define PCI_PWR_CAP_BUDGET(x)␉␉␉␉((x) & 1)␉␉␉/* Included in system budget */␊ |
698 | ␊ |
699 | /* Access Control Services */␊ |
700 | #define PCI_ACS_CAP␉␉␉␉␉␉␉0x04␉␉/* ACS Capability Register */␊ |
701 | #define PCI_ACS_CAP_VALID␉␉␉␉␉0x0001␉␉/* ACS Source Validation */␊ |
702 | #define PCI_ACS_CAP_BLOCK␉␉␉␉␉0x0002␉␉/* ACS Translation Blocking */␊ |
703 | #define PCI_ACS_CAP_REQ_RED␉␉␉␉␉0x0004␉␉/* ACS P2P Request Redirect */␊ |
704 | #define PCI_ACS_CAP_CMPLT_RED␉␉␉␉0x0008␉␉/* ACS P2P Completion Redirect */␊ |
705 | #define PCI_ACS_CAP_FORWARD␉␉␉␉␉0x0010␉␉/* ACS Upstream Forwarding */␊ |
706 | #define PCI_ACS_CAP_EGRESS␉␉␉␉␉0x0020␉␉/* ACS P2P Egress Control */␊ |
707 | #define PCI_ACS_CAP_TRANS␉␉␉␉␉0x0040␉␉/* ACS Direct Translated P2P */␊ |
708 | #define PCI_ACS_CAP_VECTOR(x)␉␉␉␉(((x) >> 8) & 0xff) /* Egress Control Vector Size */␊ |
709 | #define PCI_ACS_CTRL␉␉␉␉␉␉0x06␉␉/* ACS Control Register */␊ |
710 | #define PCI_ACS_CTRL_VALID␉␉␉␉␉0x0001␉␉/* ACS Source Validation Enable */␊ |
711 | #define PCI_ACS_CTRL_BLOCK␉␉␉␉␉0x0002␉␉/* ACS Translation Blocking Enable */␊ |
712 | #define PCI_ACS_CTRL_REQ_RED␉␉␉␉0x0004␉␉/* ACS P2P Request Redirect Enable */␊ |
713 | #define PCI_ACS_CTRL_CMPLT_RED␉␉␉␉0x0008␉␉/* ACS P2P Completion Redirect Enable */␊ |
714 | #define PCI_ACS_CTRL_FORWARD␉␉␉␉0x0010␉␉/* ACS Upstream Forwarding Enable */␊ |
715 | #define PCI_ACS_CTRL_EGRESS␉␉␉␉␉0x0020␉␉/* ACS P2P Egress Control Enable */␊ |
716 | #define PCI_ACS_CTRL_TRANS␉␉␉␉␉0x0040␉␉/* ACS Direct Translated P2P Enable */␊ |
717 | #define PCI_ACS_EGRESS_CTRL␉␉␉␉␉0x08␉␉/* Egress Control Vector */␊ |
718 | ␊ |
719 | /* Alternative Routing-ID Interpretation */␊ |
720 | #define PCI_ARI_CAP␉␉␉␉␉␉␉0x04␉␉/* ARI Capability Register */␊ |
721 | #define PCI_ARI_CAP_MFVC␉␉␉␉␉0x0001␉␉/* MFVC Function Groups Capability */␊ |
722 | #define PCI_ARI_CAP_ACS␉␉␉␉␉␉0x0002␉␉/* ACS Function Groups Capability */␊ |
723 | #define PCI_ARI_CAP_NFN(x)␉␉␉␉␉(((x) >> 8) & 0xff) /* Next Function Number */␊ |
724 | #define PCI_ARI_CTRL␉␉␉␉␉␉0x06␉␉/* ARI Control Register */␊ |
725 | #define PCI_ARI_CTRL_MFVC␉␉␉␉␉0x0001␉␉/* MFVC Function Groups Enable */␊ |
726 | #define PCI_ARI_CTRL_ACS␉␉␉␉␉0x0002␉␉/* ACS Function Groups Enable */␊ |
727 | #define PCI_ARI_CTRL_FG(x)␉␉␉␉␉(((x) >> 4) & 7) /* Function Group */␊ |
728 | ␊ |
729 | /* Address Translation Service */␊ |
730 | #define PCI_ATS_CAP␉␉␉␉␉␉␉0x04␉␉ /* ATS Capability Register */␊ |
731 | #define PCI_ATS_CAP_IQD(x)␉␉␉␉␉((x) & 0x1f) /* Invalidate Queue Depth */␊ |
732 | #define PCI_ATS_CTRL␉␉␉␉␉␉0x06␉␉ /* ATS Control Register */␊ |
733 | #define PCI_ATS_CTRL_STU(x)␉␉␉␉␉((x) & 0x1f) /* Smallest Translation Unit */␊ |
734 | #define PCI_ATS_CTRL_ENABLE␉␉␉␉␉0x8000␉␉ /* ATS Enable */␊ |
735 | ␊ |
736 | /* Single Root I/O Virtualization */␊ |
737 | #define PCI_IOV_CAP␉␉␉␉␉␉␉0x04␉␉/* SR-IOV Capability Register */␊ |
738 | #define PCI_IOV_CAP_VFM␉␉␉␉␉␉0x00000001␉/* VF Migration Capable */␊ |
739 | #define PCI_IOV_CAP_IMN(x)␉␉␉␉␉((x) >> 21) /* VF Migration Interrupt Message Number */␊ |
740 | #define PCI_IOV_CTRL␉␉␉␉␉␉0x08␉␉/* SR-IOV Control Register */␊ |
741 | #define PCI_IOV_CTRL_VFE␉␉␉␉␉0x0001␉␉/* VF Enable */␊ |
742 | #define PCI_IOV_CTRL_VFME␉␉␉␉␉0x0002␉␉/* VF Migration Enable */␊ |
743 | #define PCI_IOV_CTRL_VFMIE␉␉␉␉␉0x0004␉␉/* VF Migration Interrupt Enable */␊ |
744 | #define PCI_IOV_CTRL_MSE␉␉␉␉␉0x0008␉␉/* VF MSE */␊ |
745 | #define PCI_IOV_CTRL_ARI␉␉␉␉␉0x0010␉␉/* ARI Capable Hierarchy */␊ |
746 | #define PCI_IOV_STATUS␉␉␉␉␉␉0x0a␉␉/* SR-IOV Status Register */␊ |
747 | #define PCI_IOV_STATUS_MS␉␉␉␉␉0x0001␉␉/* VF Migration Status */␊ |
748 | #define PCI_IOV_INITIALVF␉␉␉␉␉0x0c␉␉/* Number of VFs that are initially associated */␊ |
749 | #define PCI_IOV_TOTALVF␉␉␉␉␉␉0x0e␉␉/* Maximum number of VFs that could be associated */␊ |
750 | #define PCI_IOV_NUMVF␉␉␉␉␉␉0x10␉␉/* Number of VFs that are available */␊ |
751 | #define PCI_IOV_FDL␉␉␉␉␉␉␉0x12␉␉/* Function Dependency Link */␊ |
752 | #define PCI_IOV_OFFSET␉␉␉␉␉␉0x14␉␉/* First VF Offset */␊ |
753 | #define PCI_IOV_STRIDE␉␉␉␉␉␉0x16␉␉/* Routing ID offset from one VF to the next one */␊ |
754 | #define PCI_IOV_DID␉␉␉␉␉␉␉0x1a␉␉/* VF Device ID */␊ |
755 | #define PCI_IOV_SUPPS␉␉␉␉␉␉0x1c␉␉/* Supported Page Sizes */␊ |
756 | #define PCI_IOV_SYSPS␉␉␉␉␉␉0x20␉␉/* System Page Size */␊ |
757 | #define PCI_IOV_BAR_BASE␉␉␉␉␉0x24␉␉/* VF BAR0, VF BAR1, ... VF BAR5 */␊ |
758 | #define PCI_IOV_NUM_BAR␉␉␉␉␉␉6␉␉␉/* Number of VF BARs */␊ |
759 | #define PCI_IOV_MSAO␉␉␉␉␉␉0x3c␉␉/* VF Migration State Array Offset */␊ |
760 | #define PCI_IOV_MSA_BIR(x)␉␉␉␉␉((x) & 7)␉/* VF Migration State BIR */␊ |
761 | #define PCI_IOV_MSA_OFFSET(x)␉␉␉␉((x) & 0xfffffff8) /* VF Migration State Offset */␊ |
762 | ␊ |
763 | /*␊ |
764 | * The PCI interface treats multi-function devices as independent␊ |
765 | * devices. The slot/function address of each device is encoded␊ |
766 | * in a single byte as follows:␊ |
767 | *␊ |
768 | *␉7:3 = slot␊ |
769 | *␉2:0 = function␊ |
770 | */␊ |
771 | #define PCI_DEVFN(slot,func)␉␉␉␉␉((((slot) & 0x1f) << 3) | ((func) & 0x07))␊ |
772 | #define PCI_SLOT(devfn)␉␉␉␉␉␉(((devfn) >> 3) & 0x1f)␊ |
773 | #define PCI_FUNC(devfn)␉␉␉␉␉␉((devfn) & 0x07)␊ |
774 | ␊ |
775 | /* Device classes and subclasses */␊ |
776 | #define PCI_CLASS_NOT_DEFINED␉␉␉␉␉0x0000␊ |
777 | #define PCI_CLASS_NOT_DEFINED_VGA␉␉␉␉0x0001␊ |
778 | ␊ |
779 | // values for the class_sub field for class_base = 0x00 (Device was built prior definition of the class code field)␊ |
780 | ␊ |
781 | // values for the class_sub field for class_base = 0x01 (Mass Storage Controller)␊ |
782 | #define PCI_BASE_CLASS_STORAGE␉␉␉␉␉0x01␊ |
783 | #define PCI_CLASS_STORAGE_SCSI␉␉␉␉␉0x0100␊ |
784 | #define PCI_CLASS_STORAGE_IDE␉␉␉␉␉0x0101␊ |
785 | #define PCI_CLASS_STORAGE_FLOPPY␉␉␉␉0x0102␊ |
786 | #define PCI_CLASS_STORAGE_IPI␉␉␉␉␉0x0103␊ |
787 | #define PCI_CLASS_STORAGE_RAID␉␉␉␉␉0x0104␊ |
788 | #define PCI_CLASS_STORAGE_ATA␉␉␉␉␉0x0105␊ |
789 | #define PCI_CLASS_STORAGE_SATA␉␉␉␉␉0x0106␊ |
790 | #define PCI_CLASS_STORAGE_SATA_AHCI␉␉␉␉0x010601␊ |
791 | #define PCI_CLASS_STORAGE_SAS␉␉␉␉␉0x0107␊ |
792 | #define PCI_CLASS_STORAGE_OTHER␉␉␉␉␉0x0180␊ |
793 | ␊ |
794 | // values for the class_sub field for class_base = 0x02 (Network Controller)␊ |
795 | #define PCI_BASE_CLASS_NETWORK␉␉␉␉␉0x02␊ |
796 | #define PCI_CLASS_NETWORK_ETHERNET␉␉␉␉0x0200␊ |
797 | #define PCI_CLASS_NETWORK_TOKEN_RING␉␉␉0x0201␊ |
798 | #define PCI_CLASS_NETWORK_FDDI␉␉␉␉␉0x0202␊ |
799 | #define PCI_CLASS_NETWORK_ATM␉␉␉␉␉0x0203␊ |
800 | #define PCI_CLASS_NETWORK_ISDN␉␉␉␉␉0x0204␊ |
801 | #define PCI_CLASS_NETWORK_OTHER␉␉␉␉␉0x0280␊ |
802 | ␊ |
803 | // values for the class_sub field for class_base = 0x03 (Display Controller)␊ |
804 | #define PCI_BASE_CLASS_DISPLAY␉␉␉␉␉0x03␊ |
805 | #define PCI_CLASS_DISPLAY_VGA␉␉␉␉␉0x0300␊ |
806 | #define PCI_CLASS_DISPLAY_XGA␉␉␉␉␉0x0301␊ |
807 | #define PCI_CLASS_DISPLAY_3D␉␉␉␉␉0x0302␊ |
808 | #define PCI_CLASS_DISPLAY_OTHER␉␉␉␉␉0x0380␊ |
809 | ␊ |
810 | // values for the class_sub field for class_base = 0x04 (Multimedia Controller)␊ |
811 | #define PCI_BASE_CLASS_MULTIMEDIA␉␉␉␉0x04␊ |
812 | #define PCI_CLASS_MULTIMEDIA_VIDEO␉␉␉␉0x0400 /* video */␊ |
813 | #define PCI_CLASS_MULTIMEDIA_AUDIO␉␉␉␉0x0401 /* audio */␊ |
814 | #define PCI_CLASS_MULTIMEDIA_PHONE␉␉␉␉0x0402␊ |
815 | #define PCI_CLASS_MULTIMEDIA_AUDIO_DEV␉␉␉␉0x0403 /* HD audio */␊ |
816 | #define PCI_CLASS_MULTIMEDIA_OTHER␉␉␉␉0x0480␊ |
817 | ␊ |
818 | // values for the class_sub field for class_base = 0x05 (Memory Controller)␊ |
819 | #define PCI_BASE_CLASS_MEMORY␉␉␉␉␉0x05␊ |
820 | #define PCI_CLASS_MEMORY_RAM␉␉␉␉␉0x0500␊ |
821 | #define PCI_CLASS_MEMORY_FLASH␉␉␉␉␉0x0501␊ |
822 | #define PCI_CLASS_MEMORY_OTHER␉␉␉␉␉0x0580␊ |
823 | ␊ |
824 | // values for the class_sub field for class_base = 0x06 (Bridge Device)␊ |
825 | #define PCI_BASE_CLASS_BRIDGE␉␉␉␉␉0x06␊ |
826 | #define PCI_CLASS_BRIDGE_HOST␉␉␉␉␉0x0600␊ |
827 | #define PCI_CLASS_BRIDGE_ISA␉␉␉␉␉0x0601␊ |
828 | #define PCI_CLASS_BRIDGE_EISA␉␉␉␉␉0x0602␊ |
829 | #define PCI_CLASS_BRIDGE_MC␉␉␉␉␉0x0603␊ |
830 | #define PCI_CLASS_BRIDGE_PCI␉␉␉␉␉0x0604␊ |
831 | #define PCI_CLASS_BRIDGE_PCMCIA␉␉␉␉␉0x0605␊ |
832 | #define PCI_CLASS_BRIDGE_NUBUS␉␉␉␉␉0x0606␊ |
833 | #define PCI_CLASS_BRIDGE_CARDBUS␉␉␉␉0x0607␊ |
834 | #define PCI_CLASS_BRIDGE_RACEWAY␉␉␉␉0x0608␊ |
835 | #define PCI_CLASS_BRIDGE_PCI_SEMI␉␉␉␉0x0609␊ |
836 | #define PCI_CLASS_BRIDGE_IB_TO_PCI␉␉␉␉0x060a␊ |
837 | #define PCI_CLASS_BRIDGE_OTHER␉␉␉␉␉0x0680␊ |
838 | ␊ |
839 | // values for the class_sub field for class_base = 0x07 (Simple Communications Controllers)␊ |
840 | #define PCI_BASE_CLASS_COMMUNICATION␉␉␉␉0x07␊ |
841 | #define PCI_CLASS_COMMUNICATION_SERIAL␉␉␉␉0x0700␊ |
842 | #define PCI_CLASS_COMMUNICATION_PARALLEL␉␉␉0x0701␊ |
843 | #define PCI_CLASS_COMMUNICATION_MSERIAL␉␉␉␉0x0702␊ |
844 | #define PCI_CLASS_COMMUNICATION_MODEM␉␉␉␉0x0703␊ |
845 | #define PCI_CLASS_COMMUNICATION_OTHER␉␉␉␉0x0780␊ |
846 | ␊ |
847 | // values for the class_sub field for class_base = 0x08 (Base System Peripherals)␊ |
848 | #define PCI_BASE_CLASS_SYSTEM␉␉␉␉␉0x08␊ |
849 | #define PCI_CLASS_SYSTEM_PIC␉␉␉␉␉0x0800␊ |
850 | #define PCI_CLASS_SYSTEM_PIC_IOAPIC␉␉␉␉0x080010␊ |
851 | #define PCI_CLASS_SYSTEM_PIC_IOXAPIC␉␉␉␉0x080020 // I/O APIC interrupt controller , 32 bye none-prefectable memory.␊ |
852 | #define PCI_CLASS_SYSTEM_DMA␉␉␉␉␉0x0801␊ |
853 | #define PCI_CLASS_SYSTEM_TIMER␉␉␉␉␉0x0802␊ |
854 | #define PCI_CLASS_SYSTEM_RTC␉␉␉␉␉0x0803␊ |
855 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG␉␉␉␉0x0804 // HotPlug Controller␊ |
856 | #define PCI_CLASS_SYSTEM_SDHCI␉␉␉␉␉0x0805␊ |
857 | #define PCI_CLASS_SYSTEM_OTHER␉␉␉␉␉0x0880␊ |
858 | ␊ |
859 | // values for the class_sub field for class_base = 0x09 (Input Devices)␊ |
860 | #define PCI_BASE_CLASS_INPUT␉␉␉␉␉0x09␊ |
861 | #define PCI_CLASS_INPUT_KEYBOARD␉␉␉␉0x0900␊ |
862 | #define PCI_CLASS_INPUT_PEN␉␉␉␉␉0x0901␊ |
863 | #define PCI_CLASS_INPUT_MOUSE␉␉␉␉␉0x0902␊ |
864 | #define PCI_CLASS_INPUT_SCANNER␉␉␉␉␉0x0903␊ |
865 | #define PCI_CLASS_INPUT_GAMEPORT␉␉␉␉0x0904␊ |
866 | #define PCI_CLASS_INPUT_OTHER␉␉␉␉␉0x0980␊ |
867 | ␊ |
868 | // values for the class_sub field for class_base = 0x0a (Docking Stations)␊ |
869 | #define PCI_BASE_CLASS_DOCKING␉␉␉␉␉0x0a␊ |
870 | #define PCI_CLASS_DOCKING_GENERIC␉␉␉␉0x0a00␊ |
871 | #define PCI_CLASS_DOCKING_OTHER␉␉␉␉␉0x0a80␊ |
872 | ␊ |
873 | // values for the class_sub field for class_base = 0x0b (processor)␊ |
874 | #define PCI_BASE_CLASS_PROCESSOR␉␉␉␉0x0b␊ |
875 | #define PCI_CLASS_PROCESSOR_386␉␉␉␉␉0x0b00␊ |
876 | #define PCI_CLASS_PROCESSOR_486␉␉␉␉␉0x0b01␊ |
877 | #define PCI_CLASS_PROCESSOR_PENTIUM␉␉␉␉0x0b02␊ |
878 | #define PCI_CLASS_PROCESSOR_ALPHA␉␉␉␉0x0b10␊ |
879 | #define PCI_CLASS_PROCESSOR_POWERPC␉␉␉␉0x0b20␊ |
880 | #define PCI_CLASS_PROCESSOR_MIPS␉␉␉␉0x0b30␊ |
881 | #define PCI_CLASS_PROCESSOR_CO␉␉␉␉␉0x0b40 // Co-Processor␊ |
882 | ␊ |
883 | // values for the class_sub field for class_base = 0x0c (serial bus controller)␊ |
884 | #define PCI_BASE_CLASS_SERIAL␉␉␉␉␉0x0c␊ |
885 | #define PCI_CLASS_SERIAL_FIREWIRE␉␉␉␉0x0c00 /* FireWire (IEEE 1394) */␊ |
886 | #define PCI_CLASS_SERIAL_FIREWIRE_OHCI␉␉␉␉0x0c10␊ |
887 | #define PCI_CLASS_SERIAL_ACCESS␉␉␉␉␉0x0c01␊ |
888 | #define PCI_CLASS_SERIAL_SSA␉␉␉␉␉0x0c02␊ |
889 | #define PCI_CLASS_SERIAL_USB␉␉␉␉␉0x0c03 /* Universal Serial Bus */␊ |
890 | #define PCI_IF_UHCI␉␉␉␉␉0x00 /* Universal Host Controller Interface */␊ |
891 | #define PCI_IF_OHCI␉␉␉␉␉0x10 /* Open Host Controller Interface */␊ |
892 | #define PCI_IF_EHCI␉␉␉␉␉0x20 /* Enhanced Host Controller Interface */␊ |
893 | #define PCI_IF_XHCI␉␉␉␉␉0x30 /* Extensible Host Controller Interface */␊ |
894 | #define PCI_CLASS_SERIAL_FIBER␉␉␉␉␉0x0c04␊ |
895 | #define PCI_CLASS_SERIAL_SMBUS␉␉␉␉␉0x0c05␊ |
896 | #define PCI_CLASS_SERIAL_INFINIBAND␉␉␉␉0x0c06␊ |
897 | ␊ |
898 | // values for the class_sub field for class_base = 0x0d (Wireless Controller)␊ |
899 | #define PCI_BASE_CLASS_WIRELESS␉␉␉␉␉0x0d␊ |
900 | #define PCI_CLASS_WIRELESS_IRDA␉␉␉␉␉0x0d00␊ |
901 | #define PCI_CLASS_WIRELESS_IR␉␉␉␉␉0x0d01␊ |
902 | #define PCI_CLASS_WIRELESS_RF␉␉␉␉␉0x0d10␊ |
903 | #define PCI_CLASS_WIRELESS_BLUETOOTH␉␉␉0x0d11␊ |
904 | #define PCI_CLASS_WIRELESS_BROADBAND␉␉␉0x0d12␊ |
905 | #define PCI_CLASS_WIRELESS_80211A␉␉␉␉0x0d20␊ |
906 | #define PCI_CLASS_WIRELESS_80211B␉␉␉␉0x0d21␊ |
907 | #define PCI_CLASS_WIRELESS_WHCI␉␉␉␉␉0x0d1010␊ |
908 | #define PCI_CLASS_WIRELESS_OTHER␉␉␉␉0x80␊ |
909 | ␊ |
910 | // values for the class_sub field for class_base = 0x0e (Intelligent I/O Controller)␊ |
911 | #define PCI_BASE_CLASS_INTELLIGENT␉␉␉␉0x0e␊ |
912 | #define PCI_CLASS_INTELLIGENT_I2O␉␉␉␉0x0e00␊ |
913 | ␊ |
914 | // values for the class_sub field for class_base = 0x0f (Satellite Communication Controller)␊ |
915 | #define PCI_BASE_CLASS_SATELLITE␉␉␉␉0x0f␊ |
916 | #define PCI_CLASS_SATELLITE_TV␉␉␉␉␉0x0f00␊ |
917 | #define PCI_CLASS_SATELLITE_AUDIO␉␉␉␉0x0f01␊ |
918 | #define PCI_CLASS_SATELLITE_VOICE␉␉␉␉0x0f03␊ |
919 | #define PCI_CLASS_SATELLITE_DATA␉␉␉␉0x0f04␊ |
920 | ␊ |
921 | // values for the class_sub field for class_base = 0x10 (Encryption and decryption controller)␊ |
922 | #define PCI_BASE_CLASS_CRYPT␉␉␉␉␉0x10␊ |
923 | #define PCI_CLASS_CRYPT_NETWORK␉␉␉␉␉0x1000␊ |
924 | #define PCI_CLASS_CRYPT_ENTERTAINMENT␉␉␉␉0x1010␊ |
925 | #define PCI_CLASS_CRYPT_OTHER␉␉␉␉␉0x1080␊ |
926 | // values for the class_sub field for class_base = 0x12 (Data Acquisition and Signal Processing Controllers)␊ |
927 | #define PCI_BASE_CLASS_SIGNAL␉␉␉␉␉0x11␊ |
928 | #define PCI_CLASS_SIGNAL_DPIO␉␉␉␉␉0x1100␊ |
929 | #define PCI_CLASS_SIGNAL_PERF_CTR␉␉␉␉0x1101␊ |
930 | #define PCI_CLASS_SIGNAL_SYNCHRONIZER␉␉␉␉0x1110␊ |
931 | #define PCI_CLASS_SIGNAL_OTHER␉␉␉␉␉0x1180␊ |
932 | ␊ |
933 | // values for the class_sub field for class_base = 0xff (Device does not fit any defined class)␊ |
934 | #define PCI_CLASS_OTHERS 0xff␊ |
935 | ␊ |
936 | /* Several ID's we need in the library */␊ |
937 | #define PCI_VENDOR_ID_APPLE␉␉␉␉␉0x106b␊ |
938 | #define PCI_VENDOR_ID_AMD␉␉␉␉␉0x1022␊ |
939 | #define PCI_VENDOR_ID_ATI␉␉␉␉␉0x1002␊ |
940 | #define PCI_VENDOR_ID_INTEL␉␉␉␉␉0x8086␊ |
941 | #define PCI_VENDOR_ID_NVIDIA␉␉␉␉0x10de␊ |
942 | #define PCI_VENDOR_ID_REALTEK␉␉␉␉0x10ec␊ |
943 | #define PCI_VENDOR_ID_TEXAS_INSTRUMENTS ␉0x104c␊ |
944 | #define PCI_VENDOR_ID_VIA␉␉␉␉␉0x1106␊ |
945 | ␊ |
946 | #endif /* !__LIBSAIO_PCI_H */␊ |
947 | |