1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #ifndef __LIBSAIO_CPU_H␊ |
7 | #define __LIBSAIO_CPU_H␊ |
8 | ␊ |
9 | #include "platform.h"␊ |
10 | ␊ |
11 | extern void scan_cpu(PlatformInfo_t *);␊ |
12 | ␊ |
13 | #define bit(n)␉␉␉␉(1ULL << (n))␊ |
14 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
15 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
16 | ␊ |
17 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Type"␊ |
18 | ␊ |
19 | /*␊ |
20 | * The CPUID_FEATURE_XXX values define 64-bit values␊ |
21 | * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
22 | */␊ |
23 | #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */␊ |
24 | #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */␊ |
25 | #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */␊ |
26 | #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */␊ |
27 | #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */␊ |
28 | #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */␊ |
29 | #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */␊ |
30 | #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */␊ |
31 | #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */␊ |
32 | #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */␊ |
33 | #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */␊ |
34 | #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */␊ |
35 | #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */␊ |
36 | #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */␊ |
37 | #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */␊ |
38 | #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */␊ |
39 | #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */␊ |
40 | #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */␊ |
41 | #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */␊ |
42 | #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */␊ |
43 | #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */␊ |
44 | #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */␊ |
45 | #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */␊ |
46 | #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */␊ |
47 | #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */␊ |
48 | #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */␊ |
49 | #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */␊ |
50 | #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */␊ |
51 | #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */␊ |
52 | ␊ |
53 | #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */␊ |
54 | #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */␊ |
55 | #define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */␊ |
56 | #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */␊ |
57 | #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */␊ |
58 | #define CPUID_FEATURE_VMX _HBit(5) /* VMX */␊ |
59 | #define CPUID_FEATURE_SMX _HBit(6) /* SMX */␊ |
60 | #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */␊ |
61 | #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */␊ |
62 | #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */␊ |
63 | #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */␊ |
64 | #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊ |
65 | #define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */␊ |
66 | #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */␊ |
67 | #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */␊ |
68 | #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */␊ |
69 | ␊ |
70 | #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊ |
71 | #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */␊ |
72 | #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */␊ |
73 | #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */␊ |
74 | #define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */␊ |
75 | #define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */␊ |
76 | #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */␊ |
77 | #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊ |
78 | #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */␊ |
79 | #define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */␊ |
80 | #define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */␊ |
81 | #define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊ |
82 | #define CPUID_FEATURE_F16C␉_HBit(29) /* Float16 convert instructions */␊ |
83 | #define CPUID_FEATURE_RDRAND␉_HBit(30) /* RDRAND instruction */␊ |
84 | #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */␊ |
85 | ␊ |
86 | /*␊ |
87 | * Leaf 7, subleaf 0 additional features.␊ |
88 | * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
89 | */␊ |
90 | #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)␉/* FS/GS base read/write */␊ |
91 | #define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)␉/* TSC thread offset */␊ |
92 | #define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
93 | #define CPUID_LEAF7_FEATURE_HLE _Bit(4)␉/* Hardware Lock Elision*/␊ |
94 | #define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)␉/* AVX2 Instructions */␊ |
95 | #define CPUID_LEAF7_FEATURE_SMEP _Bit(7)␉/* Supervisor Mode Execute Protect */␊ |
96 | #define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
97 | #define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)␉/* ENhanced Fast STRinG copy */␊ |
98 | #define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)␉/* INVPCID intruction, TDB */␊ |
99 | #define CPUID_LEAF7_FEATURE_RTM _Bit(11)␉/* TBD */␊ |
100 | ␊ |
101 | /*␊ |
102 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
103 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
104 | */␊ |
105 | #define CPUID_EXTFEATURE_SYSCALL _Bit(11)␉/* SYSCALL/sysret */␊ |
106 | #define CPUID_EXTFEATURE_XD␉ _Bit(20)␉/* eXecute Disable */␊ |
107 | ␊ |
108 | #define CPUID_EXTFEATURE_1GBPAGE _Bit(26)␉/* 1GB pages */␊ |
109 | #define CPUID_EXTFEATURE_RDTSCP␉ _Bit(27)␉/* RDTSCP */␊ |
110 | #define CPUID_EXTFEATURE_EM64T␉ _Bit(29)␉/* Extended Mem 64 Technology */␊ |
111 | ␊ |
112 | #define CPUID_EXTFEATURE_LAHF␉ _HBit(0)␉/* LAFH/SAHF instructions */␊ |
113 | ␊ |
114 | /*␊ |
115 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
116 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
117 | */␊ |
118 | #define CPUID_EXTFEATURE_TSCI _Bit(8)␉/* TSC Invariant */␊ |
119 | ␊ |
120 | #define␉CPUID_CACHE_SIZE␉16␉/* Number of descriptor values */␊ |
121 | ␊ |
122 | #define CPUID_MWAIT_EXTENSION␉ _Bit(0)␉/* enumeration of WMAIT extensions */␊ |
123 | #define CPUID_MWAIT_BREAK␉ _Bit(1)␉/* interrupts are break events␉ */␊ |
124 | ␊ |
125 | //-- processor type -> p_type:␊ |
126 | #define PT_OEM␉0x00␉// Intel Original OEM Processor;␊ |
127 | #define PT_OD␉0x01 ␉// Intel Over Drive Processor;␊ |
128 | #define PT_DUAL␉0x02␉// Intel Dual Processor;␊ |
129 | #define PT_RES␉0x03␉// Intel Reserved;␊ |
130 | ␊ |
131 | /* Known MSR registers */␊ |
132 | #define MSR_IA32_PLATFORM_ID 0x0017␊ |
133 | #define MSR_CORE_THREAD_COUNT 0x0035␉/* limited use - not for Penryn or older */␊ |
134 | #define IA32_TSC_ADJUST 0x003B␊ |
135 | #define MSR_IA32_BIOS_SIGN_ID 0x008B␉/* microcode version */␊ |
136 | #define MSR_FSB_FREQ 0x00CD␉/* limited use - not for i7 */␊ |
137 | #define␉MSR_PLATFORM_INFO 0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
138 | /* turbo for penryn */␊ |
139 | #define MSR_PKG_CST_CONFIG_CONTROL 0x00E2␉/* sandy and ivy */␊ |
140 | #define MSR_PMG_IO_CAPTURE_BASE 0x00E4␊ |
141 | #define IA32_MPERF 0x00E7␉/* TSC in C0 only */␊ |
142 | #define IA32_APERF 0x00E8␉/* actual clocks in C0 */␊ |
143 | #define MSR_IA32_EXT_CONFIG 0x00EE␉/* limited use - not for i7 */␊ |
144 | #define MSR_FLEX_RATIO 0x0194␉/* limited use - not for Penryn or older */␊ |
145 | ␉␉␉␉␉␉//see no value on most CPUs␊ |
146 | #define␉MSR_IA32_PERF_STATUS 0x0198␊ |
147 | #define MSR_IA32_PERF_CONTROL 0x0199␊ |
148 | #define MSR_IA32_CLOCK_MODULATION 0x019A␊ |
149 | #define MSR_THERMAL_STATUS 0x019C␊ |
150 | #define MSR_IA32_MISC_ENABLE 0x01A0␊ |
151 | #define MSR_THERMAL_TARGET 0x01A2␉ /* TjMax limited use - not for Penryn or older␉*/␊ |
152 | #define MSR_MISC_PWR_MGMT 0x01AA␊ |
153 | #define MSR_TURBO_RATIO_LIMIT 0x01AD␉ /* limited use - not for Penryn or older */␊ |
154 | ␊ |
155 | #define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊ |
156 | #define MSR_PACKAGE_THERM_STATUS␉0x01B1␊ |
157 | #define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊ |
158 | #define MSR_POWER_CTL␉␉␉␉0x01FC // MSR 000001FC 0000-0000-0004-005F␊ |
159 | ␊ |
160 | // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊ |
161 | #define MSR_RAPL_POWER_UNIT␉␉␉0x606 /* R/O */␊ |
162 | //MSR 00000606 0000-0000-000A-1003␊ |
163 | #define MSR_PKGC3_IRTL␉␉␉␉0x60A /* RW time limit to go C3 */␊ |
164 | // bit 15 = 1 -- the value valid for C-state PM␊ |
165 | #define MSR_PKGC6_IRTL␉␉␉␉0x60B /* RW time limit to go C6 */␊ |
166 | //MSR 0000060B 0000-0000-0000-8854␊ |
167 | //Valid + 010=1024ns + 0x54=84mks␊ |
168 | #define MSR_PKGC7_IRTL␉␉␉␉0x60C /* RW time limit to go C7 */␊ |
169 | //MSR 0000060C 0000-0000-0000-8854␊ |
170 | #define MSR_PKG_C2_RESIDENCY␉␉0x60D /* same as TSC but in C2 only */␊ |
171 | ␊ |
172 | #define MSR_PKG_RAPL_POWER_LIMIT␉0x610 //MSR 00000610 0000-A580-0000-8960␊ |
173 | #define MSR_PKG_ENERGY_STATUS␉␉0x611 //MSR 00000611 0000-0000-3212-A857␊ |
174 | #define MSR_PKG_POWER_INFO␉␉␉0x614 //MSR 00000614 0000-0000-01E0-02F8␊ |
175 | ␊ |
176 | //AMD␊ |
177 | #define K8_FIDVID_STATUS 0xC0010042␊ |
178 | #define K10_COFVID_LIMIT 0xC0010061␊ |
179 | #define K10_PSTATE_STATUS 0xC0010064␊ |
180 | #define K10_COFVID_STATUS 0xC0010071␊ |
181 | ␊ |
182 | #define MSR_AMD_MPERF 0x000000E7␊ |
183 | #define MSR_AMD_APERF 0x000000E8␊ |
184 | ␊ |
185 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
186 | ␊ |
187 | // DFE: This constant comes from older xnu:␊ |
188 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
189 | ␊ |
190 | // DFE: These two constants come from Linux except CLOCK_TICK_RATE replaced with CLKNUM␊ |
191 | #define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊ |
192 | #define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊ |
193 | ␊ |
194 | static inline uint64_t rdtsc64(void)␊ |
195 | {␊ |
196 | ␉uint64_t ret;␊ |
197 | ␉__asm__ volatile("rdtsc" : "=A" (ret));␊ |
198 | ␉return ret;␊ |
199 | }␊ |
200 | ␊ |
201 | static inline uint64_t rdmsr64(uint32_t msr)␊ |
202 | {␊ |
203 | uint64_t ret;␊ |
204 | __asm__ volatile("rdmsr" : "=A" (ret) : "c" (msr));␊ |
205 | return ret;␊ |
206 | }␊ |
207 | ␊ |
208 | static inline void wrmsr64(uint32_t msr, uint64_t val)␊ |
209 | {␊ |
210 | ␉__asm__ volatile("wrmsr" : : "c" (msr), "A" (val));␊ |
211 | }␊ |
212 | ␊ |
213 | static inline void intel_waitforsts(void) {␊ |
214 | ␉uint32_t inline_timeout = 100000;␊ |
215 | ␉while (rdmsr64(MSR_IA32_PERF_STATUS) & (1 << 21)) { if (!inline_timeout--) break; }␊ |
216 | }␊ |
217 | ␊ |
218 | static inline void do_cpuid(uint32_t selector, uint32_t *data)␊ |
219 | {␊ |
220 | ␉asm volatile ("cpuid"␊ |
221 | ␉␉␉␉ : "=a" (data[0]),␊ |
222 | ␉␉␉␉␉"=b" (data[1]),␊ |
223 | ␉␉␉␉␉"=c" (data[2]),␊ |
224 | ␉␉␉␉␉"=d" (data[3])␊ |
225 | ␉␉␉␉ : "a" (selector));␊ |
226 | }␊ |
227 | ␊ |
228 | static inline void do_cpuid2(uint32_t selector, uint32_t selector2, uint32_t *data)␊ |
229 | {␊ |
230 | ␉asm volatile ("cpuid"␊ |
231 | ␉␉␉␉ : "=a" (data[0]),␊ |
232 | ␉␉␉␉␉"=b" (data[1]),␊ |
233 | ␉␉␉␉␉"=c" (data[2]),␊ |
234 | ␉␉␉␉␉"=d" (data[3])␊ |
235 | ␉␉␉␉ : "a" (selector),␊ |
236 | ␉␉␉␉␉"c" (selector2));␊ |
237 | }␊ |
238 | ␊ |
239 | // DFE: enable_PIT2 and disable_PIT2 come from older xnu␊ |
240 | ␊ |
241 | /*␊ |
242 | * Enable or disable timer 2.␊ |
243 | * Port 0x61 controls timer 2:␊ |
244 | * bit 0 gates the clock,␊ |
245 | * bit 1 gates output to speaker.␊ |
246 | */␊ |
247 | static inline void enable_PIT2(void)␊ |
248 | {␊ |
249 | /* Enable gate, disable speaker */␊ |
250 | __asm__ volatile(␊ |
251 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
252 | ␉␉␉␉␉ " and $0xFC,%%al \n\t" /* & ~0x03 */␊ |
253 | ␉␉␉␉␉ " or $1,%%al \n\t"␊ |
254 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
255 | ␉␉␉␉␉ : : : "%al" );␊ |
256 | }␊ |
257 | ␊ |
258 | static inline void disable_PIT2(void)␊ |
259 | {␊ |
260 | /* Disable gate and output to speaker */␊ |
261 | __asm__ volatile(␊ |
262 | ␉␉␉␉␉ " inb $0x61,%%al \n\t"␊ |
263 | ␉␉␉␉␉ " and $0xFC,%%al \n\t"␉/* & ~0x03 */␊ |
264 | ␉␉␉␉␉ " outb %%al,$0x61 \n\t"␊ |
265 | ␉␉␉␉␉ : : : "%al" );␊ |
266 | }␊ |
267 | ␊ |
268 | // DFE: set_PIT2_mode0, poll_PIT2_gate, and measure_tsc_frequency are␊ |
269 | // roughly based on Linux code␊ |
270 | ␊ |
271 | /* Set the 8254 channel 2 to mode 0 with the specified value.␊ |
272 | In mode 0, the counter will initially set its gate low when the␊ |
273 | timer expires. For this to be useful, you ought to set it high␊ |
274 | before calling this function. The enable_PIT2 function does this.␊ |
275 | */␊ |
276 | static inline void set_PIT2_mode0(uint16_t value)␊ |
277 | {␊ |
278 | __asm__ volatile(␊ |
279 | ␉␉␉␉␉ " movb $0xB0,%%al \n\t"␊ |
280 | ␉␉␉␉␉ " outb␉%%al,$0x43␉\n\t"␊ |
281 | ␉␉␉␉␉ " movb␉%%dl,%%al␉\n\t"␊ |
282 | ␉␉␉␉␉ " outb␉%%al,$0x42␉\n\t"␊ |
283 | ␉␉␉␉␉ " movb␉%%dh,%%al␉\n\t"␊ |
284 | ␉␉␉␉␉ " outb␉%%al,$0x42"␊ |
285 | ␉␉␉␉␉ : : "d"(value) /*: no clobber */ );␊ |
286 | }␊ |
287 | ␊ |
288 | /* Returns the number of times the loop ran before the PIT2 signaled */␊ |
289 | static inline unsigned long poll_PIT2_gate(void)␊ |
290 | {␊ |
291 | unsigned long count = 0;␊ |
292 | unsigned char nmi_sc_val;␊ |
293 | do {␊ |
294 | ++count;␊ |
295 | __asm__ volatile(␊ |
296 | ␉␉␉␉␉␉ "inb␉$0x61,%0"␊ |
297 | ␉␉␉␉␉␉ : "=a"(nmi_sc_val) /*:*/ /* no input */ /*:*/ /* no clobber */);␊ |
298 | } while( (nmi_sc_val & 0x20) == 0);␊ |
299 | return count;␊ |
300 | }␊ |
301 | ␊ |
302 | inline static void␊ |
303 | set_PIT2(int value)␊ |
304 | {␊ |
305 | /*␊ |
306 | * First, tell the clock we are going to write 16 bits to the counter␊ |
307 | * and enable one-shot mode (command 0xB8 to port 0x43)␊ |
308 | * Then write the two bytes into the PIT2 clock register (port 0x42).␊ |
309 | * Loop until the value is "realized" in the clock,␊ |
310 | * this happens on the next tick.␊ |
311 | */␊ |
312 | asm volatile(␊ |
313 | " movb $0xB8,%%al \n\t"␊ |
314 | " outb %%al,$0x43 \n\t"␊ |
315 | " movb %%dl,%%al \n\t"␊ |
316 | " outb %%al,$0x42 \n\t"␊ |
317 | " movb %%dh,%%al \n\t"␊ |
318 | " outb %%al,$0x42 \n"␊ |
319 | "1: inb $0x42,%%al \n\t" ␊ |
320 | " inb $0x42,%%al \n\t"␊ |
321 | " cmp %%al,%%dh \n\t"␊ |
322 | " jne 1b"␊ |
323 | : : "d"(value) : "%al");␊ |
324 | }␊ |
325 | ␊ |
326 | ␊ |
327 | inline static uint64_t␊ |
328 | get_PIT2(unsigned int *value)␊ |
329 | {␊ |
330 | register uint64_t result;␊ |
331 | /*␊ |
332 | * This routine first latches the time (command 0x80 to port 0x43),␊ |
333 | * then gets the time stamp so we know how long the read will take later.␊ |
334 | * Read (from port 0x42) and return the current value of the timer.␊ |
335 | */␊ |
336 | #ifdef __i386__␊ |
337 | asm volatile(␊ |
338 | " xorl %%ecx,%%ecx \n\t"␊ |
339 | " movb $0x80,%%al \n\t"␊ |
340 | " outb %%al,$0x43 \n\t"␊ |
341 | " rdtsc \n\t"␊ |
342 | " pushl %%eax \n\t"␊ |
343 | " inb $0x42,%%al \n\t"␊ |
344 | " movb %%al,%%cl \n\t"␊ |
345 | " inb $0x42,%%al \n\t"␊ |
346 | " movb %%al,%%ch \n\t"␊ |
347 | " popl %%eax "␊ |
348 | : "=A"(result), "=c"(*value));␊ |
349 | #else /* __x86_64__ */␊ |
350 | asm volatile(␊ |
351 | ␉␉" xorq %%rcx,%%rcx \n\t"␊ |
352 | ␉␉" movb $0x80,%%al \n\t"␊ |
353 | ␉␉" outb %%al,$0x43 \n\t"␊ |
354 | ␉␉" rdtsc \n\t"␊ |
355 | ␉␉" pushq %%rax \n\t"␊ |
356 | ␉␉" inb $0x42,%%al \n\t"␊ |
357 | ␉␉" movb %%al,%%cl \n\t"␊ |
358 | ␉␉" inb $0x42,%%al \n\t"␊ |
359 | ␉␉" movb %%al,%%ch \n\t"␊ |
360 | ␉␉" popq %%rax "␊ |
361 | ␉␉: "=A"(result), "=c"(*value));␊ |
362 | #endif␊ |
363 | ␊ |
364 | return result;␊ |
365 | }␊ |
366 | ␊ |
367 | #endif /* !__LIBSAIO_CPU_H */␊ |
368 | |