1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
34 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
36 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
37 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
38 | ␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊ |
39 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
40 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
41 | ␊ |
42 | ␉␉␉␉␉␉value->word = 0;␊ |
43 | ␉␉␉␉␉␉break;␊ |
44 | ␉␉␉␉␉default:␊ |
45 | ␉␉␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
46 | ␉␉␉␉}␊ |
47 | ␉␉␉}␊ |
48 | ␉␉␉␉break;␊ |
49 | ␊ |
50 | ␉␉␉default:␊ |
51 | ␉␉␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
52 | ␉␉}␊ |
53 | ␉}␊ |
54 | ␉else␊ |
55 | ␉{␊ |
56 | ␉␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
57 | ␉}␊ |
58 | ␊ |
59 | ␉return true;␊ |
60 | }␊ |
61 | ␊ |
62 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
63 | {␊ |
64 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
65 | ␉return true;␊ |
66 | }␊ |
67 | ␊ |
68 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
69 | {␊ |
70 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
71 | ␉{␉␉␊ |
72 | ␉␉switch (Platform.CPU.Family) ␊ |
73 | ␉␉{␊ |
74 | ␉␉␉case 0x06:␊ |
75 | ␉␉␉{␊ |
76 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
77 | ␉␉␉␉{␊ |
78 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
79 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
80 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
81 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
82 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
83 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
84 | ␉␉␉␉␉␉return false;␊ |
85 | ␊ |
86 | ␉␉␉␉␉case 0x19:␊ |
87 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
88 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
89 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
90 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
91 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
92 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
93 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
94 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
95 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊ |
96 | ␉␉␉␉␉{␊ |
97 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
98 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
99 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
100 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
101 | ␉␉␉␉␉␉unsigned int i;␊ |
102 | ␉␉␉␉␉␉␊ |
103 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
104 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
105 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
106 | ␉␉␉␉␉␉{␊ |
107 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
108 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
109 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
110 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
111 | ␉␉␉␉␉␉␉␊ |
112 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
113 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
114 | ␉␉␉␉␉␉}␊ |
115 | ␊ |
116 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
117 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
118 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
119 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
120 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
121 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
122 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
123 | ␉␉␉␉␉␉{␊ |
124 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
125 | ␉␉␉␉␉␉}␊ |
126 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
127 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
128 | ␉␉␉␉␉␉return true;␊ |
129 | ␉␉␉␉␉}␊ |
130 | ␉␉␉␉}␊ |
131 | ␉␉␉}␊ |
132 | ␉␉}␊ |
133 | ␉}␊ |
134 | ␉return false;␊ |
135 | }␊ |
136 | ␊ |
137 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
138 | {␊ |
139 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
140 | ␉{␊ |
141 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
142 | ␉}␊ |
143 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
144 | ␉{␊ |
145 | ␉␉return 0x0201;␉// Core Solo␊ |
146 | ␉};␊ |
147 | ␉␊ |
148 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
149 | }␊ |
150 | ␊ |
151 | bool getSMBOemProcessorType(returnType *value)␊ |
152 | {␊ |
153 | ␉static bool done = false;␉␉␊ |
154 | ␊ |
155 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
156 | ␊ |
157 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
158 | ␉{␊ |
159 | ␉␉if (!done)␊ |
160 | ␉␉{␊ |
161 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
162 | ␉␉␉done = true;␊ |
163 | ␉␉}␊ |
164 | ␊ |
165 | ␉␉switch (Platform.CPU.Family) ␊ |
166 | ␉␉{␊ |
167 | ␉␉␉case 0x06:␊ |
168 | ␉␉␉{␊ |
169 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
170 | ␉␉␉␉{␊ |
171 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
172 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// Intel Pentium M␊ |
173 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Intel Mobile Core Solo, Duo␊ |
174 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
175 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
176 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
177 | ␉␉␉␉␉␉return true;␊ |
178 | ␊ |
179 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
180 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
181 | ␉␉␉␉␉␉{␊ |
182 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊ |
183 | ␉␉␉␉␉␉}␊ |
184 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
185 | ␉␉␉␉␉␉{␊ |
186 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
187 | ␉␉␉␉␉␉}␊ |
188 | ␉␉␉␉␉␉return true;␊ |
189 | ␊ |
190 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
191 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
192 | ␉␉␉␉␉␉{␊ |
193 | ␉␉␉␉␉␉␉value->word = 0x501;// Xeon␊ |
194 | ␉␉␉␉␉␉}␊ |
195 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
196 | ␉␉␉␉␉␉{␊ |
197 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
198 | ␉␉␉␉␉␉}␊ |
199 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
200 | ␉␉␉␉␉␉{␊ |
201 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// Core i7␊ |
202 | ␉␉␉␉␉␉}␊ |
203 | ␊ |
204 | ␉␉␉␉␉␉return true;␊ |
205 | ␊ |
206 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
207 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
208 | ␉␉␉␉␉␉{␊ |
209 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
210 | ␉␉␉␉␉␉}␊ |
211 | ␉␉␉␉␉␉else␊ |
212 | ␉␉␉␉␉␉{␊ |
213 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
214 | ␉␉␉␉␉␉}␊ |
215 | ␉␉␉␉␉␉return true;␊ |
216 | ␊ |
217 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
218 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
219 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
220 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
221 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
222 | ␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊ |
223 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
224 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
225 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊ |
226 | ␉␉␉␉␉␉{␊ |
227 | ␉␉␉␉␉␉␉value->word = 0x0501;␉␉// Xeon␊ |
228 | ␉␉␉␉␉␉}␊ |
229 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
230 | ␉␉␉␉␉␉{␊ |
231 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊ |
232 | ␉␉␉␉␉␉}␊ |
233 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
234 | ␉␉␉␉␉␉{␊ |
235 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
236 | ␉␉␉␉␉␉}␊ |
237 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7"))␊ |
238 | ␉␉␉␉␉␉{␊ |
239 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
240 | ␉␉␉␉␉␉}␊ |
241 | ␉␉␉␉␉␉return true;␊ |
242 | ␊ |
243 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
244 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
245 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊ |
246 | ␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Core i7␊ |
247 | ␉␉␉␉␉␉return true;␊ |
248 | ␊ |
249 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
250 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
251 | ␉␉␉␉␉␉return true;␊ |
252 | ␉␉␉␉␉default:␊ |
253 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
254 | ␉␉␉␉}␊ |
255 | ␉␉␉}␊ |
256 | ␉␉␉default:␊ |
257 | ␉␉␉␉break; ␊ |
258 | ␉␉}␊ |
259 | ␉}␊ |
260 | ␉␊ |
261 | ␉return false;␊ |
262 | }␊ |
263 | ␊ |
264 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
265 | {␊ |
266 | ␉static int idx = -1;␊ |
267 | ␉int␉map;␊ |
268 | ␊ |
269 | ␉idx++;␊ |
270 | ␉if (idx < MAX_RAM_SLOTS)␊ |
271 | ␉{␊ |
272 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
273 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
274 | ␉␉{␊ |
275 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
276 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
277 | ␉␉␉return true;␊ |
278 | ␉␉}␊ |
279 | ␉}␊ |
280 | ␉␊ |
281 | ␉return false;␊ |
282 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
283 | //␉return true;␊ |
284 | }␊ |
285 | ␊ |
286 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
287 | {␊ |
288 | ␉value->word = 0xFFFF;␊ |
289 | ␉return true;␊ |
290 | }␊ |
291 | ␊ |
292 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
293 | {␊ |
294 | ␉static int idx = -1;␊ |
295 | ␉int␉map;␊ |
296 | ␊ |
297 | ␉idx++;␊ |
298 | ␉if (idx < MAX_RAM_SLOTS)␊ |
299 | ␉{␊ |
300 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
301 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
302 | ␉␉{␊ |
303 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
304 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
305 | ␉␉␉return true;␊ |
306 | ␉␉}␊ |
307 | ␉}␊ |
308 | ␊ |
309 | ␉return false;␊ |
310 | //␉value->dword = 800;␊ |
311 | //␉return true;␊ |
312 | }␊ |
313 | ␊ |
314 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
315 | {␊ |
316 | ␉static int idx = -1;␊ |
317 | ␉int␉map;␊ |
318 | ␊ |
319 | ␉idx++;␊ |
320 | ␉if (idx < MAX_RAM_SLOTS)␊ |
321 | ␉{␊ |
322 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
323 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
324 | ␉␉{␊ |
325 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
326 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
327 | ␉␉␉return true;␊ |
328 | ␉␉}␊ |
329 | ␉}␊ |
330 | ␊ |
331 | ␉if (!bootInfo->memDetect)␊ |
332 | ␉{␊ |
333 | ␉␉return false;␊ |
334 | ␉}␊ |
335 | ␉value->string = NOT_AVAILABLE;␊ |
336 | ␉return true;␊ |
337 | }␊ |
338 | ␊ |
339 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
340 | {␊ |
341 | ␉static int idx = -1;␊ |
342 | ␉int␉map;␊ |
343 | ␊ |
344 | ␉idx++;␊ |
345 | ␊ |
346 | ␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
347 | ␊ |
348 | ␉if (idx < MAX_RAM_SLOTS)␊ |
349 | ␉{␊ |
350 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
351 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
352 | ␉␉{␊ |
353 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
354 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
355 | ␉␉␉return true;␊ |
356 | ␉␉}␊ |
357 | ␉}␊ |
358 | ␊ |
359 | ␉if (!bootInfo->memDetect)␊ |
360 | ␉{␊ |
361 | ␉␉return false;␊ |
362 | ␉}␊ |
363 | ␉value->string = NOT_AVAILABLE;␊ |
364 | ␉return true;␊ |
365 | }␊ |
366 | ␊ |
367 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
368 | {␊ |
369 | ␉static int idx = -1;␊ |
370 | ␉int␉map;␊ |
371 | ␊ |
372 | ␉idx++;␊ |
373 | ␉if (idx < MAX_RAM_SLOTS)␊ |
374 | ␉{␊ |
375 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
376 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
377 | ␉␉{␊ |
378 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
379 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
380 | ␉␉␉return true;␊ |
381 | ␉␉}␊ |
382 | ␉}␊ |
383 | ␊ |
384 | ␉if (!bootInfo->memDetect)␊ |
385 | ␉{␊ |
386 | ␉␉return false;␊ |
387 | ␉}␊ |
388 | ␉value->string = NOT_AVAILABLE;␊ |
389 | ␉return true;␊ |
390 | }␊ |
391 | ␊ |
392 | ␊ |
393 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
394 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
395 | static const char * const SMTAG = "_SM_";␊ |
396 | static const char* const DMITAG = "_DMI_";␊ |
397 | ␊ |
398 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
399 | {␊ |
400 | ␉SMBEntryPoint␉*smbios;␊ |
401 | ␉/* ␊ |
402 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
403 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
404 | ␉ */␊ |
405 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
406 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
407 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
408 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
409 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
410 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
411 | ␉ {␊ |
412 | ␉␉␉return smbios;␊ |
413 | ␉ }␊ |
414 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
415 | ␉}␊ |
416 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
417 | ␉pause();␊ |
418 | ␉return NULL;␊ |
419 | }␊ |
420 | ␊ |
421 | |