1 | /*␊ |
2 | * dram controller access and scan from the pci host controller␊ |
3 | * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work␊ |
4 | * original source comes from:␊ |
5 | *␊ |
6 | * memtest86␊ |
7 | *␊ |
8 | * Released under version 2 of the Gnu Public License.␊ |
9 | * By Chris Brady, cbrady@sgi.com␊ |
10 | * ----------------------------------------------------␊ |
11 | * MemTest86+ V4.00 Specific code (GPL V2.0)␊ |
12 | * By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊ |
13 | * http://www.canardpc.com - http://www.memtest.org␊ |
14 | */␊ |
15 | ␊ |
16 | #include "libsaio.h"␊ |
17 | #include "bootstruct.h"␊ |
18 | #include "pci.h"␊ |
19 | #include "platform.h"␊ |
20 | #include "dram_controllers.h"␊ |
21 | ␊ |
22 | #ifndef DEBUG_DRAM␊ |
23 | #define DEBUG_DRAM 0␊ |
24 | #endif␊ |
25 | ␊ |
26 | #if DEBUG_DRAM␊ |
27 | #define DBG(x...) printf(x)␊ |
28 | #else␊ |
29 | #define DBG(x...)␊ |
30 | #endif␊ |
31 | ␊ |
32 | /*␊ |
33 | * Initialise memory controller functions␊ |
34 | */␊ |
35 | ␊ |
36 | // Setup P35 Memory Controller␊ |
37 | static void setup_p35(pci_dt_t *dram_dev)␊ |
38 | {␊ |
39 | ␉uint32_t dev0;␊ |
40 | ␊ |
41 | ␉// Activate MMR I/O␊ |
42 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
43 | ␉if (!(dev0 & 0x1)) {␊ |
44 | ␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊ |
45 | ␉}␊ |
46 | }␊ |
47 | ␊ |
48 | int nhm_bus = 0x3F;␊ |
49 | ␊ |
50 | // Setup Nehalem Integrated Memory Controller␊ |
51 | static void setup_nhm(pci_dt_t *dram_dev)␊ |
52 | {␊ |
53 | ␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
54 | ␉unsigned long did, vid;␊ |
55 | ␉int i;␊ |
56 | ␊ |
57 | ␉// Nehalem supports Scrubbing␊ |
58 | ␉// First, locate the PCI bus where the MCH is located␊ |
59 | ␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊ |
60 | ␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊ |
61 | ␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊ |
62 | ␉␉vid &= 0xFFFF;␊ |
63 | ␉␉did &= 0xFF00;␊ |
64 | ␊ |
65 | ␉␉if(vid == 0x8086 && did >= 0x2C00) {␊ |
66 | ␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
67 | ␉␉}␊ |
68 | ␉}␊ |
69 | }␊ |
70 | ␊ |
71 | /*␊ |
72 | * Retrieve memory controller fsb functions␊ |
73 | */␊ |
74 | ␊ |
75 | ␊ |
76 | // Get i965 Memory Speed␊ |
77 | static void get_fsb_i965(pci_dt_t *dram_dev)␊ |
78 | {␊ |
79 | ␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊ |
80 | ␊ |
81 | ␉long *ptr;␊ |
82 | ␊ |
83 | ␉// Find Ratio␊ |
84 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
85 | ␉dev0 &= 0xFFFFC000;␊ |
86 | ␉ptr = (long*)(dev0 + 0xC00);␊ |
87 | ␉mch_cfg = *ptr & 0xFFFF;␊ |
88 | ␊ |
89 | ␉mch_ratio = 100000;␊ |
90 | ␊ |
91 | ␉switch (mch_cfg & 7) {␊ |
92 | ␉␉case 0: mch_fsb = 1066; break;␊ |
93 | ␉␉case 1: mch_fsb = 533; break;␊ |
94 | ␉␉default:␊ |
95 | ␉␉case 2: mch_fsb = 800; break;␊ |
96 | ␉␉case 3: mch_fsb = 667; break;␊ |
97 | ␉␉case 4: mch_fsb = 1333; break;␊ |
98 | ␉␉case 6: mch_fsb = 1600; break;␊ |
99 | ␉}␊ |
100 | ␊ |
101 | ␉DBG("mch_fsb %d\n", mch_fsb);␊ |
102 | ␊ |
103 | ␉switch (mch_fsb) {␊ |
104 | ␉␉case 533:␊ |
105 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
106 | ␉␉␉case 1:␉mch_ratio = 200000; break;␊ |
107 | ␉␉␉case 2:␉mch_ratio = 250000; break;␊ |
108 | ␉␉␉case 3:␉mch_ratio = 300000; break;␊ |
109 | ␉␉}␊ |
110 | ␉␉break;␊ |
111 | ␊ |
112 | ␉␉default:␊ |
113 | ␉␉case 800:␊ |
114 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
115 | ␉␉␉case 0:␉mch_ratio = 100000; break;␊ |
116 | ␉␉␉case 1:␉mch_ratio = 125000; break;␊ |
117 | ␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊ |
118 | ␉␉␉case 3:␉mch_ratio = 200000; break;␊ |
119 | ␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊ |
120 | ␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊ |
121 | ␉␉}␊ |
122 | ␉␉break;␊ |
123 | ␊ |
124 | ␉␉case 1066:␊ |
125 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
126 | ␉␉␉case 1:␉mch_ratio = 100000; break;␊ |
127 | ␉␉␉case 2:␉mch_ratio = 125000; break;␊ |
128 | ␉␉␉case 3:␉mch_ratio = 150000; break;␊ |
129 | ␉␉␉case 4:␉mch_ratio = 200000; break;␊ |
130 | ␉␉␉case 5:␉mch_ratio = 250000; break;␊ |
131 | ␉␉}␊ |
132 | ␉␉break;␊ |
133 | ␊ |
134 | ␉␉case 1333:␊ |
135 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
136 | ␉␉␉case 2:␉mch_ratio = 100000; break;␊ |
137 | ␉␉␉case 3:␉mch_ratio = 120000; break;␊ |
138 | ␉␉␉case 4:␉mch_ratio = 160000; break;␊ |
139 | ␉␉␉case 5:␉mch_ratio = 200000; break;␊ |
140 | ␉␉}␊ |
141 | ␉␉break;␊ |
142 | ␊ |
143 | ␉␉case 1600:␊ |
144 | ␉␉switch ((mch_cfg >> 4) & 7)␊ |
145 | ␉␉{␊ |
146 | ␉␉␉case 3:␉mch_ratio = 100000; break;␊ |
147 | ␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊ |
148 | ␉␉␉case 5:␉mch_ratio = 150000; break;␊ |
149 | ␉␉␉case 6:␉mch_ratio = 200000; break;␊ |
150 | ␉␉}␊ |
151 | ␉␉break;␊ |
152 | ␉}␊ |
153 | ␊ |
154 | ␉DBG("mch_ratio %d\n", mch_ratio);␊ |
155 | ␊ |
156 | ␉// Compute RAM Frequency␊ |
157 | ␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊ |
158 | ␊ |
159 | ␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊ |
160 | ␊ |
161 | }␊ |
162 | ␊ |
163 | // Get i965m Memory Speed␊ |
164 | static void get_fsb_im965(pci_dt_t *dram_dev)␊ |
165 | {␊ |
166 | ␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊ |
167 | ␊ |
168 | ␉long *ptr;␊ |
169 | ␊ |
170 | ␉// Find Ratio␊ |
171 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
172 | ␉dev0 &= 0xFFFFC000;␊ |
173 | ␉ptr = (long*)(dev0 + 0xC00);␊ |
174 | ␉mch_cfg = *ptr & 0xFFFF;␊ |
175 | ␊ |
176 | ␉mch_ratio = 100000;␊ |
177 | ␊ |
178 | ␉switch (mch_cfg & 7) {␊ |
179 | ␉␉case 1: mch_fsb = 533; break;␊ |
180 | ␉␉default: ␊ |
181 | ␉␉case 2:␉mch_fsb = 800; break;␊ |
182 | ␉␉case 3:␉mch_fsb = 667; break;␊ |
183 | ␉␉case 6:␉mch_fsb = 1066; break;␊ |
184 | ␉}␊ |
185 | ␊ |
186 | ␉switch (mch_fsb) {␊ |
187 | ␉␉case 533:␊ |
188 | ␉␉␉switch ((mch_cfg >> 4) & 7) {␊ |
189 | ␉␉␉␉case 1:␉mch_ratio = 125000; break;␊ |
190 | ␉␉␉␉case 2:␉mch_ratio = 150000; break;␊ |
191 | ␉␉␉␉case 3:␉mch_ratio = 200000; break;␊ |
192 | ␉␉␉}␊ |
193 | ␉␉␉break;␊ |
194 | ␊ |
195 | ␉␉case 667:␊ |
196 | ␉␉␉switch ((mch_cfg >> 4)& 7) {␊ |
197 | ␉␉␉␉case 1:␉mch_ratio = 100000; break;␊ |
198 | ␉␉␉␉case 2:␉mch_ratio = 120000; break;␊ |
199 | ␉␉␉␉case 3:␉mch_ratio = 160000; break;␊ |
200 | ␉␉␉␉case 4:␉mch_ratio = 200000; break;␊ |
201 | ␉␉␉␉case 5:␉mch_ratio = 240000; break;␊ |
202 | ␉␉␉}␊ |
203 | ␉␉␉break;␊ |
204 | ␊ |
205 | ␉␉default:␊ |
206 | ␉␉case 800:␊ |
207 | ␉␉␉switch ((mch_cfg >> 4) & 7) {␊ |
208 | ␉␉␉␉case 1:␉mch_ratio = 83333; break; // 0.833333333␊ |
209 | ␉␉␉␉case 2:␉mch_ratio = 100000; break;␊ |
210 | ␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊ |
211 | ␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊ |
212 | ␉␉␉␉case 5:␉mch_ratio = 200000; break;␊ |
213 | ␉␉␉}␊ |
214 | ␉␉␉break;␊ |
215 | ␉␉case 1066:␊ |
216 | ␉␉␉switch ((mch_cfg >> 4)&7) {␊ |
217 | ␉␉␉␉case 5:␉mch_ratio = 150000; break;␊ |
218 | ␉␉␉␉case 6:␉mch_ratio = 200000; break;␊ |
219 | ␉␉␉}␊ |
220 | ␊ |
221 | ␉}␊ |
222 | ␊ |
223 | ␉// Compute RAM Frequency␊ |
224 | ␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊ |
225 | ␊ |
226 | ␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊ |
227 | }␊ |
228 | ␊ |
229 | ␊ |
230 | // Get iCore7 Memory Speed␊ |
231 | static void get_fsb_nhm(pci_dt_t *dram_dev)␊ |
232 | {␊ |
233 | ␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊ |
234 | ␊ |
235 | ␉// Get the clock ratio␊ |
236 | ␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊ |
237 | ␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊ |
238 | ␊ |
239 | ␉// Compute RAM Frequency␊ |
240 | ␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊ |
241 | ␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊ |
242 | }␊ |
243 | ␊ |
244 | /*␊ |
245 | * Retrieve memory controller info functions␊ |
246 | */␊ |
247 | ␊ |
248 | // Get i965 Memory Timings␊ |
249 | static void get_timings_i965(pci_dt_t *dram_dev)␊ |
250 | {␊ |
251 | ␉// Thanks for CDH optis␊ |
252 | ␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊ |
253 | ␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊ |
254 | ␊ |
255 | ␉long *ptr;␊ |
256 | ␊ |
257 | ␉// Read MMR Base Address␊ |
258 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
259 | ␉dev0 &= 0xFFFFC000;␊ |
260 | ␊ |
261 | ␉ptr = (long*)(dev0 + 0x260);␊ |
262 | ␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊ |
263 | ␊ |
264 | ␉ptr = (long*)(dev0 + 0x660);␊ |
265 | ␉c1ckectrl = *ptr & 0xFFFFFFFF;␊ |
266 | ␊ |
267 | ␉// If DIMM 0 not populated, check DIMM 1␊ |
268 | ␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊ |
269 | ␊ |
270 | ␉ptr = (long*)(dev0 + offset + 0x29C);␊ |
271 | ␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊ |
272 | ␊ |
273 | ␉ptr = (long*)(dev0 + offset + 0x250);␉␊ |
274 | ␉Precharge_Register = *ptr & 0xFFFFFFFF;␊ |
275 | ␊ |
276 | ␉ptr = (long*)(dev0 + offset + 0x252);␊ |
277 | ␉ACT_Register = *ptr & 0xFFFFFFFF;␊ |
278 | ␊ |
279 | ␉ptr = (long*)(dev0 + offset + 0x258);␊ |
280 | ␉Read_Register = *ptr & 0xFFFFFFFF;␊ |
281 | ␊ |
282 | ␉ptr = (long*)(dev0 + offset + 0x244);␊ |
283 | ␉Misc_Register = *ptr & 0xFFFFFFFF;␊ |
284 | ␊ |
285 | ␉// 965 Series only support DDR2␊ |
286 | ␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊ |
287 | ␊ |
288 | ␉// CAS Latency (tCAS)␊ |
289 | ␉Platform.RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3;␊ |
290 | ␊ |
291 | ␉// RAS-To-CAS (tRCD)␊ |
292 | ␉Platform.RAM.TRC = (Read_Register >> 16) & 0xF;␊ |
293 | ␊ |
294 | ␉// RAS Precharge (tRP)␊ |
295 | ␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊ |
296 | ␊ |
297 | ␉// RAS Active to precharge (tRAS)␊ |
298 | ␉Platform.RAM.RAS = (Precharge_Register >> 11) & 0x1F;␊ |
299 | ␊ |
300 | ␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊ |
301 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
302 | ␉} else {␊ |
303 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
304 | ␉}␊ |
305 | }␊ |
306 | ␊ |
307 | // Get im965 Memory Timings␊ |
308 | static void get_timings_im965(pci_dt_t *dram_dev)␊ |
309 | {␊ |
310 | ␉// Thanks for CDH optis␊ |
311 | ␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊ |
312 | ␉long *ptr;␊ |
313 | ␊ |
314 | ␉// Read MMR Base Address␊ |
315 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
316 | ␉dev0 &= 0xFFFFC000;␊ |
317 | ␊ |
318 | ␉ptr = (long*)(dev0 + 0x1200);␊ |
319 | ␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊ |
320 | ␊ |
321 | ␉ptr = (long*)(dev0 + 0x1300);␊ |
322 | ␉c1ckectrl = *ptr & 0xFFFFFFFF;␊ |
323 | ␊ |
324 | ␉// If DIMM 0 not populated, check DIMM 1␊ |
325 | ␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊ |
326 | ␊ |
327 | ␉ptr = (long*)(dev0 + offset + 0x121C);␊ |
328 | ␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊ |
329 | ␊ |
330 | ␉ptr = (long*)(dev0 + offset + 0x1214);␉␊ |
331 | ␉Precharge_Register = *ptr & 0xFFFFFFFF;␊ |
332 | ␊ |
333 | ␉// Series only support DDR2␊ |
334 | ␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊ |
335 | ␊ |
336 | ␉// CAS Latency (tCAS)␊ |
337 | ␉Platform.RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3;␊ |
338 | ␊ |
339 | ␉// RAS-To-CAS (tRCD)␊ |
340 | ␉Platform.RAM.TRC = ((Precharge_Register >> 5) & 7) + 2;␊ |
341 | ␊ |
342 | ␉// RAS Precharge (tRP)␊ |
343 | ␉Platform.RAM.TRP= (Precharge_Register & 7) + 2;␊ |
344 | ␊ |
345 | ␉// RAS Active to precharge (tRAS)␊ |
346 | ␉Platform.RAM.RAS = (Precharge_Register >> 21) & 0x1F;␊ |
347 | ␊ |
348 | ␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊ |
349 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
350 | ␉} else {␊ |
351 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
352 | ␉}␊ |
353 | }␊ |
354 | ␊ |
355 | // Get P35 Memory Timings␊ |
356 | static void get_timings_p35(pci_dt_t *dram_dev)␊ |
357 | {␊ |
358 | ␉// Thanks for CDH optis␊ |
359 | ␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊ |
360 | ␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊ |
361 | ␉long *ptr;␊ |
362 | ␊ |
363 | ␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊ |
364 | ␉//Device_ID &= 0xFFFF;␊ |
365 | ␊ |
366 | ␉// Now, read MMR Base Address␊ |
367 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
368 | ␉dev0 &= 0xFFFFC000;␊ |
369 | ␊ |
370 | ␉ptr = (long*)(dev0 + 0x260);␊ |
371 | ␉c0ckectrl = *ptr & 0xFFFFFFFF;␊ |
372 | ␊ |
373 | ␉ptr = (long*)(dev0 + 0x660);␊ |
374 | ␉c1ckectrl = *ptr & 0xFFFFFFFF;␊ |
375 | ␊ |
376 | ␉// If DIMM 0 not populated, check DIMM 1␊ |
377 | ␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊ |
378 | ␊ |
379 | ␉ptr = (long*)(dev0 + offset + 0x265);␊ |
380 | ␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊ |
381 | ␊ |
382 | ␉ptr = (long*)(dev0 + offset + 0x25D);␊ |
383 | ␉Precharge_Register = *ptr & 0xFFFFFFFF;␊ |
384 | ␊ |
385 | ␉ptr = (long*)(dev0 + offset + 0x252);␊ |
386 | ␉ACT_Register = *ptr & 0xFFFFFFFF;␊ |
387 | ␊ |
388 | ␉ptr = (long*)(dev0 + offset + 0x258);␊ |
389 | ␉Read_Register = *ptr & 0xFFFFFFFF;␊ |
390 | ␊ |
391 | ␉ptr = (long*)(dev0 + offset + 0x244);␊ |
392 | ␉Misc_Register = *ptr & 0xFFFFFFFF;␊ |
393 | ␊ |
394 | ␉ptr = (long*)(dev0 + offset + 0x1E8);␊ |
395 | ␉Memory_Check = *ptr & 0xFFFFFFFF;␊ |
396 | ␊ |
397 | ␉// On P45, check 1A8␊ |
398 | ␉if(dram_dev->device_id > 0x2E00) {␊ |
399 | ␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊ |
400 | ␉␉Memory_Check = *ptr & 0xFFFFFFFF;␊ |
401 | ␉␉Memory_Check >>= 2;␊ |
402 | ␉␉Memory_Check &= 1;␊ |
403 | ␉␉Memory_Check = !Memory_Check;␊ |
404 | ␉} else {␊ |
405 | ␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊ |
406 | ␉␉Memory_Check = *ptr & 0xFFFFFFFF;␊ |
407 | ␉}␊ |
408 | ␊ |
409 | ␉// Determine DDR-II or DDR-III␊ |
410 | ␉if (Memory_Check & 1) {␊ |
411 | ␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊ |
412 | ␉} else {␊ |
413 | ␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊ |
414 | ␉}␊ |
415 | ␊ |
416 | ␉// CAS Latency (tCAS)␊ |
417 | ␉if(dram_dev->device_id > 0x2E00) {␊ |
418 | ␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊ |
419 | ␉} else {␊ |
420 | ␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊ |
421 | ␉}␊ |
422 | ␊ |
423 | ␉// RAS-To-CAS (tRCD)␊ |
424 | ␉Platform.RAM.TRC = (Read_Register >> 17) & 0xF;␊ |
425 | ␊ |
426 | ␉// RAS Precharge (tRP)␊ |
427 | ␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊ |
428 | ␊ |
429 | ␉// RAS Active to precharge (tRAS)␊ |
430 | ␉Platform.RAM.RAS = Precharge_Register & 0x3F;␊ |
431 | ␊ |
432 | ␉// Channel configuration␊ |
433 | ␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) {␊ |
434 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
435 | ␉} else {␊ |
436 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
437 | ␉}␊ |
438 | }␊ |
439 | ␊ |
440 | // Get Nehalem Memory Timings␊ |
441 | static void get_timings_nhm(pci_dt_t *dram_dev)␊ |
442 | {␊ |
443 | ␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊ |
444 | ␉int fvc_bn = 4;␊ |
445 | ␊ |
446 | ␉// Find which channels are populated␊ |
447 | ␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊ |
448 | ␉mc_control = (mc_control >> 8) & 0x7;␊ |
449 | ␊ |
450 | ␉// DDR-III␊ |
451 | ␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊ |
452 | ␊ |
453 | ␉// Get the first valid channel␊ |
454 | ␉if(mc_control & 1) {␊ |
455 | ␉␉fvc_bn = 4; ␊ |
456 | ␉} else if(mc_control & 2) {␊ |
457 | ␉␉fvc_bn = 5; ␊ |
458 | ␉} else if(mc_control & 7) {␊ |
459 | ␉␉fvc_bn = 6; ␊ |
460 | ␉}␊ |
461 | ␊ |
462 | ␉// Now, detect timings␊ |
463 | ␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊ |
464 | ␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊ |
465 | ␊ |
466 | ␉// CAS Latency (tCAS)␊ |
467 | ␉Platform.RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4;␊ |
468 | ␊ |
469 | ␉// RAS-To-CAS (tRCD)␊ |
470 | ␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊ |
471 | ␊ |
472 | ␉// RAS Active to precharge (tRAS)␊ |
473 | ␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊ |
474 | ␊ |
475 | ␉// RAS Precharge (tRP)␊ |
476 | ␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊ |
477 | ␊ |
478 | ␉// Single , Dual or Triple Channels␊ |
479 | ␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) {␊ |
480 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
481 | ␉} else if (mc_control == 7) {␊ |
482 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_TRIPLE;␊ |
483 | ␉} else ␉{␊ |
484 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
485 | ␉}␊ |
486 | }␊ |
487 | ␊ |
488 | static struct mem_controller_t dram_controllers[] = {␊ |
489 | ␊ |
490 | ␉// Default unknown chipset␊ |
491 | ␉{ 0, 0, "",␉NULL, NULL, NULL },␊ |
492 | ␊ |
493 | ␉// Intel␊ |
494 | //␉{ 0x8086, 0x0100, "2rd Gen Core processor",␉NULL, NULL, NULL },␊ |
495 | //␉{ 0x8086, 0x0104, "2rd Gen Core processor",␉NULL, NULL, NULL },␊ |
496 | //␉{ 0x8086, 0x010C, "Xeon E3-1200/2rd Gen Core processor",␉NULL, NULL, NULL },␊ |
497 | //␉{ 0x8086, 0x0150, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊ |
498 | //␉{ 0x8086, 0x0154, "3rd Gen Core processor",␉NULL, NULL, NULL },␊ |
499 | //␉{ 0x8086, 0x0158, "Xeon E3-1200 v2/Ivy Bridge",␉NULL, NULL, NULL },␊ |
500 | //␉{ 0x8086, 0x015C, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊ |
501 | ␊ |
502 | //␉{ 0x8086, 0x0BF0, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
503 | //␉{ 0x8086, 0x0BF1, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
504 | //␉{ 0x8086, 0x0BF2, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
505 | //␉{ 0x8086, 0x0BF3, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
506 | //␉{ 0x8086, 0x0BF4, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
507 | //␉{ 0x8086, 0x0BF5, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
508 | //␉{ 0x8086, 0x0BF6, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
509 | //␉{ 0x8086, 0x0BF7, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
510 | ␊ |
511 | //␉{ 0x8086, 0x0C00, "Haswell",␉NULL, NULL, NULL },␊ |
512 | //␉{ 0x8086, 0x0C04, "Haswell",␉NULL, NULL, NULL },␊ |
513 | //␉{ 0x8086, 0x0C08, "Haswell",␉NULL, NULL, NULL },␊ |
514 | ␊ |
515 | ␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊ |
516 | ␊ |
517 | ␉{ 0x8086, 0x1A30, "82845 845 [Brookdale]",␉NULL, NULL, NULL },␊ |
518 | ␉␊ |
519 | ␉{ 0x8086, 0x2970, "82946GZ/PL/GL",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊ |
520 | ␉{ 0x8086, 0x2990, "82Q963/Q965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊ |
521 | ␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊ |
522 | ␊ |
523 | ␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊ |
524 | ␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊ |
525 | ␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊ |
526 | ␊ |
527 | ␉{ 0x8086, 0x29B0, "82Q35 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
528 | ␉{ 0x8086, 0x29C0, "82G33/G31/P35/P31",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
529 | ␉{ 0x8086, 0x29D0, "82Q33 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
530 | ␉{ 0x8086, 0x29E0, "82X38/X48 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
531 | ␉{ 0x8086, 0x29F0, "3200/3210",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
532 | ␊ |
533 | ␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
534 | ␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
535 | ␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
536 | ␉{ 0x8086, 0x2E30, "G41",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
537 | //␉{ 0x8086, 0x2E40, "4 Series Chipset",␉␉NULL, NULL, NULL },␊ |
538 | //␉{ 0x8086, 0x2E90, "4 Series Chipset",␉␉NULL, NULL, NULL },␊ |
539 | ␊ |
540 | ␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
541 | ␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
542 | ␉{ 0x8086, 0x3400, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
543 | ␉{ 0x8086, 0x3401, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
544 | ␉{ 0x8086, 0x3402, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
545 | ␉{ 0x8086, 0x3403, "5500",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
546 | ␉{ 0x8086, 0x3404, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
547 | ␉{ 0x8086, 0x3405, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
548 | ␉{ 0x8086, 0x3406, "5520",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
549 | ␉{ 0x8086, 0x3407, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
550 | };␊ |
551 | ␊ |
552 | static const char *memory_channel_types[] =␊ |
553 | {␊ |
554 | ␉"Unknown", "Single", "Dual", "Triple"␊ |
555 | };␊ |
556 | ␊ |
557 | void scan_dram_controller(pci_dt_t *dram_dev)␊ |
558 | {␊ |
559 | ␉int i;␊ |
560 | ␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++) {␊ |
561 | ␉␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) && (dram_controllers[i].device == dram_dev->device_id)) {␊ |
562 | ␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊ |
563 | ␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel Corporation " : "" ,␊ |
564 | ␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊ |
565 | ␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊ |
566 | ␊ |
567 | ␉␉␉if (dram_controllers[i].initialise != NULL) {␊ |
568 | ␉␉␉␉dram_controllers[i].initialise(dram_dev);␊ |
569 | ␉␉␉}␊ |
570 | ␊ |
571 | ␉␉␉if (dram_controllers[i].poll_timings != NULL) {␊ |
572 | ␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊ |
573 | ␉␉␉}␊ |
574 | ␊ |
575 | ␉␉␉if (dram_controllers[i].poll_speed != NULL) {␊ |
576 | ␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊ |
577 | ␉␉␉}␊ |
578 | ␊ |
579 | ␉␉␉verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", ␊ |
580 | ␉␉␉␉(uint32_t)Platform.RAM.Frequency / 1000000,␊ |
581 | ␉␉␉␉(uint32_t)Platform.RAM.Frequency / 500000,␊ |
582 | ␉␉␉␉memory_channel_types[Platform.RAM.Channels]␊ |
583 | ␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊ |
584 | ␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS);␊ |
585 | //␉␉␉getchar();␊ |
586 | ␉␉}␊ |
587 | ␉}␊ |
588 | }␊ |
589 | |