1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | #include "cpu.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "boot.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␉␉msglog(x)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * timeRDTSC()␊ |
24 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
25 | * It pauses until the value is latched in the counter␊ |
26 | * and then reads the time stamp counter to return to the caller.␊ |
27 | */␊ |
28 | uint64_t timeRDTSC(void)␊ |
29 | {␊ |
30 | ␉int␉␉attempts = 0;␊ |
31 | ␉uint64_t latchTime;␊ |
32 | ␉uint64_t␉saveTime,intermediate;␊ |
33 | ␉unsigned int timerValue, lastValue;␊ |
34 | ␉//boolean_t␉int_enabled;␊ |
35 | ␉/*␊ |
36 | ␉ * Table of correction factors to account for␊ |
37 | ␉ *␉ - timer counter quantization errors, and␊ |
38 | ␉ *␉ - undercounts 0..5␊ |
39 | ␉ */␊ |
40 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
41 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
42 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
43 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
44 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
45 | ␉uint64_t␉scale[6] = {␊ |
46 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
47 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
48 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
49 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
50 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
51 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
52 | ␉};␊ |
53 | ␊ |
54 | ␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊ |
55 | ␊ |
56 | restart:␊ |
57 | ␉if (attempts >= 9) // increase to up to 9 attempts.␊ |
58 | ␉{␊ |
59 | ␉ // This will flash-reboot. TODO: Use tscPanic instead.␊ |
60 | ␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
61 | ␉}␊ |
62 | ␉attempts++;␊ |
63 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
64 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
65 | ␉latchTime = rdtsc64();␉// get the time stamp to time ␊ |
66 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
67 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
68 | ␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
69 | ␉get_PIT2(&lastValue);␊ |
70 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
71 | ␉do {␊ |
72 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
73 | ␉␉if (timerValue > lastValue)␊ |
74 | ␉␉{␊ |
75 | ␉␉␉// Timer wrapped␊ |
76 | ␉␉␉set_PIT2(0);␊ |
77 | ␉␉␉disable_PIT2();␊ |
78 | ␉␉␉goto restart;␊ |
79 | ␉␉}␊ |
80 | ␉␉lastValue = timerValue;␊ |
81 | ␉} while (timerValue > 5);␊ |
82 | ␉printf("timerValue␉ %d\n",timerValue);␊ |
83 | ␉printf("intermediate 0x%016llx\n",intermediate);␊ |
84 | ␉printf("saveTime␉ 0x%016llx\n",saveTime);␊ |
85 | ␊ |
86 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
87 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
88 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
89 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
90 | ␊ |
91 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
92 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
93 | ␉␊ |
94 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
95 | ␉return intermediate;␊ |
96 | }␊ |
97 | ␊ |
98 | /*␊ |
99 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
100 | */␊ |
101 | static uint64_t measure_tsc_frequency(void)␊ |
102 | {␊ |
103 | ␉uint64_t tscStart;␊ |
104 | ␉uint64_t tscEnd;␊ |
105 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
106 | ␉unsigned long pollCount;␊ |
107 | ␉uint64_t retval = 0;␊ |
108 | ␉int i;␊ |
109 | ␊ |
110 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
111 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
112 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
113 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
114 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
115 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
116 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
117 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
118 | ␉ */␊ |
119 | ␉for(i = 0; i < 10; ++i)␊ |
120 | ␉{␊ |
121 | ␉␉enable_PIT2();␊ |
122 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
123 | ␉␉tscStart = rdtsc64();␊ |
124 | ␉␉pollCount = poll_PIT2_gate();␊ |
125 | ␉␉tscEnd = rdtsc64();␊ |
126 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
127 | ␉␉if (pollCount <= 1) {␊ |
128 | ␉␉␉continue;␊ |
129 | ␉␉}␊ |
130 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
131 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
132 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
133 | ␉␉ */␊ |
134 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) {␊ |
135 | ␉␉␉continue;␊ |
136 | ␉␉}␊ |
137 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
138 | ␉␉if ( (tscEnd - tscStart) < tscDelta ) {␊ |
139 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
140 | ␉␉}␊ |
141 | ␉}␊ |
142 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
143 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
144 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
145 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
146 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
147 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
148 | ␉ */␊ |
149 | ␊ |
150 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
151 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
152 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
153 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
154 | ␉ */␊ |
155 | ␉if (tscDelta > (1ULL<<32)) {␊ |
156 | ␉␉retval = 0;␊ |
157 | ␉} else {␊ |
158 | ␉␉retval = tscDelta * 1000 / 30;␊ |
159 | ␉}␊ |
160 | ␉disable_PIT2();␊ |
161 | ␉return retval;␊ |
162 | }␊ |
163 | ␊ |
164 | /*␊ |
165 | * Original comment/code:␊ |
166 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
167 | *␊ |
168 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
169 | * (just a naming change, mperf --> aperf )␊ |
170 | */␊ |
171 | static uint64_t measure_aperf_frequency(void)␊ |
172 | {␊ |
173 | ␉uint64_t aperfStart;␊ |
174 | ␉uint64_t aperfEnd;␊ |
175 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
176 | ␉unsigned long pollCount;␊ |
177 | ␉uint64_t retval = 0;␊ |
178 | ␉int i;␊ |
179 | ␊ |
180 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
181 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
182 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
183 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
184 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
185 | ␉ * expire.␊ |
186 | ␉ */␊ |
187 | ␉for(i = 0; i < 10; ++i)␊ |
188 | ␉{␊ |
189 | ␉␉enable_PIT2();␊ |
190 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
191 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
192 | ␉␉pollCount = poll_PIT2_gate();␊ |
193 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
194 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
195 | ␉␉if (pollCount <= 1)␊ |
196 | ␉␉{␊ |
197 | ␉␉␉continue;␊ |
198 | ␉␉}␊ |
199 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
200 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
201 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
202 | ␉␉ */␊ |
203 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
204 | ␉␉{␊ |
205 | ␉␉␉continue;␊ |
206 | ␉␉}␊ |
207 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
208 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
209 | ␉␉{␊ |
210 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
211 | ␉␉}␊ |
212 | ␉}␊ |
213 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
214 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
215 | ␉ */␊ |
216 | ␊ |
217 | ␉if (aperfDelta > (1ULL<<32))␊ |
218 | ␉{␊ |
219 | ␉␉retval = 0;␊ |
220 | ␉}␊ |
221 | ␉else␊ |
222 | ␉{␊ |
223 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
224 | ␉}␊ |
225 | ␉disable_PIT2();␊ |
226 | ␉return retval;␊ |
227 | }␊ |
228 | ␊ |
229 | /*␊ |
230 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
231 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
232 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
233 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
234 | * - fsbFrequency = tscFrequency / multi␊ |
235 | * - cpuFrequency = fsbFrequency * multi␊ |
236 | */␊ |
237 | void scan_cpu(PlatformInfo_t *p)␊ |
238 | {␊ |
239 | ␉uint64_t␉tscFrequency = 0;␊ |
240 | ␉uint64_t␉fsbFrequency = 0;␊ |
241 | ␉uint64_t␉cpuFrequency = 0;␊ |
242 | ␉uint64_t␉msr = 0;␊ |
243 | ␉uint64_t␉flex_ratio = 0;␊ |
244 | ␉uint32_t␉max_ratio = 0;␊ |
245 | ␉uint32_t␉min_ratio = 0;␊ |
246 | ␉uint8_t␉␉bus_ratio_max = 0;␊ |
247 | ␉uint8_t␉␉currdiv = 0;␊ |
248 | ␉uint8_t␉␉currcoef = 0;␊ |
249 | ␉uint8_t␉␉maxdiv = 0;␊ |
250 | ␉uint8_t␉␉maxcoef = 0;␊ |
251 | ␉const char␉*newratio;␊ |
252 | ␉int␉␉len = 0;␊ |
253 | ␉int␉␉myfsb = 0;␊ |
254 | ␉uint8_t␉␉bus_ratio_min = 0;␊ |
255 | ␉uint32_t␉reg[4];␊ |
256 | ␉char␉␉str[128];␊ |
257 | ␊ |
258 | ␉/* get cpuid values */␊ |
259 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
260 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
261 | ␊ |
262 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊ |
263 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊ |
264 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
265 | ␊ |
266 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
267 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊ |
268 | ␉{␊ |
269 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
270 | ␉}␊ |
271 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊ |
272 | ␉{␊ |
273 | ␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
274 | ␉}␊ |
275 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
276 | ␉{␊ |
277 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
278 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
279 | ␉}␊ |
280 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
281 | ␉{␊ |
282 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
283 | ␉}␊ |
284 | ␊ |
285 | // #if DEBUG_CPU␊ |
286 | ␉{␊ |
287 | ␉␉int␉␉i;␊ |
288 | ␉␉DBG("CPUID Raw Values:\n");␊ |
289 | ␉␉for (i = 0; i < CPUID_MAX; i++) {␊ |
290 | ␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
291 | ␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
292 | ␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
293 | ␉␉}␊ |
294 | ␉}␊ |
295 | // #endif␊ |
296 | ␊ |
297 | /*␊ |
298 | EAX (Intel):␊ |
299 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
300 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
301 | |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊ |
302 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
303 | ␊ |
304 | EAX (AMD):␊ |
305 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
306 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
307 | |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊ |
308 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
309 | */␊ |
310 | ␊ |
311 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
312 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
313 | ␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊ |
314 | ␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊ |
315 | ␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊ |
316 | ␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
317 | ␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
318 | ␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
319 | ␊ |
320 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
321 | ␊ |
322 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL)␊ |
323 | ␉{␊ |
324 | ␉␉/*␊ |
325 | ␉␉ * Find the number of enabled cores and threads␊ |
326 | ␉␉ * (which determines whether SMT/Hyperthreading is active).␊ |
327 | ␉␉ */␊ |
328 | ␉␉switch (p->CPU.Model)␊ |
329 | ␉␉{␊ |
330 | ␉␉␉case CPU_MODEL_NEHALEM:␊ |
331 | ␉␉␉case CPU_MODEL_FIELDS:␊ |
332 | ␉␉␉case CPU_MODEL_DALES:␊ |
333 | ␉␉␉case CPU_MODEL_NEHALEM_EX:␊ |
334 | ␉␉␉case CPU_MODEL_JAKETOWN:␊ |
335 | ␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
336 | ␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
337 | ␉␉␉case CPU_MODEL_HASWELL:␊ |
338 | ␉␉␉case CPU_MODEL_HASWELL_SVR:␊ |
339 | ␉␉␉//case CPU_MODEL_HASWELL_H:␊ |
340 | ␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
341 | ␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
342 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
343 | ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊ |
344 | ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
345 | ␉␉␉␉break;␊ |
346 | ␊ |
347 | ␉␉␉case CPU_MODEL_DALES_32NM:␊ |
348 | ␉␉␉case CPU_MODEL_WESTMERE:␊ |
349 | ␉␉␉case CPU_MODEL_WESTMERE_EX:␊ |
350 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
351 | ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊ |
352 | ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
353 | ␉␉␉␉break;␊ |
354 | ␊ |
355 | ␉␉␉default:␊ |
356 | ␉␉␉␉p->CPU.NoCores = 0;␊ |
357 | ␉␉␉␉break;␊ |
358 | ␉␉} // end switch␊ |
359 | ␉}␊ |
360 | ␊ |
361 | ␉if (p->CPU.NoCores == 0)␊ |
362 | ␉{␊ |
363 | ␉␉p->CPU.NoCores␉␉= (uint8_t)(p->CPU.CoresPerPackage & 0xff);␊ |
364 | ␉␉p->CPU.NoThreads␉= (uint8_t)(p->CPU.LogicalPerPackage & 0xff);␊ |
365 | ␉}␊ |
366 | ␊ |
367 | ␉/* get BrandString (if supported) */␊ |
368 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
369 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
370 | ␉{␊ |
371 | ␉␉char␉ *s;␊ |
372 | ␉␉bzero(str, 128);␊ |
373 | ␉␉/*␊ |
374 | ␉␉ * The BrandString 48 bytes (max), guaranteed to␊ |
375 | ␉␉ * be NULL terminated.␊ |
376 | ␉␉ */␊ |
377 | ␉␉do_cpuid(0x80000002, reg);␊ |
378 | ␉␉memcpy(&str[0], (char *)reg, 16);␊ |
379 | ␉␉do_cpuid(0x80000003, reg);␊ |
380 | ␉␉memcpy(&str[16], (char *)reg, 16);␊ |
381 | ␉␉do_cpuid(0x80000004, reg);␊ |
382 | ␉␉memcpy(&str[32], (char *)reg, 16);␊ |
383 | ␉␉for (s = str; *s != '\0'; s++)␊ |
384 | ␉␉{␊ |
385 | ␉␉␉if (*s != ' ')␊ |
386 | ␉␉␉{␊ |
387 | ␉␉␉␉break;␊ |
388 | ␉␉␉}␊ |
389 | ␉␉}␊ |
390 | ␉␉strlcpy(p->CPU.BrandString, s, 48);␊ |
391 | ␊ |
392 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
393 | ␉␉{␊ |
394 | ␉␉␉/*␊ |
395 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
396 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
397 | ␉␉␉ */␊ |
398 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
399 | ␉␉}␊ |
400 | ␉␉p->CPU.BrandString[47] = '\0';␊ |
401 | //␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊ |
402 | ␉}␊ |
403 | ␊ |
404 | ␉//workaround for N270. I don't know why it detected wrong␊ |
405 | ␉// MSR is *NOT* available on the Intel Atom CPU␊ |
406 | ␉if ((p->CPU.Model == CPU_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊ |
407 | ␉{␊ |
408 | ␉␉p->CPU.NoCores␉␉= 1;␊ |
409 | ␉␉p->CPU.NoThreads␉= 2;␊ |
410 | ␉}␊ |
411 | ␊ |
412 | ␉if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊ |
413 | ␉{␊ |
414 | ␉␉p->CPU.NoThreads␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
415 | ␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
416 | ␉}␊ |
417 | ␊ |
418 | ␉/* setup features */␊ |
419 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
420 | ␉{␊ |
421 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
422 | ␉}␊ |
423 | ␊ |
424 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
425 | ␉{␊ |
426 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
427 | ␉}␊ |
428 | ␊ |
429 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
430 | ␉{␊ |
431 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
432 | ␉}␊ |
433 | ␊ |
434 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
435 | ␉{␊ |
436 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
437 | ␉}␊ |
438 | ␊ |
439 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
440 | ␉{␊ |
441 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
442 | ␉}␊ |
443 | ␊ |
444 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
445 | ␉{␊ |
446 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
447 | ␉}␊ |
448 | ␊ |
449 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
450 | ␉{␊ |
451 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
452 | ␉}␊ |
453 | ␊ |
454 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
455 | ␉{␊ |
456 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
457 | ␉}␊ |
458 | ␊ |
459 | ␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
460 | ␊ |
461 | ␉if (p->CPU.NoThreads > p->CPU.NoCores)␊ |
462 | ␉{␊ |
463 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
464 | ␉}␊ |
465 | ␊ |
466 | ␉tscFrequency = measure_tsc_frequency();␊ |
467 | ␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊ |
468 | ␉/* if usual method failed */␊ |
469 | ␉if ( tscFrequency < 1000 )␉//TEST␊ |
470 | ␉{␊ |
471 | ␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊ |
472 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
473 | ␉} else {␊ |
474 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊ |
475 | ␉}␊ |
476 | ␊ |
477 | ␉fsbFrequency = 0;␊ |
478 | ␉cpuFrequency = 0;␊ |
479 | ␊ |
480 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))) {␊ |
481 | ␉␉int intelCPU = p->CPU.Model;␊ |
482 | ␉␉if (p->CPU.Family == 0x06) {␊ |
483 | ␉␉␉/* Nehalem CPU model */␊ |
484 | ␉␉␉switch (p->CPU.Model) {␊ |
485 | ␉␉␉␉case CPU_MODEL_NEHALEM:␊ |
486 | ␉␉␉␉case CPU_MODEL_FIELDS:␊ |
487 | ␉␉␉␉case CPU_MODEL_DALES:␊ |
488 | ␉␉␉␉case CPU_MODEL_DALES_32NM:␊ |
489 | ␉␉␉␉case CPU_MODEL_WESTMERE:␊ |
490 | ␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊ |
491 | ␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊ |
492 | /* --------------------------------------------------------- */␊ |
493 | ␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
494 | ␉␉␉␉case CPU_MODEL_JAKETOWN:␊ |
495 | ␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
496 | ␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
497 | ␉␉␉␉case CPU_MODEL_HASWELL:␊ |
498 | ␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊ |
499 | ␊ |
500 | ␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
501 | ␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
502 | /* --------------------------------------------------------- */␊ |
503 | ␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
504 | ␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
505 | ␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
506 | ␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
507 | ␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
508 | ␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
509 | ␉␉␉␉␉if (bitfield(msr, 16, 16))␊ |
510 | ␉␉␉␉␉{␊ |
511 | ␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
512 | ␉␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
513 | ␉␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
514 | ␉␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
515 | ␉␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
516 | ␉␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
517 | ␉␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
518 | ␉␉␉␉␉␉ is inadvertently set to 0.␊ |
519 | ␉␉␉␉␉␉ */␊ |
520 | ␉␉␉␉␉␉if (flex_ratio == 0)␊ |
521 | ␉␉␉␉␉␉{␊ |
522 | ␉␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
523 | ␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
524 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
525 | ␉␉␉␉␉␉␉DBG("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
526 | ␉␉␉␉␉␉}␊ |
527 | ␉␉␉␉␉␉else␊ |
528 | ␉␉␉␉␉␉{␊ |
529 | ␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
530 | ␉␉␉␉␉␉␉{␊ |
531 | ␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
532 | ␉␉␉␉␉␉␉}␊ |
533 | ␉␉␉␉␉␉}␊ |
534 | ␉␉␉␉␉}␊ |
535 | ␊ |
536 | ␉␉␉␉␉if (bus_ratio_max)␊ |
537 | ␉␉␉␉␉{␊ |
538 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
539 | ␉␉␉␉␉}␊ |
540 | ␊ |
541 | ␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
542 | ␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
543 | ␉␉␉␉␉{␊ |
544 | ␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
545 | ␊ |
546 | ␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
547 | ␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
548 | ␉␉␉␉␉}␊ |
549 | ␉␉␉␉␉else␊ |
550 | ␉␉␉␉␉{␊ |
551 | ␉␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
552 | ␉␉␉␉␉}␊ |
553 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
554 | ␉␉␉␉␉{␊ |
555 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
556 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
557 | ␉␉␉␉␉␉if (len >= 3)␊ |
558 | ␉␉␉␉␉␉{␊ |
559 | ␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
560 | ␉␉␉␉␉␉}␊ |
561 | ␊ |
562 | ␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
563 | ␊ |
564 | ␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
565 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
566 | ␉␉␉␉␉␉{␊ |
567 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
568 | ␉␉␉␉␉␉␉if (len >= 3)␊ |
569 | ␉␉␉␉␉␉␉{␊ |
570 | ␉␉␉␉␉␉␉␉maxdiv = 1;␊ |
571 | ␉␉␉␉␉␉␉}␊ |
572 | ␉␉␉␉␉␉␉else␊ |
573 | ␉␉␉␉␉␉␉{␊ |
574 | ␉␉␉␉␉␉␉␉maxdiv = 0;␊ |
575 | ␉␉␉␉␉␉␉}␊ |
576 | ␉␉␉␉␉␉}␊ |
577 | ␉␉␉␉␉␉else␊ |
578 | ␉␉␉␉␉␉{␊ |
579 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
580 | ␉␉␉␉␉␉}␊ |
581 | ␉␉␉␉␉}␊ |
582 | ␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
583 | ␉␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
584 | ␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
585 | ␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
586 | ␊ |
587 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
588 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
589 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
590 | ␊ |
591 | ␉␉␉␉break;␊ |
592 | ␊ |
593 | ␉␉␉default:␊ |
594 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
595 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
596 | ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
597 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
598 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
599 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
600 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
601 | ␊ |
602 | ␉␉␉␉// This will always be model >= 3␊ |
603 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
604 | ␉␉␉␉{␊ |
605 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
606 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
607 | ␉␉␉␉}␊ |
608 | ␉␉␉␉else␊ |
609 | ␉␉␉␉{␊ |
610 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
611 | ␉␉␉␉␉/* XXX */␊ |
612 | ␉␉␉␉␉maxcoef = currcoef;␊ |
613 | ␉␉␉␉}␊ |
614 | ␊ |
615 | ␉␉␉␉if (!currcoef)␊ |
616 | ␉␉␉␉{␊ |
617 | ␉␉␉␉␉currcoef = maxcoef;␊ |
618 | ␉␉␉␉}␊ |
619 | ␊ |
620 | ␉␉␉␉if (maxcoef)␊ |
621 | ␉␉␉␉{␊ |
622 | ␉␉␉␉␉if (maxdiv)␊ |
623 | ␉␉␉␉␉{␊ |
624 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
625 | ␉␉␉␉␉}␊ |
626 | ␉␉␉␉␉else␊ |
627 | ␉␉␉␉␉{␊ |
628 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
629 | ␉␉␉␉␉}␊ |
630 | ␊ |
631 | ␉␉␉␉␉if (currdiv)␊ |
632 | ␉␉␉␉␉{␊ |
633 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
634 | ␉␉␉␉␉}␊ |
635 | ␉␉␉␉␉else␊ |
636 | ␉␉␉␉␉{␊ |
637 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
638 | ␉␉␉␉␉}␊ |
639 | ␊ |
640 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
641 | ␉␉␉␉}␊ |
642 | ␉␉␉␉break;␊ |
643 | ␉␉␉}␊ |
644 | ␉␉}␊ |
645 | ␉␉/* Mobile CPU */␊ |
646 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
647 | ␉␉{␊ |
648 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
649 | ␉␉}␊ |
650 | ␉}␊ |
651 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
652 | ␉{␊ |
653 | ␉␉switch(p->CPU.ExtFamily)␊ |
654 | ␉␉{␊ |
655 | ␉␉␉case 0x00: /* K8 */␊ |
656 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
657 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
658 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
659 | ␉␉␉␉break;␊ |
660 | ␊ |
661 | ␉␉␉case 0x01: /* K10 */␊ |
662 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
663 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
664 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
665 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
666 | ␉␉␉␉{␊ |
667 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
668 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
669 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
670 | ␉␉␉␉}␊ |
671 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
672 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
673 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
674 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
675 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
676 | ␊ |
677 | ␉␉␉␉break;␊ |
678 | ␊ |
679 | ␉␉␉case 0x05: /* K14 */␊ |
680 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
681 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
682 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
683 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
684 | ␊ |
685 | ␉␉␉␉break;␊ |
686 | ␊ |
687 | ␉␉␉case 0x02: /* K11 */␊ |
688 | ␉␉␉␉// not implimented␊ |
689 | ␉␉␉␉break;␊ |
690 | ␉␉}␊ |
691 | ␊ |
692 | ␉␉if (maxcoef)␊ |
693 | ␉␉{␊ |
694 | ␉␉␉if (currdiv)␊ |
695 | ␉␉␉{␊ |
696 | ␉␉␉␉if (!currcoef)␊ |
697 | ␉␉␉␉{␊ |
698 | ␉␉␉␉␉currcoef = maxcoef;␊ |
699 | ␉␉␉␉}␊ |
700 | ␊ |
701 | ␉␉␉␉if (!cpuFrequency)␊ |
702 | ␉␉␉␉{␊ |
703 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
704 | ␉␉␉␉}␊ |
705 | ␉␉␉␉else␊ |
706 | ␉␉␉␉{␊ |
707 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
708 | ␉␉␉␉}␊ |
709 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
710 | ␉␉␉}␊ |
711 | ␉␉␉else␊ |
712 | ␉␉␉{␊ |
713 | ␉␉␉␉if (!cpuFrequency)␊ |
714 | ␉␉␉␉{␊ |
715 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
716 | ␉␉␉␉}␊ |
717 | ␉␉␉␉else␊ |
718 | ␉␉␉␉{␊ |
719 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
720 | ␉␉␉␉}␊ |
721 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
722 | ␉␉␉}␊ |
723 | ␉␉}␊ |
724 | ␉␉else if (currcoef)␊ |
725 | ␉␉{␊ |
726 | ␉␉␉if (currdiv)␊ |
727 | ␉␉␉{␊ |
728 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
729 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
730 | ␉␉␉}␊ |
731 | ␉␉␉else␊ |
732 | ␉␉␉{␊ |
733 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
734 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
735 | ␉␉␉}␊ |
736 | ␉␉}␊ |
737 | ␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊ |
738 | ␉}␊ |
739 | ␉␊ |
740 | #if 0␊ |
741 | ␉if (!fsbFrequency)␊ |
742 | ␉{␊ |
743 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
744 | ␉␉cpuFrequency = tscFrequency;␊ |
745 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
746 | ␉}␊ |
747 | ␊ |
748 | ␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
749 | ␊ |
750 | #endif␊ |
751 | ␊ |
752 | ␉p->CPU.MaxCoef = maxcoef;␊ |
753 | ␉p->CPU.MaxDiv = maxdiv;␊ |
754 | ␉p->CPU.CurrCoef = currcoef;␊ |
755 | ␉p->CPU.CurrDiv = currdiv;␊ |
756 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
757 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
758 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
759 | ␊ |
760 | ␉// keep formatted with spaces instead of tabs␊ |
761 | ␉DBG("\n---------------------------------------------\n");␊ |
762 | ␉DBG("------------------ CPU INFO -----------------\n");␊ |
763 | ␉DBG("---------------------------------------------\n");␊ |
764 | ␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString); // Processor name (BIOS)␊ |
765 | ␉DBG("Vendor: 0x%x\n",␉␉p->CPU.Vendor); // Vendor ex: GenuineIntel␊ |
766 | ␉DBG("Family: 0x%x\n",␉␉p->CPU.Family); // Family ex: 6 (06h)␊ |
767 | ␉DBG("ExtFamily: 0x%x\n",␉␉p->CPU.ExtFamily);␊ |
768 | ␉DBG("Signature: %x\n",␉␉p->CPU.Signature); // CPUID signature␊ |
769 | ␉DBG("Model: 0x%x\n",␉␉p->CPU.Model); // Model ex: 37 (025h)␊ |
770 | ␉DBG("ExtModel: 0x%x\n",␉␉p->CPU.ExtModel);␊ |
771 | ␉DBG("Stepping: 0x%x\n",␉␉p->CPU.Stepping); // Stepping ex: 5 (05h)␊ |
772 | ␉DBG("MaxCoef: 0x%x\n",␉␉p->CPU.MaxCoef);␊ |
773 | ␉DBG("CurrCoef: 0x%x\n",␉␉p->CPU.CurrCoef);␊ |
774 | ␉DBG("MaxDiv: 0x%x\n",␉␉p->CPU.MaxDiv);␊ |
775 | ␉DBG("CurrDiv: 0x%x\n",␉␉p->CPU.CurrDiv);␊ |
776 | ␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊ |
777 | ␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊ |
778 | ␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊ |
779 | ␉DBG("Cores: %d\n",␉␉p->CPU.NoCores); // Cores␊ |
780 | ␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads); // Logical procesor␊ |
781 | ␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊ |
782 | ␊ |
783 | ␉DBG("\n---------------------------------------------\n");␊ |
784 | #if DEBUG_CPU␊ |
785 | ␉pause();␊ |
786 | #endif␊ |
787 | }␊ |
788 | |