1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
25 | ␉{␊ |
26 | ␉␉switch (Platform.CPU.Family)␊ |
27 | ␉␉{␊ |
28 | ␉␉␉case 0x06:␊ |
29 | ␉␉␉{␊ |
30 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
31 | ␉␉␉␉{␊ |
32 | ␉␉␉␉␉␉// set external clock to 0 for SANDY␊ |
33 | ␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
34 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊ |
36 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
37 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
38 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
39 | ␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊ |
40 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
41 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
42 | ␊ |
43 | ␉␉␉␉␉␉value->word = 0;␊ |
44 | ␉␉␉␉␉␉break;␊ |
45 | ␉␉␉␉␉default:␊ |
46 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
47 | ␉␉␉␉}␊ |
48 | ␉␉␉}␊ |
49 | ␉␉␉␉break;␊ |
50 | ␊ |
51 | ␉␉␉default:␊ |
52 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
53 | ␉␉}␊ |
54 | ␉}␊ |
55 | ␉else␊ |
56 | ␉{␊ |
57 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
58 | ␉}␊ |
59 | ␊ |
60 | ␉return true;␊ |
61 | }␊ |
62 | ␊ |
63 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
64 | {␊ |
65 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
66 | ␉return true;␊ |
67 | }␊ |
68 | ␊ |
69 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
70 | {␊ |
71 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
72 | ␉{␊ |
73 | ␉␉switch (Platform.CPU.Family)␊ |
74 | ␉␉{␊ |
75 | ␉␉␉case 0x06:␊ |
76 | ␉␉␉{␊ |
77 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
78 | ␉␉␉␉{␊ |
79 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
80 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
81 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
82 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
83 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
84 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
85 | ␉␉␉␉␉␉return false;␊ |
86 | ␊ |
87 | ␉␉␉␉␉case 0x19:␊ |
88 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
89 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
90 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
91 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
92 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
93 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
94 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
95 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
96 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
97 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
98 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
99 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
100 | ␉␉␉␉␉{␊ |
101 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
102 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
103 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
104 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
105 | ␉␉␉␉␉␉unsigned int i;␊ |
106 | ␉␉␉␉␉␉␊ |
107 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
108 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
109 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊ |
110 | ␉␉␉␉␉␉{␊ |
111 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
112 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
113 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
114 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
115 | ␉␉␉␉␉␉␉␊ |
116 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
117 | ␉␉␉␉␉␉␉{␊ |
118 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊ |
119 | ␉␉␉␉␉␉␉}␊ |
120 | ␉␉␉␉␉␉}␊ |
121 | ␊ |
122 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
123 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
124 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
125 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
126 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
127 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
128 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
129 | ␉␉␉␉␉␉{␊ |
130 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
131 | ␉␉␉␉␉␉}␊ |
132 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
133 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
134 | ␉␉␉␉␉␉return true;␊ |
135 | ␉␉␉␉␉}␊ |
136 | ␉␉␉␉␉default:␊ |
137 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
138 | ␉␉␉␉}␊ |
139 | ␉␉␉}␊ |
140 | ␉␉␉default:␊ |
141 | ␉␉␉␉break;␊ |
142 | ␉␉}␊ |
143 | ␉}␊ |
144 | ␉return false;␊ |
145 | }␊ |
146 | ␊ |
147 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
148 | {␊ |
149 | ␉if (Platform.CPU.NoCores >= 4)␊ |
150 | ␉{␊ |
151 | ␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊ |
152 | ␉}␊ |
153 | ␉else if (Platform.CPU.NoCores == 1)␊ |
154 | ␉{␊ |
155 | ␉␉return 0x201;␉// 513 - Core Duo␊ |
156 | ␉};␊ |
157 | ␉␊ |
158 | ␉return 0x301;␉␉// 769 - Core 2 Duo␊ |
159 | }␊ |
160 | ␊ |
161 | bool getSMBOemProcessorType(returnType *value)␊ |
162 | {␊ |
163 | ␉static bool done = false;␊ |
164 | ␊ |
165 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
166 | ␊ |
167 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
168 | ␉{␊ |
169 | ␉␉if (!done)␊ |
170 | ␉␉{␊ |
171 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
172 | ␉␉␉done = true;␊ |
173 | ␉␉}␊ |
174 | ␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊ |
175 | ␉␉switch (Platform.CPU.Family)␊ |
176 | ␉␉{␊ |
177 | ␉␉␉case 0x0F:␊ |
178 | ␉␉␉case 0x06:␊ |
179 | ␉␉␉{␊ |
180 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
181 | ␉␉␉␉{␊ |
182 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
183 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊ |
184 | ␉␉␉␉␉case CPU_MODEL_PRESCOTT:␊ |
185 | ␉␉␉␉␉case CPU_MODEL_NOCONA:␊ |
186 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
187 | ␉␉␉␉␉␉{␊ |
188 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
189 | ␉␉␉␉␉␉}␊ |
190 | ␉␉␉␉␉␉return true;␊ |
191 | ␊ |
192 | ␉␉␉␉␉case CPU_MODEL_PRESLER:␊ |
193 | ␉␉␉␉␉case CPU_MODEL_CELERON:␊ |
194 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
195 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
196 | ␉␉␉␉␉␉return true;␊ |
197 | ␊ |
198 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
199 | ␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
200 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
201 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
202 | ␉␉␉␉␉␉{␊ |
203 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
204 | ␉␉␉␉␉␉return true;␊ |
205 | ␉␉␉␉␉␉}␊ |
206 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
207 | ␉␉␉␉␉␉{␊ |
208 | ␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊ |
209 | ␉␉␉␉␉␉} else {␊ |
210 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊ |
211 | ␉␉␉␉␉␉}␊ |
212 | ␉␉␉␉␉␉return true;␊ |
213 | ␊ |
214 | ␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
215 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
216 | ␉␉␉␉␉␉return true;␊ |
217 | ␊ |
218 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊ |
219 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
220 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
221 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
222 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊ |
223 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
224 | ␉␉␉␉␉␉␉return true;␊ |
225 | ␉␉␉␉␉␉}␊ |
226 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
227 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
228 | ␉␉␉␉␉␉␉return true;␊ |
229 | ␉␉␉␉␉␉}␊ |
230 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
231 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
232 | ␉␉␉␉␉␉␉return true;␊ |
233 | ␉␉␉␉␉␉}␊ |
234 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
235 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
236 | ␉␉␉␉␉␉␉return true;␊ |
237 | ␉␉␉␉␉␉}␊ |
238 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
239 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊ |
240 | ␉␉␉␉␉␉}␊ |
241 | ␉␉␉␉␉␉return true;␊ |
242 | ␊ |
243 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
244 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
245 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
246 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊ |
247 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
248 | ␉␉␉␉␉␉␉return true;␊ |
249 | ␉␉␉␉␉␉}␊ |
250 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
251 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
252 | ␉␉␉␉␉␉␉return true;␊ |
253 | ␉␉␉␉␉␉}␊ |
254 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
255 | ␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊ |
256 | ␉␉␉␉␉␉␉return true;␊ |
257 | ␉␉␉␉␉␉}␊ |
258 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
259 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
260 | ␉␉␉␉␉␉␉return true;␊ |
261 | ␉␉␉␉␉␉}␊ |
262 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
263 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊ |
264 | ␉␉␉␉␉␉}␊ |
265 | ␉␉␉␉␉␉return true;␊ |
266 | ␊ |
267 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
268 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
269 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊ |
270 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
271 | ␉␉␉␉␉␉␉return true;␊ |
272 | ␉␉␉␉␉␉}␊ |
273 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
274 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
275 | ␉␉␉␉␉␉␉return true;␊ |
276 | ␉␉␉␉␉␉}␊ |
277 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
278 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
279 | ␉␉␉␉␉␉␉return true;␊ |
280 | ␉␉␉␉␉␉}␊ |
281 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
282 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
283 | ␉␉␉␉␉␉␉return true;␊ |
284 | ␉␉␉␉␉␉}␊ |
285 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
286 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊ |
287 | ␉␉␉␉␉␉}␊ |
288 | ␉␉␉␉␉␉return true;␊ |
289 | ␊ |
290 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
291 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊ |
292 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
293 | ␉␉␉␉␉␉␉return true;␊ |
294 | ␉␉␉␉␉␉}␊ |
295 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
296 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊ |
297 | ␉␉␉␉␉␉␉return true;␊ |
298 | ␉␉␉␉␉␉}␊ |
299 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
300 | ␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊ |
301 | ␉␉␉␉␉␉␉return true;␊ |
302 | ␉␉␉␉␉␉}␊ |
303 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
304 | ␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊ |
305 | ␉␉␉␉␉␉␉return true;␊ |
306 | ␉␉␉␉␉␉}␊ |
307 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
308 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊ |
309 | ␉␉␉␉␉␉}␊ |
310 | ␉␉␉␉␉␉return true;␊ |
311 | ␊ |
312 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊ |
313 | ␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
314 | ␉␉␉␉␉␉return true;␊ |
315 | ␊ |
316 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊ |
317 | ␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊ |
318 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
319 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊ |
320 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon")) {␊ |
321 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
322 | ␉␉␉␉␉␉␉return true;␊ |
323 | ␉␉␉␉␉␉}␊ |
324 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
325 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
326 | ␉␉␉␉␉␉␉return true;␊ |
327 | ␉␉␉␉␉␉}␊ |
328 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
329 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
330 | ␉␉␉␉␉␉␉return true;␊ |
331 | ␉␉␉␉␉␉}␊ |
332 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
333 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
334 | ␉␉␉␉␉␉␉return true;␊ |
335 | ␉␉␉␉␉␉}␊ |
336 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
337 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊ |
338 | ␉␉␉␉␉␉}␊ |
339 | ␉␉␉␉␉␉return true;␊ |
340 | ␊ |
341 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
342 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
343 | ␉␉␉␉␉␉return true;␊ |
344 | ␊ |
345 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
346 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
347 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
348 | ␉␉␉␉␉␉return true;␊ |
349 | ␉␉␉␉␉default:␊ |
350 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
351 | ␉␉␉␉}␊ |
352 | ␉␉␉}␊ |
353 | ␉␉␉default:␊ |
354 | ␉␉␉␉break;␊ |
355 | ␉␉}␊ |
356 | ␉}␊ |
357 | ␉␊ |
358 | ␉return false;␊ |
359 | }␊ |
360 | ␊ |
361 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
362 | {␊ |
363 | ␉static int idx = -1;␊ |
364 | ␉int␉map;␊ |
365 | ␊ |
366 | ␉if (!bootInfo->memDetect)␊ |
367 | ␉{␊ |
368 | ␉␉return false;␊ |
369 | ␉}␊ |
370 | ␊ |
371 | ␉idx++;␊ |
372 | ␉if (idx < MAX_RAM_SLOTS)␊ |
373 | ␉{␊ |
374 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
375 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
376 | ␉␉{␊ |
377 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
378 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
379 | ␉␉␉return true;␊ |
380 | ␉␉}␊ |
381 | ␉}␊ |
382 | ␊ |
383 | ␉value->byte = 2; // means Unknown␊ |
384 | ␉return true;␊ |
385 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
386 | //␉return true;␊ |
387 | }␊ |
388 | ␊ |
389 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
390 | {␊ |
391 | ␉value->word = 0xFFFF;␊ |
392 | ␉return true;␊ |
393 | }␊ |
394 | ␊ |
395 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
396 | {␊ |
397 | ␉static int idx = -1;␊ |
398 | ␉int␉map;␊ |
399 | ␊ |
400 | ␉if (!bootInfo->memDetect) {␊ |
401 | ␉␉return false;␊ |
402 | ␉}␊ |
403 | ␊ |
404 | ␉idx++;␊ |
405 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
406 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
407 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊ |
408 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
409 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
410 | ␉␉␉return true;␊ |
411 | ␉␉}␊ |
412 | ␉}␊ |
413 | ␊ |
414 | ␉value->dword = 0; // means Unknown␊ |
415 | ␉return true;␊ |
416 | //␉value->dword = 800;␊ |
417 | //␉return true;␊ |
418 | }␊ |
419 | ␊ |
420 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
421 | {␊ |
422 | ␉static int idx = -1;␊ |
423 | ␉int␉map;␊ |
424 | ␊ |
425 | ␉if (!bootInfo->memDetect) {␊ |
426 | ␉␉return false;␊ |
427 | ␉}␊ |
428 | ␊ |
429 | ␉idx++;␊ |
430 | ␉if (idx < MAX_RAM_SLOTS)␊ |
431 | ␉{␊ |
432 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
433 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
434 | ␉␉{␊ |
435 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
436 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
437 | ␉␉␉return true;␊ |
438 | ␉␉}␊ |
439 | ␉}␊ |
440 | ␊ |
441 | ␉value->string = NOT_AVAILABLE;␊ |
442 | ␉return true;␊ |
443 | }␊ |
444 | ␊ |
445 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
446 | {␊ |
447 | ␉static int idx = -1;␊ |
448 | ␉int␉map;␊ |
449 | ␊ |
450 | ␉if (!bootInfo->memDetect) {␊ |
451 | ␉␉return false;␊ |
452 | ␉}␊ |
453 | ␊ |
454 | ␉idx++;␊ |
455 | ␊ |
456 | ␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
457 | ␊ |
458 | ␉if (idx < MAX_RAM_SLOTS)␊ |
459 | ␉{␊ |
460 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
461 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
462 | ␉␉{␊ |
463 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
464 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
465 | ␉␉␉return true;␊ |
466 | ␉␉}␊ |
467 | ␉}␊ |
468 | ␊ |
469 | ␉value->string = NOT_AVAILABLE;␊ |
470 | ␉return true;␊ |
471 | }␊ |
472 | ␊ |
473 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
474 | {␊ |
475 | ␉static int idx = -1;␊ |
476 | ␉int␉map;␊ |
477 | ␊ |
478 | ␉if (!bootInfo->memDetect) {␊ |
479 | ␉␉return false;␊ |
480 | ␉}␊ |
481 | ␊ |
482 | ␉idx++;␊ |
483 | ␉if (idx < MAX_RAM_SLOTS)␊ |
484 | ␉{␊ |
485 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
486 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
487 | ␉␉{␊ |
488 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
489 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
490 | ␉␉␉return true;␊ |
491 | ␉␉}␊ |
492 | ␉}␊ |
493 | ␊ |
494 | ␉value->string = NOT_AVAILABLE;␊ |
495 | ␉return true;␊ |
496 | }␊ |
497 | ␊ |
498 | ␊ |
499 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
500 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
501 | static const char * const SMTAG = "_SM_";␊ |
502 | static const char* const DMITAG = "_DMI_";␊ |
503 | ␊ |
504 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
505 | {␊ |
506 | ␉SMBEntryPoint␉*smbios;␊ |
507 | ␉/*␊ |
508 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
509 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
510 | ␉ */␊ |
511 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
512 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊ |
513 | ␉{␊ |
514 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
515 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
516 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
517 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
518 | ␉␉{␊ |
519 | ␉␉␉return smbios;␊ |
520 | ␉ }␊ |
521 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
522 | ␉}␊ |
523 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
524 | ␉pause();␊ |
525 | ␉return NULL;␊ |
526 | }␊ |
527 | ␊ |
528 | |