1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | */␊ |
5 | ␊ |
6 | #include "libsaio.h"␊ |
7 | #include "platform.h"␊ |
8 | #include "cpu.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | #include "boot.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_CPU␊ |
13 | #define DEBUG_CPU 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_CPU␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␉␉msglog(x)␊ |
20 | #endif␊ |
21 | ␊ |
22 | /*␊ |
23 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
24 | */␊ |
25 | static uint64_t measure_tsc_frequency(void)␊ |
26 | {␊ |
27 | ␉uint64_t tscStart;␊ |
28 | ␉uint64_t tscEnd;␊ |
29 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
30 | ␉unsigned long pollCount;␊ |
31 | ␉uint64_t retval = 0;␊ |
32 | ␉int i;␊ |
33 | ␊ |
34 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
35 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
36 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
37 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
38 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
39 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
40 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
41 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
42 | ␉ */␊ |
43 | ␉for(i = 0; i < 10; ++i)␊ |
44 | ␉{␊ |
45 | ␉␉enable_PIT2();␊ |
46 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
47 | ␉␉tscStart = rdtsc64();␊ |
48 | ␉␉pollCount = poll_PIT2_gate();␊ |
49 | ␉␉tscEnd = rdtsc64();␊ |
50 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
51 | ␉␉if (pollCount <= 1)␊ |
52 | ␉␉{␊ |
53 | ␉␉␉continue;␊ |
54 | ␉␉}␊ |
55 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
56 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
57 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
58 | ␉␉ */␊ |
59 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
60 | ␉␉{␊ |
61 | ␉␉␉continue;␊ |
62 | ␉␉}␊ |
63 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
64 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
65 | ␉␉{␊ |
66 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
67 | ␉␉}␊ |
68 | ␉}␊ |
69 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
70 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
71 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
72 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
73 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
74 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
75 | ␉ */␊ |
76 | ␊ |
77 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
78 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
79 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
80 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
81 | ␉ */␊ |
82 | ␉if (tscDelta > (1ULL<<32))␊ |
83 | ␉{␊ |
84 | ␉␉retval = 0;␊ |
85 | ␉}␊ |
86 | ␉else␊ |
87 | ␉{␊ |
88 | ␉␉retval = tscDelta * 1000 / 30;␊ |
89 | ␉}␊ |
90 | ␉disable_PIT2();␊ |
91 | ␉return retval;␊ |
92 | }␊ |
93 | ␊ |
94 | /*␊ |
95 | * timeRDTSC()␊ |
96 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
97 | * It pauses until the value is latched in the counter␊ |
98 | * and then reads the time stamp counter to return to the caller.␊ |
99 | */␊ |
100 | static uint64_t timeRDTSC(void)␊ |
101 | {␊ |
102 | ␉int␉␉attempts = 0;␊ |
103 | ␉uint64_t latchTime;␊ |
104 | ␉uint64_t␉saveTime,intermediate;␊ |
105 | ␉unsigned int timerValue, lastValue;␊ |
106 | ␉//boolean_t␉int_enabled;␊ |
107 | ␉/*␊ |
108 | ␉ * Table of correction factors to account for␊ |
109 | ␉ *␉ - timer counter quantization errors, and␊ |
110 | ␉ *␉ - undercounts 0..5␊ |
111 | ␉ */␊ |
112 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
113 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
114 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
115 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
116 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
117 | ␉uint64_t␉scale[6] = {␊ |
118 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
119 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
120 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
121 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
122 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
123 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
124 | ␉};␊ |
125 | ␊ |
126 | ␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊ |
127 | ␊ |
128 | restart:␊ |
129 | ␉if (attempts >= 9) // increase to up to 9 attempts.␊ |
130 | ␉{␊ |
131 | ␉ // This will flash-reboot. TODO: Use tscPanic instead.␊ |
132 | ␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
133 | ␉}␊ |
134 | ␉attempts++;␊ |
135 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
136 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
137 | ␉latchTime = rdtsc64();␉// get the time stamp to time ␊ |
138 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
139 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
140 | ␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
141 | ␉get_PIT2(&lastValue);␊ |
142 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
143 | ␉do {␊ |
144 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
145 | ␉␉if (timerValue > lastValue)␊ |
146 | ␉␉{␊ |
147 | ␉␉␉// Timer wrapped␊ |
148 | ␉␉␉set_PIT2(0);␊ |
149 | ␉␉␉disable_PIT2();␊ |
150 | ␉␉␉goto restart;␊ |
151 | ␉␉}␊ |
152 | ␉␉lastValue = timerValue;␊ |
153 | ␉} while (timerValue > 5);␊ |
154 | ␉printf("timerValue␉ %d\n",timerValue);␊ |
155 | ␉printf("intermediate 0x%016llx\n",intermediate);␊ |
156 | ␉printf("saveTime␉ 0x%016llx\n",saveTime);␊ |
157 | ␊ |
158 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
159 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
160 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
161 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
162 | ␊ |
163 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
164 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
165 | ␊ |
166 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
167 | ␉return intermediate;␊ |
168 | }␊ |
169 | ␊ |
170 | /*␊ |
171 | * Original comment/code:␊ |
172 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
173 | *␊ |
174 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
175 | * (just a naming change, mperf --> aperf )␊ |
176 | */␊ |
177 | static uint64_t measure_aperf_frequency(void)␊ |
178 | {␊ |
179 | ␉uint64_t aperfStart;␊ |
180 | ␉uint64_t aperfEnd;␊ |
181 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
182 | ␉unsigned long pollCount;␊ |
183 | ␉uint64_t retval = 0;␊ |
184 | ␉int i;␊ |
185 | ␊ |
186 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
187 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
188 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
189 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
190 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
191 | ␉ * expire.␊ |
192 | ␉ */␊ |
193 | ␉for(i = 0; i < 10; ++i)␊ |
194 | ␉{␊ |
195 | ␉␉enable_PIT2();␊ |
196 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
197 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
198 | ␉␉pollCount = poll_PIT2_gate();␊ |
199 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
200 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
201 | ␉␉if (pollCount <= 1)␊ |
202 | ␉␉{␊ |
203 | ␉␉␉continue;␊ |
204 | ␉␉}␊ |
205 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
206 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
207 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
208 | ␉␉ */␊ |
209 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
210 | ␉␉{␊ |
211 | ␉␉␉continue;␊ |
212 | ␉␉}␊ |
213 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
214 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
215 | ␉␉{␊ |
216 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
217 | ␉␉}␊ |
218 | ␉}␊ |
219 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
220 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
221 | ␉ */␊ |
222 | ␊ |
223 | ␉if (aperfDelta > (1ULL<<32))␊ |
224 | ␉{␊ |
225 | ␉␉retval = 0;␊ |
226 | ␉}␊ |
227 | ␉else␊ |
228 | ␉{␊ |
229 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
230 | ␉}␊ |
231 | ␉disable_PIT2();␊ |
232 | ␉return retval;␊ |
233 | }␊ |
234 | ␊ |
235 | /*␊ |
236 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
237 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
238 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
239 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
240 | * - fsbFrequency = tscFrequency / multi␊ |
241 | * - cpuFrequency = fsbFrequency * multi␊ |
242 | */␊ |
243 | void scan_cpu(PlatformInfo_t *p)␊ |
244 | {␊ |
245 | ␉uint64_t␉tscFrequency = 0;␊ |
246 | ␉uint64_t␉fsbFrequency = 0;␊ |
247 | ␉uint64_t␉cpuFrequency = 0;␊ |
248 | ␉uint64_t␉msr = 0;␊ |
249 | ␉uint64_t␉flex_ratio = 0;␊ |
250 | ␊ |
251 | ␉uint32_t␉max_ratio = 0;␊ |
252 | ␉uint32_t␉min_ratio = 0;␊ |
253 | ␉uint8_t␉␉bus_ratio_max = 0;␊ |
254 | ␉uint8_t␉␉bus_ratio_min = 0;␊ |
255 | ␉uint8_t␉␉currdiv = 0;␊ |
256 | ␉uint8_t␉␉currcoef = 0;␊ |
257 | ␉uint8_t␉␉maxdiv = 0;␊ |
258 | ␉uint8_t␉␉maxcoef = 0;␊ |
259 | ␉const char␉*newratio;␊ |
260 | ␉int␉␉len = 0;␊ |
261 | ␉int␉␉myfsb = 0;␊ |
262 | ␊ |
263 | ␉/* get cpuid values */␊ |
264 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊ |
265 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊ |
266 | ␊ |
267 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊ |
268 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊ |
269 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
270 | ␊ |
271 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
272 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␊ |
273 | ␉{␊ |
274 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
275 | ␉}␊ |
276 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␊ |
277 | ␉{␊ |
278 | ␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
279 | ␉}␊ |
280 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
281 | ␉{␊ |
282 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
283 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
284 | ␉}␊ |
285 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
286 | ␉{␊ |
287 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
288 | ␉}␊ |
289 | ␊ |
290 | // #if DEBUG_CPU␊ |
291 | ␉{␊ |
292 | ␉␉int␉␉i;␊ |
293 | ␉␉DBG("CPUID Raw Values:\n");␊ |
294 | ␉␉for (i = 0; i < CPUID_MAX; i++) {␊ |
295 | ␉␉␉DBG("%02d: %08x-%08x-%08x-%08x\n", i,␊ |
296 | ␉␉␉␉ p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊ |
297 | ␉␉␉␉ p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊ |
298 | ␉␉}␊ |
299 | ␉}␊ |
300 | // #endif␊ |
301 | ␊ |
302 | /* http://www.flounder.com/cpuid_explorer2.htm␊ |
303 | EAX (Intel):␊ |
304 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
305 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
306 | |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊ |
307 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
308 | ␊ |
309 | EAX (AMD):␊ |
310 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
311 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
312 | |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊ |
313 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
314 | */␊ |
315 | ␉p->CPU.MCodeVersion␉= (uint32_t)(rdmsr64(MSR_IA32_BIOS_SIGN_ID) >> 32);␊ |
316 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
317 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
318 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0); // stepping = cpu_feat_eax & 0xF;␊ |
319 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4); // model = (cpu_feat_eax >> 4) & 0xF;␊ |
320 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8); // family = (cpu_feat_eax >> 8) & 0xF;␊ |
321 | ␉//p->CPU.Type␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
322 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16); // ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
323 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
324 | ␊ |
325 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
326 | ␊ |
327 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊ |
328 | ␉␉p->CPU.Family == 0x06 &&␊ |
329 | ␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊ |
330 | ␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
331 | ␉␉)␊ |
332 | ␉{␊ |
333 | ␉␉/*␊ |
334 | ␉␉ * Find the number of enabled cores and threads␊ |
335 | ␉␉ * (which determines whether SMT/Hyperthreading is active).␊ |
336 | ␉␉ */␊ |
337 | ␉␉switch (p->CPU.Model)␊ |
338 | ␉␉{␊ |
339 | ␉␉␉case CPUID_MODEL_NEHALEM:␊ |
340 | ␉␉␉case CPUID_MODEL_FIELDS:␊ |
341 | ␉␉␉case CPUID_MODEL_DALES:␊ |
342 | ␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
343 | ␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
344 | ␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
345 | ␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
346 | ␉␉␉case CPUID_MODEL_HASWELL:␊ |
347 | ␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
348 | ␉␉␉//case CPUID_MODEL_HASWELL_H:␊ |
349 | ␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
350 | ␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
351 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
352 | ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 31, 16);␊ |
353 | ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
354 | ␉␉␉␉break;␊ |
355 | ␊ |
356 | ␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
357 | ␉␉␉case CPUID_MODEL_WESTMERE:␊ |
358 | ␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
359 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
360 | ␉␉␉␉p->CPU.NoCores␉␉= (uint8_t)bitfield((uint32_t)msr, 19, 16);␊ |
361 | ␉␉␉␉p->CPU.NoThreads␉= (uint8_t)bitfield((uint32_t)msr, 15, 0);␊ |
362 | ␉␉␉␉break;␊ |
363 | ␊ |
364 | ␉␉␉default:␊ |
365 | ␉␉␉␉p->CPU.NoCores = bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
366 | ␉␉␉␉p->CPU.NoThreads = (uint8_t)(p->CPU.LogicalPerPackage & 0xff);␊ |
367 | ␉␉␉␉//workaround for N270. I don't know why it detected wrong␊ |
368 | ␉␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (p->CPU.Stepping == 2))␊ |
369 | ␉␉␉␉{␊ |
370 | ␉␉␉␉␉p->CPU.NoCores = 1;␊ |
371 | ␉␉␉␉}␊ |
372 | ␉␉␉␉break;␊ |
373 | ␊ |
374 | ␉␉} // end switch␊ |
375 | ␊ |
376 | ␉}␊ |
377 | ␉else if (p->CPU.Vendor == CPUID_VENDOR_AMD)␊ |
378 | ␉{␊ |
379 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
380 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
381 | ␉}␊ |
382 | ␉else␊ |
383 | ␉{␊ |
384 | ␉␉// Use previous method for Cores and Threads␊ |
385 | ␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
386 | ␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊ |
387 | ␉}␊ |
388 | ␊ |
389 | ␉/* get BrandString (if supported) */␊ |
390 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
391 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
392 | ␉{␊ |
393 | ␉␉uint32_t␉reg[4];␊ |
394 | ␉␉char␉␉str[128], *s;␊ |
395 | ␉␉/*␊ |
396 | ␉␉ * The BrandString 48 bytes (max), guaranteed to␊ |
397 | ␉␉ * be NULL terminated.␊ |
398 | ␉␉ */␊ |
399 | ␉␉do_cpuid(0x80000002, reg);␊ |
400 | ␉␉bcopy((char *)reg, &str[0], 16);␊ |
401 | ␉␉do_cpuid(0x80000003, reg);␊ |
402 | ␉␉bcopy((char *)reg, &str[16], 16);␊ |
403 | ␉␉do_cpuid(0x80000004, reg);␊ |
404 | ␉␉bcopy((char *)reg, &str[32], 16);␊ |
405 | ␉␉for (s = str; *s != '\0'; s++)␊ |
406 | ␉␉{␊ |
407 | ␉␉␉if (*s != ' ')␊ |
408 | ␉␉␉{␊ |
409 | ␉␉␉␉break;␊ |
410 | ␉␉␉}␊ |
411 | ␉␉}␊ |
412 | ␊ |
413 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
414 | ␉␉{␊ |
415 | ␉␉␉/*␊ |
416 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
417 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
418 | ␉␉␉ */␊ |
419 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
420 | ␉␉}␊ |
421 | ␉}␊ |
422 | ␊ |
423 | ␉/* setup features */␊ |
424 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
425 | ␉{␊ |
426 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
427 | ␉}␊ |
428 | ␊ |
429 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
430 | ␉{␊ |
431 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
432 | ␉}␊ |
433 | ␊ |
434 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
435 | ␉{␊ |
436 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
437 | ␉}␊ |
438 | ␊ |
439 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
440 | ␉{␊ |
441 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
442 | ␉}␊ |
443 | ␊ |
444 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
445 | ␉{␊ |
446 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
447 | ␉}␊ |
448 | ␊ |
449 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
450 | ␉{␊ |
451 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
452 | ␉}␊ |
453 | ␊ |
454 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
455 | ␉{␊ |
456 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
457 | ␉}␊ |
458 | ␊ |
459 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
460 | ␉{␊ |
461 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
462 | ␉}␊ |
463 | ␊ |
464 | ␉//if ((bit(28) & p->CPU.CPUID[CPUID_1][3]) != 0) {␊ |
465 | ␊ |
466 | ␉if (p->CPU.NoThreads > p->CPU.NoCores)␊ |
467 | ␉{␊ |
468 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
469 | ␉}␊ |
470 | ␊ |
471 | ␉tscFrequency = measure_tsc_frequency();␊ |
472 | ␉DBG("cpu freq classic = 0x%016llx\n", tscFrequency);␊ |
473 | ␉/* if usual method failed */␊ |
474 | ␉if ( tscFrequency < 1000 )␉//TEST␊ |
475 | ␉{␊ |
476 | ␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊ |
477 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
478 | ␉}␊ |
479 | ␉else␊ |
480 | ␉{␊ |
481 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊ |
482 | ␉}␊ |
483 | ␊ |
484 | ␉fsbFrequency = 0;␊ |
485 | ␉cpuFrequency = 0;␊ |
486 | ␊ |
487 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f)))␊ |
488 | ␉{␊ |
489 | ␉␉int intelCPU = p->CPU.Model;␊ |
490 | ␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03))␊ |
491 | ␉␉{␊ |
492 | ␉␉␉/* Nehalem CPU model */␊ |
493 | ␉␉␉switch (p->CPU.Model)␊ |
494 | ␉␉␉{␊ |
495 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
496 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
497 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
498 | ␉␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
499 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
500 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
501 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
502 | /* --------------------------------------------------------- */␊ |
503 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
504 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
505 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
506 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
507 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
508 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
509 | ␊ |
510 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
511 | ␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
512 | /* --------------------------------------------------------- */␊ |
513 | ␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
514 | ␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
515 | ␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
516 | ␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
517 | ␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
518 | ␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
519 | ␉␉␉␉␉if (bitfield(msr, 16, 16))␊ |
520 | ␉␉␉␉␉{␊ |
521 | ␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
522 | ␉␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊ |
523 | ␉␉␉␉␉␉ where the cpu multipler can't be changed to␊ |
524 | ␉␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
525 | ␉␉␉␉␉␉ contents.␉These contents cause mach_kernel to␊ |
526 | ␉␉␉␉␉␉ fail to compute the bus ratio correctly, instead␊ |
527 | ␉␉␉␉␉␉ causing the system to crash since tscGranularity␊ |
528 | ␉␉␉␉␉␉ is inadvertently set to 0.␊ |
529 | ␉␉␉␉␉␉ */␊ |
530 | ␉␉␉␉␉␉if (flex_ratio == 0)␊ |
531 | ␉␉␉␉␉␉{␊ |
532 | ␉␉␉␉␉␉␉/* Clear bit 16 (evidently the presence bit) */␊ |
533 | ␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
534 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
535 | ␉␉␉␉␉␉␉DBG("Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
536 | ␉␉␉␉␉␉}␊ |
537 | ␉␉␉␉␉␉else␊ |
538 | ␉␉␉␉␉␉{␊ |
539 | ␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
540 | ␉␉␉␉␉␉␉{␊ |
541 | ␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
542 | ␉␉␉␉␉␉␉}␊ |
543 | ␉␉␉␉␉␉}␊ |
544 | ␉␉␉␉␉}␊ |
545 | ␊ |
546 | ␉␉␉␉␉if (bus_ratio_max)␊ |
547 | ␉␉␉␉␉{␊ |
548 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
549 | ␉␉␉␉␉}␊ |
550 | ␊ |
551 | ␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
552 | ␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
553 | ␉␉␉␉␉{␊ |
554 | ␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
555 | ␊ |
556 | ␉␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
557 | ␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
558 | ␉␉␉␉␉}␊ |
559 | ␉␉␉␉␉else␊ |
560 | ␉␉␉␉␉{␊ |
561 | ␉␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
562 | ␉␉␉␉␉}␊ |
563 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
564 | ␉␉␉␉␉{␊ |
565 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
566 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
567 | ␉␉␉␉␉␉if (len >= 3)␊ |
568 | ␉␉␉␉␉␉{␊ |
569 | ␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
570 | ␉␉␉␉␉␉}␊ |
571 | ␊ |
572 | ␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
573 | ␊ |
574 | ␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
575 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
576 | ␉␉␉␉␉␉{␊ |
577 | ␉␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
578 | ␉␉␉␉␉␉␉if (len >= 3)␊ |
579 | ␉␉␉␉␉␉␉{␊ |
580 | ␉␉␉␉␉␉␉␉maxdiv = 1;␊ |
581 | ␉␉␉␉␉␉␉}␊ |
582 | ␉␉␉␉␉␉␉else␊ |
583 | ␉␉␉␉␉␉␉{␊ |
584 | ␉␉␉␉␉␉␉␉maxdiv = 0;␊ |
585 | ␉␉␉␉␉␉␉}␊ |
586 | ␉␉␉␉␉␉}␊ |
587 | ␉␉␉␉␉␉else␊ |
588 | ␉␉␉␉␉␉{␊ |
589 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
590 | ␉␉␉␉␉␉}␊ |
591 | ␉␉␉␉␉}␊ |
592 | ␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
593 | ␉␉␉␉␉/*if (bus_ratio_max > 0) bus_ratio = flex_ratio;*/␊ |
594 | ␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
595 | ␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
596 | ␊ |
597 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
598 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
599 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
600 | ␊ |
601 | ␉␉␉␉break;␊ |
602 | ␊ |
603 | ␉␉␉default:␊ |
604 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
605 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
606 | ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
607 | ␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊ |
608 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
609 | ␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊ |
610 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
611 | ␊ |
612 | ␉␉␉␉// This will always be model >= 3␊ |
613 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
614 | ␉␉␉␉{␊ |
615 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
616 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
617 | ␉␉␉␉}␊ |
618 | ␉␉␉␉else␊ |
619 | ␉␉␉␉{␊ |
620 | ␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊ |
621 | ␉␉␉␉␉/* XXX */␊ |
622 | ␉␉␉␉␉maxcoef = currcoef;␊ |
623 | ␉␉␉␉}␊ |
624 | ␊ |
625 | ␉␉␉␉if (!currcoef)␊ |
626 | ␉␉␉␉{␊ |
627 | ␉␉␉␉␉currcoef = maxcoef;␊ |
628 | ␉␉␉␉}␊ |
629 | ␊ |
630 | ␉␉␉␉if (maxcoef)␊ |
631 | ␉␉␉␉{␊ |
632 | ␉␉␉␉␉if (maxdiv)␊ |
633 | ␉␉␉␉␉{␊ |
634 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
635 | ␉␉␉␉␉}␊ |
636 | ␉␉␉␉␉else␊ |
637 | ␉␉␉␉␉{␊ |
638 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
639 | ␉␉␉␉␉}␊ |
640 | ␊ |
641 | ␉␉␉␉␉if (currdiv)␊ |
642 | ␉␉␉␉␉{␊ |
643 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
644 | ␉␉␉␉␉}␊ |
645 | ␉␉␉␉␉else␊ |
646 | ␉␉␉␉␉{␊ |
647 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
648 | ␉␉␉␉␉}␊ |
649 | ␊ |
650 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
651 | ␉␉␉␉}␊ |
652 | ␉␉␉␉break;␊ |
653 | ␉␉␉}␊ |
654 | ␉␉}␊ |
655 | ␉␉/* Mobile CPU */␊ |
656 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
657 | ␉␉{␊ |
658 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
659 | ␉␉}␊ |
660 | ␉}␊ |
661 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
662 | ␉{␊ |
663 | ␉␉switch(p->CPU.ExtFamily)␊ |
664 | ␉␉{␊ |
665 | ␉␉␉case 0x00: /* K8 */␊ |
666 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
667 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
668 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
669 | ␉␉␉␉break;␊ |
670 | ␊ |
671 | ␉␉␉case 0x01: /* K10 */␊ |
672 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
673 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
674 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
675 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
676 | ␉␉␉␉{␊ |
677 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
678 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
679 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
680 | ␉␉␉␉}␊ |
681 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
682 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
683 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
684 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
685 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
686 | ␊ |
687 | ␉␉␉␉break;␊ |
688 | ␊ |
689 | ␉␉␉case 0x05: /* K14 */␊ |
690 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
691 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
692 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
693 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
694 | ␊ |
695 | ␉␉␉␉break;␊ |
696 | ␊ |
697 | ␉␉␉case 0x02: /* K11 */␊ |
698 | ␉␉␉␉// not implimented␊ |
699 | ␉␉␉␉break;␊ |
700 | ␉␉}␊ |
701 | ␊ |
702 | ␉␉if (maxcoef)␊ |
703 | ␉␉{␊ |
704 | ␉␉␉if (currdiv)␊ |
705 | ␉␉␉{␊ |
706 | ␉␉␉␉if (!currcoef)␊ |
707 | ␉␉␉␉{␊ |
708 | ␉␉␉␉␉currcoef = maxcoef;␊ |
709 | ␉␉␉␉}␊ |
710 | ␊ |
711 | ␉␉␉␉if (!cpuFrequency)␊ |
712 | ␉␉␉␉{␊ |
713 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
714 | ␉␉␉␉}␊ |
715 | ␉␉␉␉else␊ |
716 | ␉␉␉␉{␊ |
717 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
718 | ␉␉␉␉}␊ |
719 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
720 | ␉␉␉}␊ |
721 | ␉␉␉else␊ |
722 | ␉␉␉{␊ |
723 | ␉␉␉␉if (!cpuFrequency)␊ |
724 | ␉␉␉␉{␊ |
725 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
726 | ␉␉␉␉}␊ |
727 | ␉␉␉␉else␊ |
728 | ␉␉␉␉{␊ |
729 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
730 | ␉␉␉␉}␊ |
731 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
732 | ␉␉␉}␊ |
733 | ␉␉}␊ |
734 | ␉␉else if (currcoef)␊ |
735 | ␉␉{␊ |
736 | ␉␉␉if (currdiv)␊ |
737 | ␉␉␉{␊ |
738 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
739 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
740 | ␉␉␉}␊ |
741 | ␉␉␉else␊ |
742 | ␉␉␉{␊ |
743 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
744 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
745 | ␉␉␉}␊ |
746 | ␉␉}␊ |
747 | ␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊ |
748 | ␉}␊ |
749 | ␉␊ |
750 | #if 0␊ |
751 | ␉if (!fsbFrequency)␊ |
752 | ␉{␊ |
753 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
754 | ␉␉cpuFrequency = tscFrequency;␊ |
755 | ␉␉DBG("0 ! using the default value for FSB !\n");␊ |
756 | ␉}␊ |
757 | ␊ |
758 | ␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
759 | ␊ |
760 | #endif␊ |
761 | ␊ |
762 | ␉p->CPU.MaxCoef = maxcoef;␊ |
763 | ␉p->CPU.MaxDiv = maxdiv;␊ |
764 | ␉p->CPU.CurrCoef = currcoef;␊ |
765 | ␉p->CPU.CurrDiv = currdiv;␊ |
766 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
767 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
768 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
769 | ␊ |
770 | ␉// keep formatted with spaces instead of tabs␊ |
771 | ␉DBG("\n---------------------------------------------\n");␊ |
772 | ␉DBG("------------------ CPU INFO -----------------\n");␊ |
773 | ␉DBG("---------------------------------------------\n");␊ |
774 | ␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString); // Processor name (BIOS)␊ |
775 | ␉DBG("Vendor: 0x%x\n",␉␉p->CPU.Vendor); // Vendor ex: GenuineIntel␊ |
776 | ␉DBG("Family: 0x%x\n",␉␉p->CPU.Family); // Family ex: 6 (06h)␊ |
777 | ␉DBG("ExtFamily: 0x%x\n",␉␉p->CPU.ExtFamily);␊ |
778 | ␉DBG("Signature: %x\n",␉␉p->CPU.Signature); // CPUID signature␊ |
779 | ␉/*switch (p->CPU.Type) {␊ |
780 | ␉␉case PT_OEM:␊ |
781 | ␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊ |
782 | ␉␉␉break;␊ |
783 | ␉␉case PT_OD:␊ |
784 | ␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊ |
785 | ␉␉␉break;␊ |
786 | ␉␉case PT_DUAL:␊ |
787 | ␉␉␉DBG("Processor type: Intel Dual Processor\n");␊ |
788 | ␉␉␉break;␊ |
789 | ␉␉case PT_RES:␊ |
790 | ␉␉␉DBG("Processor type: Intel Reserved\n");␊ |
791 | ␉␉␉break;␊ |
792 | ␉␉default:␊ |
793 | ␉␉␉break;␊ |
794 | ␉}*/␊ |
795 | ␉DBG("Model: 0x%x\n",␉␉p->CPU.Model); // Model ex: 37 (025h)␊ |
796 | ␉DBG("ExtModel: 0x%x\n",␉␉p->CPU.ExtModel);␊ |
797 | ␉DBG("Stepping: 0x%x\n",␉␉p->CPU.Stepping); // Stepping ex: 5 (05h)␊ |
798 | ␉DBG("MaxCoef: 0x%x\n",␉␉p->CPU.MaxCoef);␊ |
799 | ␉DBG("CurrCoef: 0x%x\n",␉␉p->CPU.CurrCoef);␊ |
800 | ␉DBG("MaxDiv: 0x%x\n",␉␉p->CPU.MaxDiv);␊ |
801 | ␉DBG("CurrDiv: 0x%x\n",␉␉p->CPU.CurrDiv);␊ |
802 | ␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊ |
803 | ␉DBG("FSBFreq: %dMHz\n",␉␉(p->CPU.FSBFrequency + 500000) / 1000000);␊ |
804 | ␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊ |
805 | ␉DBG("Cores: %d\n",␉␉p->CPU.NoCores); // Cores␊ |
806 | ␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads); // Logical procesor␊ |
807 | ␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊ |
808 | ␉DBG("Microcode version: %d\n",␉␉p->CPU.MCodeVersion); // CPU microcode version␊ |
809 | ␉DBG("\n---------------------------------------------\n");␊ |
810 | #if DEBUG_CPU␊ |
811 | ␉pause();␊ |
812 | #endif␊ |
813 | }␊ |
814 | |