1 | /*␊ |
2 | * platform.h␊ |
3 | * AsereBLN: reworked and extended␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
8 | #define __LIBSAIO_PLATFORM_H␊ |
9 | ␊ |
10 | //#include "libsaio.h"␊ |
11 | ␊ |
12 | extern bool platformCPUFeature(uint32_t);␊ |
13 | extern void scan_platform(void);␊ |
14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
15 | ␊ |
16 | /* CPUID Vendor */␊ |
17 | #define CPUID_VENDOR_INTEL 0x756E6547␊ |
18 | #define CPUID_VENDOR_AMD 0x68747541␊ |
19 | ␊ |
20 | /* CPUID index into cpuid_raw */␊ |
21 | #define CPUID_0␉␉␉␉0␊ |
22 | #define CPUID_1␉␉␉␉1␊ |
23 | #define CPUID_2␉␉␉␉2␊ |
24 | #define CPUID_3␉␉␉␉3␊ |
25 | #define CPUID_4␉␉␉␉4␊ |
26 | #define CPUID_5␉␉␉␉5␊ |
27 | #define CPUID_6␉␉␉␉6␊ |
28 | #define CPUID_80␉␉␉7␊ |
29 | #define CPUID_81␉␉␉8␊ |
30 | #define CPUID_88␉␉␉9␊ |
31 | #define CPUID_MAX␉␉␉10␊ |
32 | ␊ |
33 | #define CPUID_MODEL_ANY␉␉␉0x00␊ |
34 | #define CPUID_MODEL_UNKNOWN␉␉0x01␊ |
35 | #define CPUID_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊ |
36 | #define CPUID_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona/Paxville, Irwindale (90nm)␊ |
37 | #define CPUID_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊ |
38 | #define CPUID_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias Pentium M (130nm)␊ |
39 | #define CPUID_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan Pentium M, Celeron M (90nm)␊ |
40 | #define CPUID_MODEL_YONAH␉␉0x0E␉␉␉// Sossaman, Yonah␊ |
41 | #define CPUID_MODEL_MEROM␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊ |
42 | #define CPUID_MODEL_CONROE␉␉0x0F␉␉␉// ␊ |
43 | #define CPUID_MODEL_CELERON␉␉0x16␉␉␉// Merom, Conroe (65nm), Celeron (45nm)␊ |
44 | #define CPUID_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊ |
45 | #define CPUID_MODEL_WOLFDALE␉␉0x17␉␉␉// Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx␊ |
46 | #define CPUID_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊ |
47 | #define CPUID_MODEL_ATOM␉␉0x1C␉␉␉// Pineview, Bonnell␊ |
48 | #define CPUID_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊ |
49 | #define CPUID_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊ |
50 | #define CPUID_MODEL_DALES␉␉0x1F␉␉␉// Havendale, Auburndale␊ |
51 | #define CPUID_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊ |
52 | #define CPUID_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊ |
53 | #define CPUID_MODEL_LINCROFT␉␉0x27␉␉␉// Bonnell␊ |
54 | #define CPUID_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊ |
55 | #define CPUID_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊ |
56 | #define CPUID_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊ |
57 | #define CPUID_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊ |
58 | #define CPUID_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊ |
59 | //#define CPUID_MODEL_BONNELL_ATOM␉0x35␉␉␉// Atom Family Bonnell␊ |
60 | #define CPUID_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview / Saltwell␊ |
61 | #define CPUID_MODEL_SILVERMONT␉␉0x37␉␉␉// Atom E3000, Z3000 Atom Silvermont␊ |
62 | #define CPUID_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊ |
63 | #define CPUID_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊ |
64 | #define CPUID_MODEL_BROADWELL␉␉0x3D␉␉␉// Core M, Broadwell / Core-AVX2␊ |
65 | #define CPUID_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊ |
66 | #define CPUID_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E)␊ |
67 | //#define CPUID_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊ |
68 | #define CPUID_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT, 4th gen Core, Xeon E3-12xx v3␊ |
69 | #define CPUID_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Crystal Well, 4th gen Core, Xeon E3-12xx v3␊ |
70 | //#define CPUID_MODEL_␉␉␉0x4A␉␉␉// Future Atom E3000, Z3000 silvermont / atom␊ |
71 | #define CPUID_MODEL_AVOTON␉␉0x4D␉␉␉// Silvermont/Avoton Atom C2000␊ |
72 | //#define CPUID_MODEL_␉␉␉0x4E␉␉␉// Future Core␊ |
73 | #define CPUID_MODEL_BRODWELL_SVR␉0x4F␉␉␉// Broadwell Server␊ |
74 | #define CPUID_MODEL_BRODWELL_MSVR␉0x56␉␉␉// Broadwell Micro Server, Future Xeon␊ |
75 | //#define CPUID_MODEL_␉␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000␊ |
76 | //#define CPUID_MODEL_␉␉␉0x5D␉␉␉// Silvermont, Future Atom E3000, Z3000␊ |
77 | ␊ |
78 | /* Unknown CPU */␊ |
79 | #define CPU_STRING_UNKNOWN␉"Unknown CPU Type"␊ |
80 | #define bit(n)␉␉␉(1ULL << (n))␊ |
81 | #define bitmask(h,l)␉␉((bit(h)|(bit(h)-1)) & ~(bit(l)-1))␊ |
82 | #define bitfield(x,h,l)␉␉(((x) & bitmask(h,l)) >> l)␊ |
83 | ␊ |
84 | ␊ |
85 | /*␊ |
86 | * The CPUID_FEATURE_XXX values define 64-bit values␊ |
87 | * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
88 | */␊ |
89 | #define CPUID_FEATURE_FPU _Bit(0) /* Floating point unit on-chip */␊ |
90 | #define CPUID_FEATURE_VME _Bit(1) /* Virtual Mode Extension */␊ |
91 | #define CPUID_FEATURE_DE _Bit(2) /* Debugging Extension */␊ |
92 | #define CPUID_FEATURE_PSE _Bit(3) /* Page Size Extension */␊ |
93 | #define CPUID_FEATURE_TSC _Bit(4) /* Time Stamp Counter */␊ |
94 | #define CPUID_FEATURE_MSR _Bit(5) /* Model Specific Registers */␊ |
95 | #define CPUID_FEATURE_PAE _Bit(6) /* Physical Address Extension */␊ |
96 | #define CPUID_FEATURE_MCE _Bit(7) /* Machine Check Exception */␊ |
97 | #define CPUID_FEATURE_CX8 _Bit(8) /* CMPXCHG8B */␊ |
98 | #define CPUID_FEATURE_APIC _Bit(9) /* On-chip APIC */␊ |
99 | #define CPUID_FEATURE_SEP _Bit(11) /* Fast System Call */␊ |
100 | #define CPUID_FEATURE_MTRR _Bit(12) /* Memory Type Range Register */␊ |
101 | #define CPUID_FEATURE_PGE _Bit(13) /* Page Global Enable */␊ |
102 | #define CPUID_FEATURE_MCA _Bit(14) /* Machine Check Architecture */␊ |
103 | #define CPUID_FEATURE_CMOV _Bit(15) /* Conditional Move Instruction */␊ |
104 | #define CPUID_FEATURE_PAT _Bit(16) /* Page Attribute Table */␊ |
105 | #define CPUID_FEATURE_PSE36 _Bit(17) /* 36-bit Page Size Extension */␊ |
106 | #define CPUID_FEATURE_PSN _Bit(18) /* Processor Serial Number */␊ |
107 | #define CPUID_FEATURE_CLFSH _Bit(19) /* CLFLUSH Instruction supported */␊ |
108 | #define CPUID_FEATURE_DS _Bit(21) /* Debug Store */␊ |
109 | #define CPUID_FEATURE_ACPI _Bit(22) /* Thermal monitor and Clock Ctrl */␊ |
110 | #define CPUID_FEATURE_MMX _Bit(23) /* MMX supported */␊ |
111 | #define CPUID_FEATURE_FXSR _Bit(24) /* Fast floating pt save/restore */␊ |
112 | #define CPUID_FEATURE_SSE _Bit(25) /* Streaming SIMD extensions */␊ |
113 | #define CPUID_FEATURE_SSE2 _Bit(26) /* Streaming SIMD extensions 2 */␊ |
114 | #define CPUID_FEATURE_SS _Bit(27) /* Self-Snoop */␊ |
115 | #define CPUID_FEATURE_HTT _Bit(28) /* Hyper-Threading Technology */␊ |
116 | #define CPUID_FEATURE_TM _Bit(29) /* Thermal Monitor (TM1) */␊ |
117 | #define CPUID_FEATURE_PBE _Bit(31) /* Pend Break Enable */␊ |
118 | ␊ |
119 | #define CPUID_FEATURE_SSE3 _HBit(0) /* Streaming SIMD extensions 3 */␊ |
120 | #define CPUID_FEATURE_PCLMULQDQ _HBit(1) /* PCLMULQDQ instruction */␊ |
121 | #define CPUID_FEATURE_DTES64 _HBit(2) /* 64-bit DS layout */␊ |
122 | #define CPUID_FEATURE_MONITOR _HBit(3) /* Monitor/mwait */␊ |
123 | #define CPUID_FEATURE_DSCPL _HBit(4) /* Debug Store CPL */␊ |
124 | #define CPUID_FEATURE_VMX _HBit(5) /* VMX */␊ |
125 | #define CPUID_FEATURE_SMX _HBit(6) /* SMX */␊ |
126 | #define CPUID_FEATURE_EST _HBit(7) /* Enhanced SpeedsTep (GV3) */␊ |
127 | #define CPUID_FEATURE_TM2 _HBit(8) /* Thermal Monitor 2 */␊ |
128 | #define CPUID_FEATURE_SSSE3 _HBit(9) /* Supplemental SSE3 instructions */␊ |
129 | #define CPUID_FEATURE_CID _HBit(10) /* L1 Context ID */␊ |
130 | #define CPUID_FEATURE_SEGLIM64 _HBit(11) /* 64-bit segment limit checking */␊ |
131 | #define CPUID_FEATURE_FMA _HBit(12) /* Fused-Multiply-Add support */␊ |
132 | #define CPUID_FEATURE_CX16 _HBit(13) /* CmpXchg16b instruction */␊ |
133 | #define CPUID_FEATURE_xTPR _HBit(14) /* Send Task PRiority msgs */␊ |
134 | #define CPUID_FEATURE_PDCM _HBit(15) /* Perf/Debug Capability MSR */␊ |
135 | ␊ |
136 | #define CPUID_FEATURE_PCID _HBit(17) /* ASID-PCID support */␊ |
137 | #define CPUID_FEATURE_DCA _HBit(18) /* Direct Cache Access */␊ |
138 | #define CPUID_FEATURE_SSE4_1 _HBit(19) /* Streaming SIMD extensions 4.1 */␊ |
139 | #define CPUID_FEATURE_SSE4_2 _HBit(20) /* Streaming SIMD extensions 4.2 */␊ |
140 | #define CPUID_FEATURE_x2APIC _HBit(21) /* Extended APIC Mode */␊ |
141 | #define CPUID_FEATURE_MOVBE _HBit(22) /* MOVBE instruction */␊ |
142 | #define CPUID_FEATURE_POPCNT _HBit(23) /* POPCNT instruction */␊ |
143 | #define CPUID_FEATURE_TSCTMR _HBit(24) /* TSC deadline timer */␊ |
144 | #define CPUID_FEATURE_AES _HBit(25) /* AES instructions */␊ |
145 | #define CPUID_FEATURE_XSAVE _HBit(26) /* XSAVE instructions */␊ |
146 | #define CPUID_FEATURE_OSXSAVE _HBit(27) /* XGETBV/XSETBV instructions */␊ |
147 | #define CPUID_FEATURE_AVX1_0␉_HBit(28) /* AVX 1.0 instructions */␊ |
148 | #define CPUID_FEATURE_F16C␉_HBit(29) /* Float16 convert instructions */␊ |
149 | #define CPUID_FEATURE_RDRAND␉_HBit(30) /* RDRAND instruction */␊ |
150 | #define CPUID_FEATURE_VMM _HBit(31) /* VMM (Hypervisor) present */␊ |
151 | ␊ |
152 | /*␊ |
153 | * Leaf 7, subleaf 0 additional features.␊ |
154 | * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
155 | */␊ |
156 | #define CPUID_LEAF7_FEATURE_RDWRFSGS _Bit(0)␉/* FS/GS base read/write */␊ |
157 | #define CPUID_LEAF7_FEATURE_TSCOFF _Bit(1)␉/* TSC thread offset */␊ |
158 | #define CPUID_LEAF7_FEATURE_BMI1 _Bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
159 | #define CPUID_LEAF7_FEATURE_HLE _Bit(4)␉/* Hardware Lock Elision*/␊ |
160 | #define CPUID_LEAF7_FEATURE_AVX2 _Bit(5)␉/* AVX2 Instructions */␊ |
161 | #define CPUID_LEAF7_FEATURE_SMEP _Bit(7)␉/* Supervisor Mode Execute Protect */␊ |
162 | #define CPUID_LEAF7_FEATURE_BMI2 _Bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
163 | #define CPUID_LEAF7_FEATURE_ENFSTRG _Bit(9)␉/* ENhanced Fast STRinG copy */␊ |
164 | #define CPUID_LEAF7_FEATURE_INVPCID _Bit(10)␉/* INVPCID intruction, TDB */␊ |
165 | #define CPUID_LEAF7_FEATURE_RTM _Bit(11)␉/* TBD */␊ |
166 | ␊ |
167 | /*␊ |
168 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
169 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
170 | */␊ |
171 | #define CPUID_EXTFEATURE_SYSCALL _Bit(11)␉/* SYSCALL/sysret */␊ |
172 | #define CPUID_EXTFEATURE_XD␉ _Bit(20)␉/* eXecute Disable */␊ |
173 | ␊ |
174 | #define CPUID_EXTFEATURE_1GBPAGE _Bit(26)␉/* 1GB pages */␊ |
175 | #define CPUID_EXTFEATURE_RDTSCP␉ _Bit(27)␉/* RDTSCP */␊ |
176 | #define CPUID_EXTFEATURE_EM64T␉ _Bit(29)␉/* Extended Mem 64 Technology */␊ |
177 | ␊ |
178 | #define CPUID_EXTFEATURE_LAHF␉ _HBit(0)␉/* LAFH/SAHF instructions */␊ |
179 | ␊ |
180 | /*␊ |
181 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
182 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
183 | */␊ |
184 | #define CPUID_EXTFEATURE_TSCI _Bit(8)␉/* TSC Invariant */␊ |
185 | ␊ |
186 | #define␉CPUID_CACHE_SIZE␉16␉/* Number of descriptor values */␊ |
187 | ␊ |
188 | #define CPUID_MWAIT_EXTENSION␉_Bit(0)␉/* enumeration of WMAIT extensions */␊ |
189 | #define CPUID_MWAIT_BREAK␉_Bit(1)␉/* interrupts are break events␉ */␊ |
190 | ␊ |
191 | //-- processor type -> p_type:␊ |
192 | #define PT_OEM␉0x00␉// Intel Original OEM Processor;␊ |
193 | #define PT_OD␉0x01 ␉// Intel Over Drive Processor;␊ |
194 | #define PT_DUAL␉0x02␉// Intel Dual Processor;␊ |
195 | #define PT_RES␉0x03␉// Intel Reserved;␊ |
196 | ␊ |
197 | /* Known MSR registers */␊ |
198 | #define MSR_IA32_PLATFORM_ID 0x0017␊ |
199 | #define MSR_CORE_THREAD_COUNT 0x0035␉/* limited use - not for Penryn or older */␊ |
200 | #define IA32_TSC_ADJUST 0x003B␊ |
201 | #define MSR_IA32_BIOS_SIGN_ID 0x008B␉/* microcode version */␊ |
202 | #define MSR_FSB_FREQ 0x00CD␉/* limited use - not for i7 */␊ |
203 | #define␉MSR_PLATFORM_INFO 0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
204 | /* turbo for penryn */␊ |
205 | #define MSR_PKG_CST_CONFIG_CONTROL 0x00E2␉/* sandy and ivy */␊ |
206 | #define MSR_PMG_IO_CAPTURE_BASE 0x00E4␊ |
207 | #define IA32_MPERF 0x00E7␉/* TSC in C0 only */␊ |
208 | #define IA32_APERF 0x00E8␉/* actual clocks in C0 */␊ |
209 | #define MSR_IA32_EXT_CONFIG 0x00EE␉/* limited use - not for i7 */␊ |
210 | #define MSR_FLEX_RATIO 0x0194␉/* limited use - not for Penryn or older */␊ |
211 | ␉␉␉␉␉␉//see no value on most CPUs␊ |
212 | #define␉MSR_IA32_PERF_STATUS 0x0198␊ |
213 | #define MSR_IA32_PERF_CONTROL 0x0199␊ |
214 | #define MSR_IA32_CLOCK_MODULATION 0x019A␊ |
215 | #define MSR_THERMAL_STATUS 0x019C␊ |
216 | #define MSR_IA32_MISC_ENABLE 0x01A0␊ |
217 | #define MSR_THERMAL_TARGET 0x01A2␉ /* TjMax limited use - not for Penryn or older␉*/␊ |
218 | #define MSR_MISC_PWR_MGMT 0x01AA␊ |
219 | #define MSR_TURBO_RATIO_LIMIT 0x01AD␉ /* limited use - not for Penryn or older */␊ |
220 | ␊ |
221 | #define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊ |
222 | #define MSR_PACKAGE_THERM_STATUS␉0x01B1␊ |
223 | #define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊ |
224 | #define MSR_POWER_CTL␉␉␉0x01FC // MSR 000001FC 0000-0000-0004-005F␊ |
225 | ␊ |
226 | // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊ |
227 | #define MSR_RAPL_POWER_UNIT␉␉␉0x606 /* R/O */␊ |
228 | //MSR 00000606 0000-0000-000A-1003␊ |
229 | #define MSR_PKGC3_IRTL 0x60A /* RW time limit to go C3 */␊ |
230 | // bit 15 = 1 -- the value valid for C-state PM␊ |
231 | #define MSR_PKGC6_IRTL 0x60B /* RW time limit to go C6 */␊ |
232 | //MSR 0000060B 0000-0000-0000-8854␊ |
233 | //Valid + 010=1024ns + 0x54=84mks␊ |
234 | #define MSR_PKGC7_IRTL 0x60C /* RW time limit to go C7 */␊ |
235 | //MSR 0000060C 0000-0000-0000-8854␊ |
236 | #define MSR_PKG_C2_RESIDENCY 0x60D /* same as TSC but in C2 only */␊ |
237 | ␊ |
238 | #define MSR_PKG_RAPL_POWER_LIMIT␉0x610 //MSR 00000610 0000-A580-0000-8960␊ |
239 | #define MSR_PKG_ENERGY_STATUS␉␉0x611 //MSR 00000611 0000-0000-3212-A857␊ |
240 | #define MSR_PKG_POWER_INFO␉␉␉0x614 //MSR 00000614 0000-0000-01E0-02F8␊ |
241 | ␊ |
242 | //AMD␊ |
243 | #define K8_FIDVID_STATUS 0xC0010042␊ |
244 | #define K10_COFVID_LIMIT 0xC0010061␊ |
245 | #define K10_PSTATE_STATUS 0xC0010064␊ |
246 | #define K10_COFVID_STATUS 0xC0010071␊ |
247 | ␊ |
248 | #define MSR_AMD_MPERF 0x000000E7␊ |
249 | #define MSR_AMD_APERF 0x000000E8␊ |
250 | ␊ |
251 | #define DEFAULT_FSB␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
252 | ␊ |
253 | // DFE: This constant comes from older xnu:␊ |
254 | #define CLKNUM␉␉␉1193182␉␉/* formerly 1193167 */␊ |
255 | ␊ |
256 | /* CPU Features */␊ |
257 | #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊ |
258 | #define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊ |
259 | #define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊ |
260 | #define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊ |
261 | #define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊ |
262 | #define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊ |
263 | #define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊ |
264 | #define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊ |
265 | #define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊ |
266 | #define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊ |
267 | ␊ |
268 | /* SMBIOS Memory Types */ ␊ |
269 | #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
270 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
271 | #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
272 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
273 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
274 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
275 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
276 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
277 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
278 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
279 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
280 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
281 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
282 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
283 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
284 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
285 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
286 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
287 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
288 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
289 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
290 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
291 | #define SMB_MEM_TYPE_DDR4␉␉26␊ |
292 | ␊ |
293 | /* Memory Configuration Types */ ␊ |
294 | #define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊ |
295 | #define SMB_MEM_CHANNEL_SINGLE␉␉1␊ |
296 | #define SMB_MEM_CHANNEL_DUAL␉␉2␊ |
297 | #define SMB_MEM_CHANNEL_TRIPLE␉␉3␊ |
298 | ␊ |
299 | /* Maximum number of ram slots */␊ |
300 | #define MAX_RAM_SLOTS␉␉␉8␊ |
301 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
302 | ␊ |
303 | /* Maximum number of SPD bytes */␊ |
304 | #define MAX_SPD_SIZE␉␉␉256␊ |
305 | ␊ |
306 | /* Size of SMBIOS UUID in bytes */␊ |
307 | #define UUID_LEN␉␉␉16␊ |
308 | ␊ |
309 | typedef struct _RamSlotInfo_t␊ |
310 | {␊ |
311 | ␉uint32_t␉␉ModuleSize;␉␉␉␉␉// Size of Module in MB␊ |
312 | ␉uint32_t␉␉Frequency;␉␉␉␉␉// in Mhz␊ |
313 | ␉const char*␉␉Vendor;␊ |
314 | ␉const char*␉␉PartNo;␊ |
315 | ␉const char*␉␉SerialNo;␊ |
316 | ␉char*␉␉␉spd;␉␉␉␉␉␉// SPD Dump␊ |
317 | ␉bool␉␉␉InUse;␊ |
318 | ␉uint8_t␉␉␉Type;␊ |
319 | ␉uint8_t␉␉␉BankConnections;␉␉␉// table type 6, see (3.3.7)␊ |
320 | ␉uint8_t␉␉␉BankConnCnt;␊ |
321 | } RamSlotInfo_t;␊ |
322 | ␊ |
323 | //==============================================================================␊ |
324 | ␊ |
325 | typedef struct _PlatformInfo_t␊ |
326 | {␊ |
327 | ␉struct CPU {␊ |
328 | ␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor - char Vendor[16];␊ |
329 | ␉␉char␉␉␉BrandString[48];␉␉␉// 48 Byte Branding String␊ |
330 | ␉␉//uint16_t␉␉Type;␉␉␉␉␉// Type␊ |
331 | ␉␉uint8_t␉␉␉Family;␉␉␉␉␉// Family␊ |
332 | ␉␉uint8_t␉␉␉Model;␉␉␉␉␉// Model␊ |
333 | ␉␉uint8_t␉␉␉ExtModel;␉␉␉␉// Extended Model␊ |
334 | ␉␉uint8_t␉␉␉ExtFamily;␉␉␉␉// Extended Family␊ |
335 | ␉␉uint8_t␉␉␉Stepping;␉␉␉␉// Stepping␊ |
336 | ␉␉uint64_t␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
337 | ␉␉uint64_t␉␉ExtFeatures;␊ |
338 | ␉␉uint32_t␉␉CoresPerPackage;␊ |
339 | ␉␉uint32_t␉␉LogicalPerPackage;␊ |
340 | ␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊ |
341 | ␉␉//uint8_t␉␉Brand;␊ |
342 | ␉␉//uint8_t␉␉ProcessorFlag;␊ |
343 | ␊ |
344 | ␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊ |
345 | ␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊ |
346 | ␊ |
347 | ␉␉//uint32_t␉␉CacheSize[LCACHE_MAX];␊ |
348 | ␉␉//uint32_t␉␉CacheLineSize;␊ |
349 | ␊ |
350 | ␉␉//uint8_t␉␉cache_info[64];␉␉␉␉// list of cache descriptors␊ |
351 | ␊ |
352 | ␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊ |
353 | ␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Min Multiplier␊ |
354 | ␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊ |
355 | ␉␉uint8_t␉␉␉CurrDiv;␊ |
356 | ␉␉uint64_t␉␉TSCFrequency;␉␉␉␉// TSC Frequency Hz␊ |
357 | ␉␉uint64_t␉␉FSBFrequency;␉␉␉␉// FSB Frequency Hz␊ |
358 | ␉␉uint64_t␉␉CPUFrequency;␉␉␉␉// CPU Frequency Hz␊ |
359 | ␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊ |
360 | ␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊ |
361 | ␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉␉␉// CPUID 0..4, 80..81 Raw Values␊ |
362 | ␊ |
363 | ␉␉uint32_t␉␉MCodeVersion;␉␉␉␉// CPU Microcode version␊ |
364 | ␉} CPU;␊ |
365 | ␊ |
366 | ␉struct RAM {␊ |
367 | ␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊ |
368 | ␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊ |
369 | ␉␉uint8_t␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
370 | ␉␉uint8_t␉␉␉TRC;␉␉␉␉␉␊ |
371 | ␉␉uint8_t␉␉␉TRP;␊ |
372 | ␉␉uint8_t␉␉␉RAS;␊ |
373 | ␉␉uint8_t␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊ |
374 | ␉␉uint8_t␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊ |
375 | ␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
376 | ␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊ |
377 | ␉} RAM;␊ |
378 | ␊ |
379 | ␉struct DMI {␊ |
380 | ␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots populated by SMBIOS␊ |
381 | ␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊ |
382 | ␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊ |
383 | ␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
384 | ␉} DMI;␊ |
385 | ␊ |
386 | ␉uint8_t␉␉␉␉Type;␉␉␉// System Type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊ |
387 | ␉uint8_t␉␉␉␉*UUID;␊ |
388 | } PlatformInfo_t;␊ |
389 | ␊ |
390 | extern PlatformInfo_t Platform;␊ |
391 | ␊ |
392 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
393 | |