1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | #define XEON "Xeon"␊ |
22 | #define CORE_I3 "Core(TM) i3"␊ |
23 | #define CORE_I5 "Core(TM) i5"␊ |
24 | #define CORE_I7 "Core(TM) i7"␊ |
25 | ␊ |
26 | ␊ |
27 | bool getProcessorInformationExternalClock(returnType *value)␊ |
28 | {␊ |
29 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
30 | ␉{␊ |
31 | ␉␉switch (Platform.CPU.Family)␊ |
32 | ␉␉{␊ |
33 | ␉␉␉case 0x06:␊ |
34 | ␉␉␉{␊ |
35 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
36 | ␉␉␉␉{␊ |
37 | ␉␉␉␉␉// set external clock to 0 for SANDY␊ |
38 | ␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
39 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
40 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
41 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
42 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
43 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
44 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
45 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
46 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
47 | ␊ |
48 | ␉␉␉␉␉␉value->word = 0;␊ |
49 | ␉␉␉␉␉␉break;␊ |
50 | ␉␉␉␉␉default:␊ |
51 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
52 | ␉␉␉␉}␊ |
53 | ␉␉␉}␊ |
54 | ␉␉␉␉break;␊ |
55 | ␊ |
56 | ␉␉␉default:␊ |
57 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
58 | ␉␉}␊ |
59 | ␉}␊ |
60 | ␉else␊ |
61 | ␉{␊ |
62 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
63 | ␉}␊ |
64 | ␊ |
65 | ␉return true;␊ |
66 | }␊ |
67 | ␊ |
68 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
69 | {␊ |
70 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
71 | ␉return true;␊ |
72 | }␊ |
73 | ␊ |
74 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
75 | {␊ |
76 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
77 | ␉{␊ |
78 | ␉␉switch (Platform.CPU.Family)␊ |
79 | ␉␉{␊ |
80 | ␉␉␉case 0x06:␊ |
81 | ␉␉␉{␊ |
82 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
83 | ␉␉␉␉{␊ |
84 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
85 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊ |
86 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
87 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
88 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
89 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
90 | ␉␉␉␉␉␉return false;␊ |
91 | ␊ |
92 | ␉␉␉␉␉case 0x19:␊ |
93 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
94 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
95 | ␉␉␉␉␉case CPUID_MODEL_DALES:␊ |
96 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
97 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
98 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
99 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
100 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
101 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
102 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
103 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
104 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
105 | ␉␉␉␉␉{␊ |
106 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
107 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
108 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
109 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
110 | ␉␉␉␉␉␉unsigned int i;␊ |
111 | ␉␉␉␉␉␉␊ |
112 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
113 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
114 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊ |
115 | ␉␉␉␉␉␉{␊ |
116 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
117 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
118 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
119 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
120 | ␉␉␉␉␉␉␉␊ |
121 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
122 | ␉␉␉␉␉␉␉{␊ |
123 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊ |
124 | ␉␉␉␉␉␉␉}␊ |
125 | ␉␉␉␉␉␉}␊ |
126 | ␊ |
127 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
128 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
129 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
130 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
131 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
132 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
133 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
134 | ␉␉␉␉␉␉{␊ |
135 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
136 | ␉␉␉␉␉␉}␊ |
137 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
138 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
139 | ␉␉␉␉␉␉return true;␊ |
140 | ␉␉␉␉␉}␊ |
141 | ␉␉␉␉␉default:␊ |
142 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
143 | ␉␉␉␉}␊ |
144 | ␉␉␉}␊ |
145 | ␉␉␉default:␊ |
146 | ␉␉␉␉break;␊ |
147 | ␉␉}␊ |
148 | ␉}␊ |
149 | ␉return false;␊ |
150 | }␊ |
151 | ␊ |
152 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
153 | {␊ |
154 | ␉if (Platform.CPU.NoCores >= 4)␊ |
155 | ␉{␊ |
156 | ␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊ |
157 | ␉}␊ |
158 | ␉else if (Platform.CPU.NoCores == 1)␊ |
159 | ␉{␊ |
160 | ␉␉return 0x201;␉// 513 - Core Duo␊ |
161 | ␉};␊ |
162 | ␉␊ |
163 | ␉return 0x301;␉␉// 769 - Core 2 Duo␊ |
164 | }␊ |
165 | ␊ |
166 | bool getSMBOemProcessorType(returnType *value)␊ |
167 | {␊ |
168 | ␉static bool done = false;␊ |
169 | ␊ |
170 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
171 | ␊ |
172 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
173 | ␉{␊ |
174 | ␉␉if (!done)␊ |
175 | ␉␉{␊ |
176 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
177 | ␉␉␉done = true;␊ |
178 | ␉␉}␊ |
179 | ␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊ |
180 | ␉␉switch (Platform.CPU.Family)␊ |
181 | ␉␉{␊ |
182 | ␉␉␉case 0x0F:␊ |
183 | ␉␉␉case 0x06:␊ |
184 | ␉␉␉{␊ |
185 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
186 | ␉␉␉␉{␊ |
187 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
188 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊ |
189 | ␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊ |
190 | ␉␉␉␉␉case CPUID_MODEL_NOCONA:␊ |
191 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
192 | ␉␉␉␉␉␉{␊ |
193 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
194 | ␉␉␉␉␉␉}␊ |
195 | ␉␉␉␉␉␉return true;␊ |
196 | ␊ |
197 | ␉␉␉␉␉case CPUID_MODEL_PRESLER:␊ |
198 | ␉␉␉␉␉case CPUID_MODEL_CELERON:␊ |
199 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
200 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
201 | ␉␉␉␉␉␉return true;␊ |
202 | ␊ |
203 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
204 | ␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
205 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
206 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
207 | ␉␉␉␉␉␉{␊ |
208 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
209 | ␉␉␉␉␉␉␉return true;␊ |
210 | ␉␉␉␉␉␉}␊ |
211 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
212 | ␉␉␉␉␉␉{␊ |
213 | ␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊ |
214 | ␉␉␉␉␉␉}␊ |
215 | ␉␉␉␉␉␉else␊ |
216 | ␉␉␉␉␉␉{␊ |
217 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊ |
218 | ␉␉␉␉␉␉}␊ |
219 | ␉␉␉␉␉␉return true;␊ |
220 | ␊ |
221 | ␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
222 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
223 | ␉␉␉␉␉␉return true;␊ |
224 | ␊ |
225 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊ |
226 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
227 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
228 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
229 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
230 | ␉␉␉␉␉␉{␊ |
231 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
232 | ␉␉␉␉␉␉␉return true;␊ |
233 | ␉␉␉␉␉␉}␊ |
234 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
235 | ␉␉␉␉␉␉{␊ |
236 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
237 | ␉␉␉␉␉␉␉return true;␊ |
238 | ␉␉␉␉␉␉}␊ |
239 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
240 | ␉␉␉␉␉␉{␊ |
241 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
242 | ␉␉␉␉␉␉␉return true;␊ |
243 | ␉␉␉␉␉␉}␊ |
244 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
245 | ␉␉␉␉␉␉{␊ |
246 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
247 | ␉␉␉␉␉␉␉return true;␊ |
248 | ␉␉␉␉␉␉}␊ |
249 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
250 | ␉␉␉␉␉␉{␊ |
251 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊ |
252 | ␉␉␉␉␉␉}␊ |
253 | ␉␉␉␉␉␉return true;␊ |
254 | ␊ |
255 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
256 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
257 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
258 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
259 | ␉␉␉␉␉␉{␊ |
260 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
261 | ␉␉␉␉␉␉␉return true;␊ |
262 | ␉␉␉␉␉␉}␊ |
263 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
264 | ␉␉␉␉␉␉{␊ |
265 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
266 | ␉␉␉␉␉␉␉return true;␊ |
267 | ␉␉␉␉␉␉}␊ |
268 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
269 | ␉␉␉␉␉␉{␊ |
270 | ␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊ |
271 | ␉␉␉␉␉␉␉return true;␊ |
272 | ␉␉␉␉␉␉}␊ |
273 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
274 | ␉␉␉␉␉␉{␊ |
275 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
276 | ␉␉␉␉␉␉␉return true;␊ |
277 | ␉␉␉␉␉␉}␊ |
278 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
279 | ␉␉␉␉␉␉{␊ |
280 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊ |
281 | ␉␉␉␉␉␉}␊ |
282 | ␉␉␉␉␉␉return true;␊ |
283 | ␊ |
284 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
285 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
286 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
287 | ␉␉␉␉␉␉{␊ |
288 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
289 | ␉␉␉␉␉␉␉return true;␊ |
290 | ␉␉␉␉␉␉}␊ |
291 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
292 | ␉␉␉␉␉␉{␊ |
293 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
294 | ␉␉␉␉␉␉␉return true;␊ |
295 | ␉␉␉␉␉␉}␊ |
296 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
297 | ␉␉␉␉␉␉{␊ |
298 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
299 | ␉␉␉␉␉␉␉return true;␊ |
300 | ␉␉␉␉␉␉}␊ |
301 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
302 | ␉␉␉␉␉␉{␊ |
303 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
304 | ␉␉␉␉␉␉␉return true;␊ |
305 | ␉␉␉␉␉␉}␊ |
306 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
307 | ␉␉␉␉␉␉{␊ |
308 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊ |
309 | ␉␉␉␉␉␉}␊ |
310 | ␉␉␉␉␉␉return true;␊ |
311 | ␊ |
312 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
313 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
314 | ␉␉␉␉␉␉{␊ |
315 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
316 | ␉␉␉␉␉␉␉return true;␊ |
317 | ␉␉␉␉␉␉}␊ |
318 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
319 | ␉␉␉␉␉␉{␊ |
320 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊ |
321 | ␉␉␉␉␉␉␉return true;␊ |
322 | ␉␉␉␉␉␉}␊ |
323 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
324 | ␉␉␉␉␉␉{␊ |
325 | ␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊ |
326 | ␉␉␉␉␉␉␉return true;␊ |
327 | ␉␉␉␉␉␉}␊ |
328 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
329 | ␉␉␉␉␉␉{␊ |
330 | ␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊ |
331 | ␉␉␉␉␉␉␉return true;␊ |
332 | ␉␉␉␉␉␉}␊ |
333 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
334 | ␉␉␉␉␉␉{␊ |
335 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊ |
336 | ␉␉␉␉␉␉}␊ |
337 | ␉␉␉␉␉␉return true;␊ |
338 | ␊ |
339 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊ |
340 | ␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊ |
341 | ␉␉␉␉␉␉return true;␊ |
342 | ␊ |
343 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊ |
344 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊ |
345 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
346 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊ |
347 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
348 | ␉␉␉␉␉␉{␊ |
349 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
350 | ␉␉␉␉␉␉␉return true;␊ |
351 | ␉␉␉␉␉␉}␊ |
352 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
353 | ␉␉␉␉␉␉{␊ |
354 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
355 | ␉␉␉␉␉␉␉return true;␊ |
356 | ␉␉␉␉␉␉}␊ |
357 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
358 | ␉␉␉␉␉␉{␊ |
359 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
360 | ␉␉␉␉␉␉␉return true;␊ |
361 | ␉␉␉␉␉␉}␊ |
362 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
363 | ␉␉␉␉␉␉{␊ |
364 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
365 | ␉␉␉␉␉␉␉return true;␊ |
366 | ␉␉␉␉␉␉}␊ |
367 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
368 | ␉␉␉␉␉␉{␊ |
369 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊ |
370 | ␉␉␉␉␉␉}␊ |
371 | ␉␉␉␉␉␉return true;␊ |
372 | ␊ |
373 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
374 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
375 | ␉␉␉␉␉␉return true;␊ |
376 | ␊ |
377 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
378 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
379 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
380 | ␉␉␉␉␉␉return true;␊ |
381 | ␉␉␉␉␉default:␊ |
382 | ␉␉␉␉␉␉break; // Unsupported CPU type␊ |
383 | ␉␉␉␉}␊ |
384 | ␉␉␉}␊ |
385 | ␉␉␉default:␊ |
386 | ␉␉␉␉break;␊ |
387 | ␉␉}␊ |
388 | ␉}␊ |
389 | ␉␊ |
390 | ␉return false;␊ |
391 | }␊ |
392 | ␊ |
393 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
394 | {␊ |
395 | ␉static int idx = -1;␊ |
396 | ␉int␉map;␊ |
397 | ␊ |
398 | ␉if (!bootInfo->memDetect)␊ |
399 | ␉{␊ |
400 | ␉␉return false;␊ |
401 | ␉}␊ |
402 | ␊ |
403 | ␉idx++;␊ |
404 | ␉if (idx < MAX_RAM_SLOTS)␊ |
405 | ␉{␊ |
406 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
407 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
408 | ␉␉{␊ |
409 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
410 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
411 | ␉␉␉return true;␊ |
412 | ␉␉}␊ |
413 | ␉}␊ |
414 | ␊ |
415 | ␉value->byte = 2; // means Unknown␊ |
416 | ␉return true;␊ |
417 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
418 | //␉return true;␊ |
419 | }␊ |
420 | ␊ |
421 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
422 | {␊ |
423 | ␉value->word = 0xFFFF;␊ |
424 | ␉return true;␊ |
425 | }␊ |
426 | ␊ |
427 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
428 | {␊ |
429 | ␉static int idx = -1;␊ |
430 | ␉int␉map;␊ |
431 | ␊ |
432 | ␉if (!bootInfo->memDetect)␊ |
433 | ␉{␊ |
434 | ␉␉return false;␊ |
435 | ␉}␊ |
436 | ␊ |
437 | ␉idx++;␊ |
438 | ␉if (idx < MAX_RAM_SLOTS)␊ |
439 | ␉{␊ |
440 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
441 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
442 | ␉␉{␊ |
443 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
444 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
445 | ␉␉␉return true;␊ |
446 | ␉␉}␊ |
447 | ␉}␊ |
448 | ␊ |
449 | ␉value->dword = 0; // means Unknown␊ |
450 | ␉return true;␊ |
451 | //␉value->dword = 800;␊ |
452 | //␉return true;␊ |
453 | }␊ |
454 | ␊ |
455 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
456 | {␊ |
457 | ␉static int idx = -1;␊ |
458 | ␉int␉map;␊ |
459 | ␊ |
460 | ␉if (!bootInfo->memDetect)␊ |
461 | ␉{␊ |
462 | ␉␉return false;␊ |
463 | ␉}␊ |
464 | ␊ |
465 | ␉idx++;␊ |
466 | ␉if (idx < MAX_RAM_SLOTS)␊ |
467 | ␉{␊ |
468 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
469 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
470 | ␉␉{␊ |
471 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
472 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
473 | ␉␉␉return true;␊ |
474 | ␉␉}␊ |
475 | ␉}␊ |
476 | ␊ |
477 | ␉value->string = NOT_AVAILABLE;␊ |
478 | ␉return true;␊ |
479 | }␊ |
480 | ␊ |
481 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
482 | {␊ |
483 | ␉static int idx = -1;␊ |
484 | ␉int␉map;␊ |
485 | ␊ |
486 | ␉if (!bootInfo->memDetect)␊ |
487 | ␉{␊ |
488 | ␉␉return false;␊ |
489 | ␉}␊ |
490 | ␊ |
491 | ␉idx++;␊ |
492 | ␊ |
493 | ␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
494 | ␊ |
495 | ␉if (idx < MAX_RAM_SLOTS)␊ |
496 | ␉{␊ |
497 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
498 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
499 | ␉␉{␊ |
500 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
501 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
502 | ␉␉␉return true;␊ |
503 | ␉␉}␊ |
504 | ␉}␊ |
505 | ␊ |
506 | ␉value->string = NOT_AVAILABLE;␊ |
507 | ␉return true;␊ |
508 | }␊ |
509 | ␊ |
510 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
511 | {␊ |
512 | ␉static int idx = -1;␊ |
513 | ␉int␉map;␊ |
514 | ␊ |
515 | ␉if (!bootInfo->memDetect)␊ |
516 | ␉{␊ |
517 | ␉␉return false;␊ |
518 | ␉}␊ |
519 | ␊ |
520 | ␉idx++;␊ |
521 | ␉if (idx < MAX_RAM_SLOTS)␊ |
522 | ␉{␊ |
523 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
524 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
525 | ␉␉{␊ |
526 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
527 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
528 | ␉␉␉return true;␊ |
529 | ␉␉}␊ |
530 | ␉}␊ |
531 | ␊ |
532 | ␉value->string = NOT_AVAILABLE;␊ |
533 | ␉return true;␊ |
534 | }␊ |
535 | ␊ |
536 | ␊ |
537 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
538 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
539 | static const char * const SMTAG = "_SM_";␊ |
540 | static const char* const DMITAG = "_DMI_";␊ |
541 | ␊ |
542 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
543 | {␊ |
544 | ␉SMBEntryPoint␉*smbios;␊ |
545 | ␉/*␊ |
546 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
547 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
548 | ␉ */␊ |
549 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
550 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊ |
551 | ␉{␊ |
552 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
553 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
554 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
555 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
556 | ␉␉{␊ |
557 | ␉␉␉return smbios;␊ |
558 | ␉ }␊ |
559 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
560 | ␉}␊ |
561 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
562 | ␉pause();␊ |
563 | ␉return NULL;␊ |
564 | }␊ |
565 | ␊ |
566 | |