Root/
Source at commit 2605 created 9 years 4 months ago. By ifabio, Temp disabled feature introduced in commit 2562 (Added ability to auto-select last booted partition as the boot volume), cause AllocateKernelMemory error. | |
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1 | /*␊ |
2 | * dram controller access and scan from the pci host controller␊ |
3 | * Integrated and adapted for chameleon 2.0 RC5 by Rekursor from bs0d work␊ |
4 | * original source comes from:␊ |
5 | *␊ |
6 | * memtest86␊ |
7 | *␊ |
8 | * Released under version 2 of the Gnu Public License.␊ |
9 | * By Chris Brady, cbrady@sgi.com␊ |
10 | * ----------------------------------------------------␊ |
11 | * MemTest86+ V4.00 Specific code (GPL V2.0)␊ |
12 | * By Samuel DEMEULEMEESTER, sdemeule@memtest.org␊ |
13 | * http://www.canardpc.com - http://www.memtest.org␊ |
14 | */␊ |
15 | ␊ |
16 | #include "libsaio.h"␊ |
17 | #include "bootstruct.h"␊ |
18 | #include "pci.h"␊ |
19 | #include "platform.h"␊ |
20 | #include "dram_controllers.h"␊ |
21 | ␊ |
22 | #ifndef DEBUG_DRAM␊ |
23 | #define DEBUG_DRAM 0␊ |
24 | #endif␊ |
25 | ␊ |
26 | #if DEBUG_DRAM␊ |
27 | #define DBG(x...) printf(x)␊ |
28 | #else␊ |
29 | #define DBG(x...)␊ |
30 | #endif␊ |
31 | ␊ |
32 | /*␊ |
33 | * Initialise memory controller functions␊ |
34 | */␊ |
35 | ␊ |
36 | // Setup P35 Memory Controller␊ |
37 | static void setup_p35(pci_dt_t *dram_dev)␊ |
38 | {␊ |
39 | ␉uint32_t dev0;␊ |
40 | ␊ |
41 | ␉// Activate MMR I/O␊ |
42 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
43 | ␉if (!(dev0 & 0x1)) {␊ |
44 | ␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊ |
45 | ␉}␊ |
46 | }␊ |
47 | ␊ |
48 | int nhm_bus = 0x3F;␊ |
49 | ␊ |
50 | // Setup Nehalem Integrated Memory Controller␊ |
51 | static void setup_nhm(pci_dt_t *dram_dev)␊ |
52 | {␊ |
53 | ␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
54 | ␉unsigned long did, vid;␊ |
55 | ␉int i;␊ |
56 | ␊ |
57 | ␉// Nehalem supports Scrubbing␊ |
58 | ␉// First, locate the PCI bus where the MCH is located␊ |
59 | ␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊ |
60 | ␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_VENDOR_ID);␊ |
61 | ␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), PCI_DEVICE_ID);␊ |
62 | ␉␉vid &= 0xFFFF;␊ |
63 | ␉␉did &= 0xFF00;␊ |
64 | ␊ |
65 | ␉␉if(vid == 0x8086 && did >= 0x2C00) {␊ |
66 | ␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
67 | ␉␉}␊ |
68 | ␉}␊ |
69 | }␊ |
70 | ␊ |
71 | /*␊ |
72 | * Retrieve memory controller fsb functions␊ |
73 | */␊ |
74 | ␊ |
75 | ␊ |
76 | // Get i965 Memory Speed␊ |
77 | static void get_fsb_i965(pci_dt_t *dram_dev)␊ |
78 | {␊ |
79 | ␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊ |
80 | ␊ |
81 | ␉long *ptr;␊ |
82 | ␊ |
83 | ␉// Find Ratio␊ |
84 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
85 | ␉dev0 &= 0xFFFFC000;␊ |
86 | ␉ptr = (long*)(dev0 + 0xC00);␊ |
87 | ␉mch_cfg = *ptr & 0xFFFF;␊ |
88 | ␊ |
89 | ␉mch_ratio = 100000;␊ |
90 | ␊ |
91 | ␉switch (mch_cfg & 7) {␊ |
92 | ␉␉case 0: mch_fsb = 1066; break;␊ |
93 | ␉␉case 1: mch_fsb = 533; break;␊ |
94 | ␉␉default:␊ |
95 | ␉␉case 2: mch_fsb = 800; break;␊ |
96 | ␉␉case 3: mch_fsb = 667; break;␊ |
97 | ␉␉case 4: mch_fsb = 1333; break;␊ |
98 | ␉␉case 6: mch_fsb = 1600; break;␊ |
99 | ␉}␊ |
100 | ␊ |
101 | ␉DBG("mch_fsb %d\n", mch_fsb);␊ |
102 | ␊ |
103 | ␉switch (mch_fsb) {␊ |
104 | ␉␉case 533:␊ |
105 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
106 | ␉␉␉case 1:␉mch_ratio = 200000; break;␊ |
107 | ␉␉␉case 2:␉mch_ratio = 250000; break;␊ |
108 | ␉␉␉case 3:␉mch_ratio = 300000; break;␊ |
109 | ␉␉}␊ |
110 | ␉␉break;␊ |
111 | ␊ |
112 | ␉␉default:␊ |
113 | ␉␉case 800:␊ |
114 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
115 | ␉␉␉case 0:␉mch_ratio = 100000; break;␊ |
116 | ␉␉␉case 1:␉mch_ratio = 125000; break;␊ |
117 | ␉␉␉case 2:␉mch_ratio = 166667; break; // 1.666666667␊ |
118 | ␉␉␉case 3:␉mch_ratio = 200000; break;␊ |
119 | ␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊ |
120 | ␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊ |
121 | ␉␉}␊ |
122 | ␉␉break;␊ |
123 | ␊ |
124 | ␉␉case 1066:␊ |
125 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
126 | ␉␉␉case 1:␉mch_ratio = 100000; break;␊ |
127 | ␉␉␉case 2:␉mch_ratio = 125000; break;␊ |
128 | ␉␉␉case 3:␉mch_ratio = 150000; break;␊ |
129 | ␉␉␉case 4:␉mch_ratio = 200000; break;␊ |
130 | ␉␉␉case 5:␉mch_ratio = 250000; break;␊ |
131 | ␉␉}␊ |
132 | ␉␉break;␊ |
133 | ␊ |
134 | ␉␉case 1333:␊ |
135 | ␉␉switch ((mch_cfg >> 4) & 7) {␊ |
136 | ␉␉␉case 2:␉mch_ratio = 100000; break;␊ |
137 | ␉␉␉case 3:␉mch_ratio = 120000; break;␊ |
138 | ␉␉␉case 4:␉mch_ratio = 160000; break;␊ |
139 | ␉␉␉case 5:␉mch_ratio = 200000; break;␊ |
140 | ␉␉}␊ |
141 | ␉␉break;␊ |
142 | ␊ |
143 | ␉␉case 1600:␊ |
144 | ␉␉switch ((mch_cfg >> 4) & 7)␊ |
145 | ␉␉{␊ |
146 | ␉␉␉case 3:␉mch_ratio = 100000; break;␊ |
147 | ␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊ |
148 | ␉␉␉case 5:␉mch_ratio = 150000; break;␊ |
149 | ␉␉␉case 6:␉mch_ratio = 200000; break;␊ |
150 | ␉␉}␊ |
151 | ␉␉break;␊ |
152 | ␉}␊ |
153 | ␊ |
154 | ␉DBG("mch_ratio %d\n", mch_ratio);␊ |
155 | ␊ |
156 | ␉// Compute RAM Frequency␊ |
157 | ␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊ |
158 | ␊ |
159 | ␉DBG("ram_fsb %d\n", Platform.RAM.Frequency);␊ |
160 | ␊ |
161 | }␊ |
162 | ␊ |
163 | // Get i965m Memory Speed␊ |
164 | static void get_fsb_im965(pci_dt_t *dram_dev)␊ |
165 | {␊ |
166 | ␉uint32_t dev0, mch_ratio, mch_cfg, mch_fsb;␊ |
167 | ␊ |
168 | ␉long *ptr;␊ |
169 | ␊ |
170 | ␉// Find Ratio␊ |
171 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
172 | ␉dev0 &= 0xFFFFC000;␊ |
173 | ␉ptr = (long*)(dev0 + 0xC00);␊ |
174 | ␉mch_cfg = *ptr & 0xFFFF;␊ |
175 | ␊ |
176 | ␉mch_ratio = 100000;␊ |
177 | ␊ |
178 | ␉switch (mch_cfg & 7) {␊ |
179 | ␉␉case 1: mch_fsb = 533; break;␊ |
180 | ␉␉default: ␊ |
181 | ␉␉case 2:␉mch_fsb = 800; break;␊ |
182 | ␉␉case 3:␉mch_fsb = 667; break;␊ |
183 | ␉␉case 6:␉mch_fsb = 1066; break;␊ |
184 | ␉}␊ |
185 | ␊ |
186 | ␉switch (mch_fsb) {␊ |
187 | ␉␉case 533:␊ |
188 | ␉␉␉switch ((mch_cfg >> 4) & 7) {␊ |
189 | ␉␉␉␉case 1:␉mch_ratio = 125000; break;␊ |
190 | ␉␉␉␉case 2:␉mch_ratio = 150000; break;␊ |
191 | ␉␉␉␉case 3:␉mch_ratio = 200000; break;␊ |
192 | ␉␉␉}␊ |
193 | ␉␉␉break;␊ |
194 | ␊ |
195 | ␉␉case 667:␊ |
196 | ␉␉␉switch ((mch_cfg >> 4)& 7) {␊ |
197 | ␉␉␉␉case 1:␉mch_ratio = 100000; break;␊ |
198 | ␉␉␉␉case 2:␉mch_ratio = 120000; break;␊ |
199 | ␉␉␉␉case 3:␉mch_ratio = 160000; break;␊ |
200 | ␉␉␉␉case 4:␉mch_ratio = 200000; break;␊ |
201 | ␉␉␉␉case 5:␉mch_ratio = 240000; break;␊ |
202 | ␉␉␉}␊ |
203 | ␉␉␉break;␊ |
204 | ␊ |
205 | ␉␉default:␊ |
206 | ␉␉case 800:␊ |
207 | ␉␉␉switch ((mch_cfg >> 4) & 7) {␊ |
208 | ␉␉␉␉case 1:␉mch_ratio = 83333; break; // 0.833333333␊ |
209 | ␉␉␉␉case 2:␉mch_ratio = 100000; break;␊ |
210 | ␉␉␉␉case 3:␉mch_ratio = 133333; break; // 1.333333333␊ |
211 | ␉␉␉␉case 4:␉mch_ratio = 166667; break; // 1.666666667␊ |
212 | ␉␉␉␉case 5:␉mch_ratio = 200000; break;␊ |
213 | ␉␉␉}␊ |
214 | ␉␉␉break;␊ |
215 | ␉␉case 1066:␊ |
216 | ␉␉␉switch ((mch_cfg >> 4)&7) {␊ |
217 | ␉␉␉␉case 5:␉mch_ratio = 150000; break;␊ |
218 | ␉␉␉␉case 6:␉mch_ratio = 200000; break;␊ |
219 | ␉␉␉}␊ |
220 | ␊ |
221 | ␉}␊ |
222 | ␊ |
223 | ␉// Compute RAM Frequency␊ |
224 | ␉Platform.RAM.Frequency = (Platform.CPU.FSBFrequency * mch_ratio) / 100000;␊ |
225 | }␊ |
226 | ␊ |
227 | ␊ |
228 | // Get iCore7 Memory Speed␊ |
229 | static void get_fsb_nhm(pci_dt_t *dram_dev)␊ |
230 | {␊ |
231 | ␉uint32_t mch_ratio, mc_dimm_clk_ratio;␊ |
232 | ␊ |
233 | ␉// Get the clock ratio␊ |
234 | ␉mc_dimm_clk_ratio = pci_config_read16(PCIADDR(nhm_bus, 3, 4), 0x54 );␊ |
235 | ␉mch_ratio = (mc_dimm_clk_ratio & 0x1F);␊ |
236 | ␊ |
237 | ␉// Compute RAM Frequency␊ |
238 | ␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊ |
239 | }␊ |
240 | ␊ |
241 | /*␊ |
242 | * Retrieve memory controller info functions␊ |
243 | */␊ |
244 | ␊ |
245 | // Get i965 Memory Timings␊ |
246 | static void get_timings_i965(pci_dt_t *dram_dev)␊ |
247 | {␊ |
248 | ␉// Thanks for CDH optis␊ |
249 | ␉uint32_t dev0, c0ckectrl, c1ckectrl, offset;␊ |
250 | ␉uint32_t ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊ |
251 | ␊ |
252 | ␉long *ptr;␊ |
253 | ␊ |
254 | ␉// Read MMR Base Address␊ |
255 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
256 | ␉dev0 &= 0xFFFFC000;␊ |
257 | ␊ |
258 | ␉ptr = (long*)(dev0 + 0x260);␊ |
259 | ␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊ |
260 | ␊ |
261 | ␉ptr = (long*)(dev0 + 0x660);␊ |
262 | ␉c1ckectrl = *ptr & 0xFFFFFFFF;␊ |
263 | ␊ |
264 | ␉// If DIMM 0 not populated, check DIMM 1␊ |
265 | ␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊ |
266 | ␊ |
267 | ␉ptr = (long*)(dev0 + offset + 0x29C);␊ |
268 | ␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊ |
269 | ␊ |
270 | ␉ptr = (long*)(dev0 + offset + 0x250);␉␊ |
271 | ␉Precharge_Register = *ptr & 0xFFFFFFFF;␊ |
272 | ␊ |
273 | ␉ptr = (long*)(dev0 + offset + 0x252);␊ |
274 | ␉ACT_Register = *ptr & 0xFFFFFFFF;␊ |
275 | ␊ |
276 | ␉ptr = (long*)(dev0 + offset + 0x258);␊ |
277 | ␉Read_Register = *ptr & 0xFFFFFFFF;␊ |
278 | ␊ |
279 | ␉ptr = (long*)(dev0 + offset + 0x244);␊ |
280 | ␉Misc_Register = *ptr & 0xFFFFFFFF;␊ |
281 | ␊ |
282 | ␉// 965 Series only support DDR2␊ |
283 | ␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊ |
284 | ␊ |
285 | ␉// CAS Latency (tCAS)␊ |
286 | ␉Platform.RAM.CAS = ((ODT_Control_Register >> 17) & 7) + 3;␊ |
287 | ␊ |
288 | ␉// RAS-To-CAS (tRCD)␊ |
289 | ␉Platform.RAM.TRC = (Read_Register >> 16) & 0xF;␊ |
290 | ␊ |
291 | ␉// RAS Precharge (tRP)␊ |
292 | ␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊ |
293 | ␊ |
294 | ␉// RAS Active to precharge (tRAS)␊ |
295 | ␉Platform.RAM.RAS = (Precharge_Register >> 11) & 0x1F;␊ |
296 | ␊ |
297 | ␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊ |
298 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
299 | ␉} else {␊ |
300 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
301 | ␉}␊ |
302 | }␊ |
303 | ␊ |
304 | // Get im965 Memory Timings␊ |
305 | static void get_timings_im965(pci_dt_t *dram_dev)␊ |
306 | {␊ |
307 | ␉// Thanks for CDH optis␊ |
308 | ␉uint32_t dev0, c0ckectrl, c1ckectrl, offset, ODT_Control_Register, Precharge_Register;␊ |
309 | ␉long *ptr;␊ |
310 | ␊ |
311 | ␉// Read MMR Base Address␊ |
312 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
313 | ␉dev0 &= 0xFFFFC000;␊ |
314 | ␊ |
315 | ␉ptr = (long*)(dev0 + 0x1200);␊ |
316 | ␉c0ckectrl = *ptr & 0xFFFFFFFF;␉␊ |
317 | ␊ |
318 | ␉ptr = (long*)(dev0 + 0x1300);␊ |
319 | ␉c1ckectrl = *ptr & 0xFFFFFFFF;␊ |
320 | ␊ |
321 | ␉// If DIMM 0 not populated, check DIMM 1␊ |
322 | ␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x100);␊ |
323 | ␊ |
324 | ␉ptr = (long*)(dev0 + offset + 0x121C);␊ |
325 | ␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊ |
326 | ␊ |
327 | ␉ptr = (long*)(dev0 + offset + 0x1214);␉␊ |
328 | ␉Precharge_Register = *ptr & 0xFFFFFFFF;␊ |
329 | ␊ |
330 | ␉// Series only support DDR2␊ |
331 | ␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊ |
332 | ␊ |
333 | ␉// CAS Latency (tCAS)␊ |
334 | ␉Platform.RAM.CAS = ((ODT_Control_Register >> 23) & 7) + 3;␊ |
335 | ␊ |
336 | ␉// RAS-To-CAS (tRCD)␊ |
337 | ␉Platform.RAM.TRC = ((Precharge_Register >> 5) & 7) + 2;␊ |
338 | ␊ |
339 | ␉// RAS Precharge (tRP)␊ |
340 | ␉Platform.RAM.TRP= (Precharge_Register & 7) + 2;␊ |
341 | ␊ |
342 | ␉// RAS Active to precharge (tRAS)␊ |
343 | ␉Platform.RAM.RAS = (Precharge_Register >> 21) & 0x1F;␊ |
344 | ␊ |
345 | ␉if ((c0ckectrl >> 20 & 0xF) && (c1ckectrl >> 20 & 0xF)) {␊ |
346 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
347 | ␉} else {␊ |
348 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
349 | ␉}␊ |
350 | }␊ |
351 | ␊ |
352 | // Get P35 Memory Timings␊ |
353 | static void get_timings_p35(pci_dt_t *dram_dev)␊ |
354 | {␊ |
355 | ␉// Thanks for CDH optis␊ |
356 | ␉unsigned long dev0, Memory_Check, c0ckectrl, c1ckectrl, offset;␊ |
357 | ␉unsigned long ODT_Control_Register, Precharge_Register, ACT_Register, Read_Register, Misc_Register;␊ |
358 | ␉long *ptr;␊ |
359 | ␊ |
360 | ␉//Device_ID = pci_config_read16(dram_dev->dev.addr, 0x02);␊ |
361 | ␉//Device_ID &= 0xFFFF;␊ |
362 | ␊ |
363 | ␉// Now, read MMR Base Address␊ |
364 | ␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊ |
365 | ␉dev0 &= 0xFFFFC000;␊ |
366 | ␊ |
367 | ␉ptr = (long*)(dev0 + 0x260);␊ |
368 | ␉c0ckectrl = *ptr & 0xFFFFFFFF;␊ |
369 | ␊ |
370 | ␉ptr = (long*)(dev0 + 0x660);␊ |
371 | ␉c1ckectrl = *ptr & 0xFFFFFFFF;␊ |
372 | ␊ |
373 | ␉// If DIMM 0 not populated, check DIMM 1␊ |
374 | ␉((c0ckectrl) >> 20 & 0xF) ? (offset = 0) : (offset = 0x400);␊ |
375 | ␊ |
376 | ␉ptr = (long*)(dev0 + offset + 0x265);␊ |
377 | ␉ODT_Control_Register = *ptr & 0xFFFFFFFF;␊ |
378 | ␊ |
379 | ␉ptr = (long*)(dev0 + offset + 0x25D);␊ |
380 | ␉Precharge_Register = *ptr & 0xFFFFFFFF;␊ |
381 | ␊ |
382 | ␉ptr = (long*)(dev0 + offset + 0x252);␊ |
383 | ␉ACT_Register = *ptr & 0xFFFFFFFF;␊ |
384 | ␊ |
385 | ␉ptr = (long*)(dev0 + offset + 0x258);␊ |
386 | ␉Read_Register = *ptr & 0xFFFFFFFF;␊ |
387 | ␊ |
388 | ␉ptr = (long*)(dev0 + offset + 0x244);␊ |
389 | ␉Misc_Register = *ptr & 0xFFFFFFFF;␊ |
390 | ␊ |
391 | ␉ptr = (long*)(dev0 + offset + 0x1E8);␊ |
392 | ␉Memory_Check = *ptr & 0xFFFFFFFF;␊ |
393 | ␊ |
394 | ␉// On P45, check 1A8␊ |
395 | ␉if(dram_dev->device_id > 0x2E00) {␊ |
396 | ␉␉ptr = (long*)(dev0 + offset + 0x1A8);␊ |
397 | ␉␉Memory_Check = *ptr & 0xFFFFFFFF;␊ |
398 | ␉␉Memory_Check >>= 2;␊ |
399 | ␉␉Memory_Check &= 1;␊ |
400 | ␉␉Memory_Check = !Memory_Check;␊ |
401 | ␉} else {␊ |
402 | ␉␉ptr = (long*)(dev0 + offset + 0x1E8);␊ |
403 | ␉␉Memory_Check = *ptr & 0xFFFFFFFF;␊ |
404 | ␉}␊ |
405 | ␊ |
406 | ␉// Determine DDR-II or DDR-III␊ |
407 | ␉if (Memory_Check & 1) {␊ |
408 | ␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊ |
409 | ␉} else {␊ |
410 | ␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊ |
411 | ␉}␊ |
412 | ␊ |
413 | ␉// CAS Latency (tCAS)␊ |
414 | ␉if(dram_dev->device_id > 0x2E00) {␊ |
415 | ␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊ |
416 | ␉} else {␊ |
417 | ␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊ |
418 | ␉}␊ |
419 | ␊ |
420 | ␉// RAS-To-CAS (tRCD)␊ |
421 | ␉Platform.RAM.TRC = (Read_Register >> 17) & 0xF;␊ |
422 | ␊ |
423 | ␉// RAS Precharge (tRP)␊ |
424 | ␉Platform.RAM.TRP = (ACT_Register >> 13) & 0xF;␊ |
425 | ␊ |
426 | ␉// RAS Active to precharge (tRAS)␊ |
427 | ␉Platform.RAM.RAS = Precharge_Register & 0x3F;␊ |
428 | ␊ |
429 | ␉// Channel configuration␊ |
430 | ␉if (((c0ckectrl >> 20) & 0xF) && ((c1ckectrl >> 20) & 0xF)) {␊ |
431 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
432 | ␉} else {␊ |
433 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
434 | ␉}␊ |
435 | }␊ |
436 | ␊ |
437 | // Get Nehalem Memory Timings␊ |
438 | static void get_timings_nhm(pci_dt_t *dram_dev)␊ |
439 | {␊ |
440 | ␉unsigned long mc_channel_bank_timing, mc_control, mc_channel_mrs_value;␊ |
441 | ␉int fvc_bn = 4;␊ |
442 | ␊ |
443 | ␉// Find which channels are populated␊ |
444 | ␉mc_control = pci_config_read16(PCIADDR(nhm_bus, 3, 0), 0x48);␊ |
445 | ␉mc_control = (mc_control >> 8) & 0x7;␊ |
446 | ␊ |
447 | ␉// DDR-III␊ |
448 | ␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊ |
449 | ␊ |
450 | ␉// Get the first valid channel␊ |
451 | ␉if(mc_control & 1) {␊ |
452 | ␉␉fvc_bn = 4; ␊ |
453 | ␉} else if(mc_control & 2) {␊ |
454 | ␉␉fvc_bn = 5; ␊ |
455 | ␉} else if(mc_control & 7) {␊ |
456 | ␉␉fvc_bn = 6; ␊ |
457 | ␉}␊ |
458 | ␊ |
459 | ␉// Now, detect timings␊ |
460 | ␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊ |
461 | ␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊ |
462 | ␊ |
463 | ␉// CAS Latency (tCAS)␊ |
464 | ␉Platform.RAM.CAS = ((mc_channel_mrs_value >> 4) & 0xF ) + 4;␊ |
465 | ␊ |
466 | ␉// RAS-To-CAS (tRCD)␊ |
467 | ␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊ |
468 | ␊ |
469 | ␉// RAS Active to precharge (tRAS)␊ |
470 | ␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊ |
471 | ␊ |
472 | ␉// RAS Precharge (tRP)␊ |
473 | ␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊ |
474 | ␊ |
475 | ␉// Single , Dual or Triple Channels␊ |
476 | ␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 ) {␊ |
477 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_SINGLE;␊ |
478 | ␉} else if (mc_control == 7) {␊ |
479 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_TRIPLE;␊ |
480 | ␉} else ␉{␊ |
481 | ␉␉Platform.RAM.Channels = SMB_MEM_CHANNEL_DUAL;␊ |
482 | ␉}␊ |
483 | }␊ |
484 | ␊ |
485 | static struct mem_controller_t dram_controllers[] = {␊ |
486 | ␊ |
487 | ␉// Default unknown chipset␊ |
488 | ␉{ 0, 0, "",␉NULL, NULL, NULL },␊ |
489 | ␊ |
490 | ␉// Intel␊ |
491 | //␉{ 0x8086, 0x0100, "2rd Gen Core processor",␉NULL, NULL, NULL },␊ |
492 | //␉{ 0x8086, 0x0104, "2rd Gen Core processor",␉NULL, NULL, NULL },␊ |
493 | //␉{ 0x8086, 0x010C, "Xeon E3-1200/2rd Gen Core processor",␉NULL, NULL, NULL },␊ |
494 | //␉{ 0x8086, 0x0150, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊ |
495 | //␉{ 0x8086, 0x0154, "3rd Gen Core processor",␉NULL, NULL, NULL },␊ |
496 | //␉{ 0x8086, 0x0158, "Xeon E3-1200 v2/Ivy Bridge",␉NULL, NULL, NULL },␊ |
497 | //␉{ 0x8086, 0x015C, "Xeon E3-1200 v2/3rd Gen Core processor",␉NULL, NULL, NULL },␊ |
498 | ␊ |
499 | //␉{ 0x8086, 0x0BF0, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
500 | //␉{ 0x8086, 0x0BF1, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
501 | //␉{ 0x8086, 0x0BF2, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
502 | //␉{ 0x8086, 0x0BF3, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
503 | //␉{ 0x8086, 0x0BF4, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
504 | //␉{ 0x8086, 0x0BF5, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
505 | //␉{ 0x8086, 0x0BF6, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
506 | //␉{ 0x8086, 0x0BF7, "Atom Processor D2xxx/N2xxx",␉NULL, NULL, NULL },␊ |
507 | ␊ |
508 | //␉{ 0x8086, 0x0C00, "Haswell",␉NULL, NULL, NULL },␊ |
509 | //␉{ 0x8086, 0x0C04, "Haswell",␉NULL, NULL, NULL },␊ |
510 | //␉{ 0x8086, 0x0C08, "Haswell",␉NULL, NULL, NULL },␊ |
511 | ␊ |
512 | ␉{ 0x8086, 0x7190, "VMWare",␉NULL, NULL, NULL },␊ |
513 | ␊ |
514 | ␉{ 0x8086, 0x1A30, "82845 845 [Brookdale]",␉NULL, NULL, NULL },␊ |
515 | ␉␊ |
516 | ␉{ 0x8086, 0x2970, "82946GZ/PL/GL",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊ |
517 | ␉{ 0x8086, 0x2990, "82Q963/Q965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊ |
518 | ␉{ 0x8086, 0x29A0, "P965/G965",␉␉setup_p35, get_fsb_i965,␉get_timings_i965␉},␊ |
519 | ␊ |
520 | ␉{ 0x8086, 0x2A00, "GM965/GL960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊ |
521 | ␉{ 0x8086, 0x2A10, "GME965/GLE960",␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊ |
522 | ␉{ 0x8086, 0x2A40, "PM/GM45/47",␉␉setup_p35, get_fsb_im965,␉get_timings_im965␉},␊ |
523 | ␊ |
524 | ␉{ 0x8086, 0x29B0, "82Q35 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
525 | ␉{ 0x8086, 0x29C0, "82G33/G31/P35/P31",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
526 | ␉{ 0x8086, 0x29D0, "82Q33 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
527 | ␉{ 0x8086, 0x29E0, "82X38/X48 Express",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
528 | ␉{ 0x8086, 0x29F0, "3200/3210",␉␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
529 | ␊ |
530 | ␉{ 0x8086, 0x2E00, "Eaglelake",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
531 | ␉{ 0x8086, 0x2E10, "Q45/Q43",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
532 | ␉{ 0x8086, 0x2E20, "P45/G45",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
533 | ␉{ 0x8086, 0x2E30, "G41",␉␉setup_p35, get_fsb_i965,␉get_timings_p35␉␉},␊ |
534 | //␉{ 0x8086, 0x2E40, "4 Series Chipset",␉␉NULL, NULL, NULL },␊ |
535 | //␉{ 0x8086, 0x2E90, "4 Series Chipset",␉␉NULL, NULL, NULL },␊ |
536 | ␊ |
537 | ␉{ 0x8086, 0xD131, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
538 | ␉{ 0x8086, 0xD132, "NHM IMC",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
539 | ␉{ 0x8086, 0x3400, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
540 | ␉{ 0x8086, 0x3401, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
541 | ␉{ 0x8086, 0x3402, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
542 | ␉{ 0x8086, 0x3403, "5500",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
543 | ␉{ 0x8086, 0x3404, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
544 | ␉{ 0x8086, 0x3405, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
545 | ␉{ 0x8086, 0x3406, "5520",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
546 | ␉{ 0x8086, 0x3407, "5520/5500/X58",␉␉setup_nhm, get_fsb_nhm,␉␉get_timings_nhm␉␉},␊ |
547 | };␊ |
548 | ␊ |
549 | static const char *memory_channel_types[] =␊ |
550 | {␊ |
551 | ␉"Unknown", "Single", "Dual", "Triple"␊ |
552 | };␊ |
553 | ␊ |
554 | void scan_dram_controller(pci_dt_t *dram_dev)␊ |
555 | {␊ |
556 | ␉int i;␊ |
557 | ␉for(i = 1; i < sizeof(dram_controllers) / sizeof(dram_controllers[0]); i++) {␊ |
558 | ␉␉if ((dram_controllers[i].vendor == dram_dev->vendor_id) && (dram_controllers[i].device == dram_dev->device_id)) {␊ |
559 | ␉␉␉verbose("%s%s DRAM Controller [%4x:%4x] at %02x:%02x.%x\n", ␊ |
560 | ␉␉␉␉(dram_dev->vendor_id == 0x8086) ? "Intel Corporation " : "" ,␊ |
561 | ␉␉␉␉dram_controllers[i].name, dram_dev->vendor_id, dram_dev->device_id,␊ |
562 | ␉␉␉␉dram_dev->dev.bits.bus, dram_dev->dev.bits.dev, dram_dev->dev.bits.func);␊ |
563 | ␊ |
564 | ␉␉␉if (dram_controllers[i].initialise != NULL) {␊ |
565 | ␉␉␉␉dram_controllers[i].initialise(dram_dev);␊ |
566 | ␉␉␉}␊ |
567 | ␊ |
568 | ␉␉␉if (dram_controllers[i].poll_timings != NULL) {␊ |
569 | ␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊ |
570 | ␉␉␉}␊ |
571 | ␊ |
572 | ␉␉␉if (dram_controllers[i].poll_speed != NULL) {␊ |
573 | ␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊ |
574 | ␉␉␉}␊ |
575 | ␊ |
576 | ␉␉␉verbose("Frequency detected: %d MHz (%d) %s Channel \n\tCAS:%d tRC:%d tRP:%d RAS:%d (%d-%d-%d-%d)\n", ␊ |
577 | ␉␉␉␉(uint32_t)Platform.RAM.Frequency / 1000000,␊ |
578 | ␉␉␉␉(uint32_t)Platform.RAM.Frequency / 500000,␊ |
579 | ␉␉␉␉memory_channel_types[Platform.RAM.Channels]␊ |
580 | ␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊ |
581 | ␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS);␊ |
582 | //␉␉␉getchar();␊ |
583 | ␉␉}␊ |
584 | ␉}␊ |
585 | }␊ |
586 |