1 | /*␊ |
2 | *␉HDA injector / Audio Enabler␊ |
3 | *␊ |
4 | *␉Copyright (C) 2012␉Chameleon Team␊ |
5 | *␉Edit by Fabio (ErmaC)␊ |
6 | *␊ |
7 | *␉HDA injector is free software: you can redistribute it and/or modify␊ |
8 | *␉it under the terms of the GNU General Public License as published by␊ |
9 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
10 | *␉(at your option) any later version.␊ |
11 | *␊ |
12 | *␉HDA injector is distributed in the hope that it will be useful,␊ |
13 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
14 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
15 | *␉GNU General Public License for more details.␊ |
16 | *␊ |
17 | *␉Alternatively you can choose to comply with APSL␊ |
18 | *␊ |
19 | *␉Permission is hereby granted, free of charge, to any person obtaining a␊ |
20 | *␉copy of this software and associated documentation files (the "Software"),␊ |
21 | *␉to deal in the Software without restriction, including without limitation␊ |
22 | *␉the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
23 | *␉and/or sell copies of the Software, and to permit persons to whom the␊ |
24 | *␉Software is furnished to do so, subject to the following conditions:␊ |
25 | *␊ |
26 | *␉The above copyright notice and this permission notice shall be included in␊ |
27 | *␉all copies or substantial portions of the Software.␊ |
28 | *␊ |
29 | ******************************************************************************␊ |
30 | * http://www.leidinger.net/FreeBSD/dox/dev_sound/html/df/d54/hdac_8c_source.html␊ |
31 | *␊ |
32 | * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>␊ |
33 | * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>␊ |
34 | * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>␊ |
35 | * All rights reserved.␊ |
36 | *␊ |
37 | * Redistribution and use in source and binary forms, with or without␊ |
38 | * modification, are permitted provided that the following conditions␊ |
39 | * are met:␊ |
40 | * 1. Redistributions of source code must retain the above copyright␊ |
41 | * notice, this list of conditions and the following disclaimer.␊ |
42 | * 2. Redistributions in binary form must reproduce the above copyright␊ |
43 | * notice, this list of conditions and the following disclaimer in the␊ |
44 | * documentation and/or other materials provided with the distribution.␊ |
45 | *␊ |
46 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND␊ |
47 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE␊ |
48 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE␊ |
49 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE␊ |
50 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL␊ |
51 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS␊ |
52 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)␊ |
53 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT␊ |
54 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY␊ |
55 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF␊ |
56 | * SUCH DAMAGE.␊ |
57 | *␊ |
58 | * Intel High Definition Audio (Controller) driver for FreeBSD.␊ |
59 | *␊ |
60 | ******************************************************************************/␊ |
61 | ␊ |
62 | #ifndef __LIBSAIO_HDA_H␊ |
63 | #define __LIBSAIO_HDA_H␊ |
64 | ␊ |
65 | bool setup_hda_devprop(pci_dt_t *hda_dev);␊ |
66 | ␊ |
67 | struct hda_controller_devices;␊ |
68 | typedef struct␊ |
69 | {␊ |
70 | ␉uint32_t␉model;␊ |
71 | ␉char␉␉*desc;␊ |
72 | ␉// char␉␉quirks_on;␊ |
73 | ␉// char␉␉quirks_off;␊ |
74 | } hda_controller_devices;␊ |
75 | ␊ |
76 | /*␊ |
77 | struct hdacc_codecs;␊ |
78 | typedef struct␊ |
79 | {␊ |
80 | ␉uint32_t cid;␊ |
81 | ␉uint16_t revid;␊ |
82 | ␉char *name;␊ |
83 | } hdacc_codecs;␊ |
84 | */␊ |
85 | ␊ |
86 | /****************************************************************************␊ |
87 | * Miscellanious defines␊ |
88 | ****************************************************************************/␊ |
89 | ␊ |
90 | /* Controller models */␊ |
91 | #define HDA_MODEL_CONSTRUCT(vendor, model) (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))␊ |
92 | ␊ |
93 | /* Intel */␊ |
94 | #define INTEL_VENDORID␉␉0x8086␊ |
95 | #define HDA_INTEL_OAK␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x080a) // NEW␊ |
96 | #define HDA_INTEL_BAY␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) // NEW␊ |
97 | #define HDA_INTEL_HSW1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c)␊ |
98 | #define HDA_INTEL_HSW2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c)␊ |
99 | #define HDA_INTEL_HSW3␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c)␊ |
100 | #define HDA_INTEL_CPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1c20)␊ |
101 | #define HDA_INTEL_PATSBURG␉HDA_MODEL_CONSTRUCT(INTEL, 0x1d20)␊ |
102 | #define HDA_INTEL_PPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) // Macmini6,2␊ |
103 | #define HDA_INTEL_82801F␉HDA_MODEL_CONSTRUCT(INTEL, 0x2668)␊ |
104 | #define HDA_INTEL_63XXESB␉HDA_MODEL_CONSTRUCT(INTEL, 0x269a)␊ |
105 | #define HDA_INTEL_82801G␉HDA_MODEL_CONSTRUCT(INTEL, 0x27d8)␊ |
106 | #define HDA_INTEL_82801H␉HDA_MODEL_CONSTRUCT(INTEL, 0x284b)␊ |
107 | #define HDA_INTEL_82801I␉HDA_MODEL_CONSTRUCT(INTEL, 0x293e)␊ |
108 | #define HDA_INTEL_82801JI␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e)␊ |
109 | #define HDA_INTEL_82801JD␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e)␊ |
110 | #define HDA_INTEL_PCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b56)␊ |
111 | #define HDA_INTEL_PCH2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b57)␊ |
112 | #define HDA_INTEL_MACBOOKPRO92␉HDA_MODEL_CONSTRUCT(INTEL, 0x7270) // NEW␊ |
113 | #define HDA_INTEL_SCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x811b)␊ |
114 | #define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) // NEW␊ |
115 | #define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) // NEW␊ |
116 | #define HDA_INTEL_WCPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0)␊ |
117 | #define HDA_INTEL_WELLS1␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d20)␊ |
118 | #define HDA_INTEL_WELLS2␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d21)␊ |
119 | #define HDA_INTEL_LPTLP1␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c20)␊ |
120 | #define HDA_INTEL_LPTLP2␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c21)␊ |
121 | #define HDA_INTEL_ALL␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xffff)␊ |
122 | ␊ |
123 | /* Nvidia */␊ |
124 | #define NVIDIA_VENDORID␉␉0x10de␊ |
125 | // AppleHDA binary contain 0a00de10 (10de000a)␊ |
126 | // AppleHDAController binary contain de10ea0b (10de0bea)␊ |
127 | #define HDA_NVIDIA_MCP51␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)␊ |
128 | #define HDA_NVIDIA_MCP55␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)␊ |
129 | #define HDA_NVIDIA_MCP61_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)␊ |
130 | #define HDA_NVIDIA_MCP61_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)␊ |
131 | #define HDA_NVIDIA_MCP65_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)␊ |
132 | #define HDA_NVIDIA_MCP65_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)␊ |
133 | #define HDA_NVIDIA_MCP67_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)␊ |
134 | #define HDA_NVIDIA_MCP67_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)␊ |
135 | #define HDA_NVIDIA_MCP78_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774)␊ |
136 | #define HDA_NVIDIA_MCP78_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775)␊ |
137 | #define HDA_NVIDIA_MCP78_3␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776)␊ |
138 | #define HDA_NVIDIA_MCP78_4␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777)␊ |
139 | #define HDA_NVIDIA_MCP73_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc)␊ |
140 | #define HDA_NVIDIA_MCP73_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd)␊ |
141 | #define HDA_NVIDIA_MCP79_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0)␊ |
142 | #define HDA_NVIDIA_MCP79_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1)␊ |
143 | #define HDA_NVIDIA_MCP79_3␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2)␊ |
144 | #define HDA_NVIDIA_MCP79_4␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3)␊ |
145 | #define HDA_NVIDIA_0BE2␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be2)␊ |
146 | #define HDA_NVIDIA_0BE3␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be3) // [GeForce 210] HDAcodec␊ |
147 | #define HDA_NVIDIA_0BE4␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be4) // [GeForge GT 240] HDACodec 10de000d (0d00de10)␊ |
148 | #define HDA_NVIDIA_GT100␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be5) // [GeForge GTX 470] HDACodec 10de0010 (1000de10)␊ |
149 | #define HDA_NVIDIA_GT106␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be9)␊ |
150 | #define HDA_NVIDIA_GT108␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bea) // HDACodec ␊ |
151 | #define HDA_NVIDIA_GT104␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0beb)␊ |
152 | #define HDA_NVIDIA_GT116␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bee)␊ |
153 | #define HDA_NVIDIA_MCP89_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94)␊ |
154 | #define HDA_NVIDIA_MCP89_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95)␊ |
155 | #define HDA_NVIDIA_MCP89_3␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96)␊ |
156 | #define HDA_NVIDIA_MCP89_4␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97)␊ |
157 | #define HDA_NVIDIA_GF119␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e08)␊ |
158 | #define HDA_NVIDIA_GF110_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e09)␊ |
159 | #define HDA_NVIDIA_GF110_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0c) // HDACodec de101600 (10de0016), Controller Binary de100c0e x2␊ |
160 | #define HDA_NVIDIA_GK104␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0a)␊ |
161 | #define HDA_NVIDIA_GK106␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0b)␊ |
162 | #define HDA_NVIDIA_GK110␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1a)␊ |
163 | #define HDA_NVIDIA_GK107␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1b) // HDACodec de104200 (10de0042)␊ |
164 | #define HDA_NVIDIA_ALL␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)␊ |
165 | ␊ |
166 | /* ATI */␊ |
167 | #define ATI_VENDORID␉␉0x1002␊ |
168 | #define HDA_ATI_SB450␉␉HDA_MODEL_CONSTRUCT(ATI, 0x437b)␊ |
169 | #define HDA_ATI_SB600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x4383)␊ |
170 | #define HDA_ATI_RS600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x793b)␊ |
171 | #define HDA_ATI_RS690␉␉HDA_MODEL_CONSTRUCT(ATI, 0x7919)␊ |
172 | #define HDA_ATI_RS780␉␉HDA_MODEL_CONSTRUCT(ATI, 0x960f)␊ |
173 | #define HDA_ATI_RS880␉␉HDA_MODEL_CONSTRUCT(ATI, 0x970f)␊ |
174 | #define HDA_ATI_TRINITY␉␉HDA_MODEL_CONSTRUCT(ATI, 0x9902)␊ |
175 | #define HDA_ATI_R600␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa00)␊ |
176 | #define HDA_ATI_RV630␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa08)␊ |
177 | #define HDA_ATI_RV610␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa10)␊ |
178 | #define HDA_ATI_RV670␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa18)␊ |
179 | #define HDA_ATI_RV635␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa20)␊ |
180 | #define HDA_ATI_RV620␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa28)␊ |
181 | #define HDA_ATI_RV770␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa30)␊ |
182 | #define HDA_ATI_RV730␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa38)␊ |
183 | #define HDA_ATI_RV710␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa40)␊ |
184 | #define HDA_ATI_RV740␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa48)␊ |
185 | #define HDA_ATI_RV870␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa50)␊ |
186 | #define HDA_ATI_RV840␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa58) // Codec 021001aa (1002aa01)␊ |
187 | #define HDA_ATI_RV830␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa60)␊ |
188 | #define HDA_ATI_RV810␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa68)␊ |
189 | #define HDA_ATI_RV970␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa80)␊ |
190 | #define HDA_ATI_RV940␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa88)␊ |
191 | #define HDA_ATI_RV930␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa90)␊ |
192 | #define HDA_ATI_RV910␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa98)␊ |
193 | #define HDA_ATI_R1000␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa0)␊ |
194 | #define HDA_ATI_VERDE␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaab0)␊ |
195 | #define HDA_ATI_ALL␉␉HDA_MODEL_CONSTRUCT(ATI, 0xffff)␊ |
196 | ␊ |
197 | /* RDC */␊ |
198 | #define RDC_VENDORID␉␉0x17f3␊ |
199 | #define HDA_RDC_M3010␉␉HDA_MODEL_CONSTRUCT(RDC, 0x3010)␊ |
200 | ␊ |
201 | /* VIA */␊ |
202 | #define VIA_VENDORID␉␉0x1106␊ |
203 | #define HDA_VIA_VT82XX␉␉HDA_MODEL_CONSTRUCT(VIA, 0x3288)␊ |
204 | #define HDA_VIA_ALL␉␉HDA_MODEL_CONSTRUCT(VIA, 0xffff)␊ |
205 | ␊ |
206 | /* SiS */␊ |
207 | #define SIS_VENDORID␉␉0x1039␊ |
208 | #define HDA_SIS_966␉␉HDA_MODEL_CONSTRUCT(SIS, 0x7502)␊ |
209 | #define HDA_SIS_ALL␉␉HDA_MODEL_CONSTRUCT(SIS, 0xffff)␊ |
210 | ␊ |
211 | /* ULI */␊ |
212 | #define ULI_VENDORID␉␉0x10b9␊ |
213 | #define HDA_ULI_M5461␉␉HDA_MODEL_CONSTRUCT(ULI, 0x5461)␊ |
214 | #define HDA_ULI_ALL␉␉HDA_MODEL_CONSTRUCT(ULI, 0xffff)␊ |
215 | ␊ |
216 | /* OEM/subvendors */␊ |
217 | ␊ |
218 | /* Intel */␊ |
219 | #define INTEL_D101GGC_SUBVENDOR␉HDA_MODEL_CONSTRUCT(INTEL, 0xd600)␊ |
220 | ␊ |
221 | /* HP/Compaq */␊ |
222 | #define HP_VENDORID␉␉0x103c␊ |
223 | #define HP_V3000_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30b5)␊ |
224 | #define HP_NX7400_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30a2)␊ |
225 | #define HP_NX6310_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30aa)␊ |
226 | #define HP_NX6325_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30b0)␊ |
227 | #define HP_XW4300_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x3013)␊ |
228 | #define HP_3010_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x3010)␊ |
229 | #define HP_DV5000_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x30a5)␊ |
230 | #define HP_DC7700S_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x2801)␊ |
231 | #define HP_DC7700_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0x2802)␊ |
232 | #define HP_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(HP, 0xffff)␊ |
233 | /* What is wrong with XN 2563 anyway? (Got the picture ?) */␊ |
234 | #define HP_NX6325_SUBVENDORX␉0x103c30b0␊ |
235 | ␊ |
236 | /* Dell */␊ |
237 | #define DELL_VENDORID␉␉0x1028␊ |
238 | #define DELL_D630_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01f9)␊ |
239 | #define DELL_D820_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01cc)␊ |
240 | #define DELL_V1400_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x0227)␊ |
241 | #define DELL_V1500_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x0228)␊ |
242 | #define DELL_I1300_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01c9)␊ |
243 | #define DELL_XPSM1210_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01d7)␊ |
244 | #define DELL_OPLX745_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0x01da)␊ |
245 | #define DELL_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(DELL, 0xffff)␊ |
246 | ␊ |
247 | /* Clevo */␊ |
248 | #define CLEVO_VENDORID␉␉0x1558␊ |
249 | #define CLEVO_D900T_SUBVENDOR␉HDA_MODEL_CONSTRUCT(CLEVO, 0x0900)␊ |
250 | #define CLEVO_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(CLEVO, 0xffff)␊ |
251 | ␊ |
252 | /* Acer */␊ |
253 | #define ACER_VENDORID␉␉0x1025␊ |
254 | #define ACER_A5050_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x010f)␊ |
255 | #define ACER_A4520_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x0127)␊ |
256 | #define ACER_A4710_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x012f)␊ |
257 | #define ACER_A4715_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x0133)␊ |
258 | #define ACER_3681WXM_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x0110)␊ |
259 | #define ACER_T6292_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x011b)␊ |
260 | #define ACER_T5320_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0x011f)␊ |
261 | #define ACER_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ACER, 0xffff)␊ |
262 | ␊ |
263 | /* Asus */␊ |
264 | #define ASUS_VENDORID␉␉0x1043␊ |
265 | #define ASUS_A8X_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1153)␊ |
266 | #define ASUS_U5F_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1263)␊ |
267 | #define ASUS_W6F_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1263)␊ |
268 | #define ASUS_A7M_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1323)␊ |
269 | #define ASUS_F3JC_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1338)␊ |
270 | #define ASUS_G2K_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1339)␊ |
271 | #define ASUS_A7T_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x13c2)␊ |
272 | #define ASUS_W2J_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1971)␊ |
273 | #define ASUS_M5200_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x1993)␊ |
274 | #define ASUS_P5PL2_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x817f)␊ |
275 | #define ASUS_P1AH2_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)␊ |
276 | #define ASUS_M2NPVMX_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81cb)␊ |
277 | #define ASUS_M2V_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81e7)␊ |
278 | #define ASUS_P5BWD_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x81ec)␊ |
279 | #define ASUS_M2N_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0x8234)␊ |
280 | #define ASUS_A8NVMCSM_SUBVENDOR␉HDA_MODEL_CONSTRUCT(NVIDIA, 0xcb84)␊ |
281 | #define ASUS_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(ASUS, 0xffff)␊ |
282 | ␊ |
283 | /* IBM / Lenovo */␊ |
284 | #define IBM_VENDORID␉␉0x1014␊ |
285 | #define IBM_M52_SUBVENDOR␉HDA_MODEL_CONSTRUCT(IBM, 0x02f6)␊ |
286 | #define IBM_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(IBM, 0xffff)␊ |
287 | ␊ |
288 | /* Lenovo */␊ |
289 | #define LENOVO_VENDORID␉␉0x17aa␊ |
290 | #define LENOVO_3KN100_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x2066)␊ |
291 | #define LENOVO_3KN200_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x384e)␊ |
292 | #define LENOVO_B450_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x3a0d)␊ |
293 | #define LENOVO_TCA55_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x1015)␊ |
294 | #define LENOVO_X300_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x20ac)␊ |
295 | #define LENOVO_X1_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21e8)␊ |
296 | #define LENOVO_X1CRBN_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21f9)␊ |
297 | #define LENOVO_X220_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21da)␊ |
298 | #define LENOVO_T420_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21ce)␊ |
299 | #define LENOVO_T430_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21f3)␊ |
300 | #define LENOVO_T430S_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21fb)␊ |
301 | #define LENOVO_T520_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21cf)␊ |
302 | #define LENOVO_T530_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0x21f6)␊ |
303 | #define LENOVO_ALL_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(LENOVO, 0xffff)␊ |
304 | ␊ |
305 | /* Samsung */␊ |
306 | #define SAMSUNG_VENDORID␉0x144d␊ |
307 | #define SAMSUNG_Q1_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SAMSUNG, 0xc027)␊ |
308 | #define SAMSUNG_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SAMSUNG, 0xffff)␊ |
309 | ␊ |
310 | /* Medion ? */␊ |
311 | #define MEDION_VENDORID␉␉␉0x161f␊ |
312 | #define MEDION_MD95257_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MEDION, 0x203d)␊ |
313 | #define MEDION_ALL_SUBVENDOR␉␉HDA_MODEL_CONSTRUCT(MEDION, 0xffff)␊ |
314 | ␊ |
315 | /* Apple Computer Inc. */␊ |
316 | #define APPLE_VENDORID␉␉0x106b␊ |
317 | #define APPLE_MB3_SUBVENDOR␉HDA_MODEL_CONSTRUCT(APPLE, 0x00a1)␊ |
318 | ␊ |
319 | /* Sony */␊ |
320 | #define SONY_VENDORID␉␉0x104d␊ |
321 | #define SONY_S5_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SONY, 0x81cc)␊ |
322 | #define SONY_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(SONY, 0xffff)␊ |
323 | ␊ |
324 | /*␊ |
325 | * Apple Intel MacXXXX seems using Sigmatel codec/vendor id␊ |
326 | * instead of their own, which is beyond my comprehension␊ |
327 | * (see HDA_CODEC_STAC9221 below).␊ |
328 | */␊ |
329 | #define APPLE_INTEL_MAC␉␉0x76808384␊ |
330 | #define APPLE_MACBOOKPRO55␉0xcb7910de␊ |
331 | ␊ |
332 | /* LG Electronics */␊ |
333 | #define LG_VENDORID␉␉0x1854␊ |
334 | #define LG_LW20_SUBVENDOR␉HDA_MODEL_CONSTRUCT(LG, 0x0018)␊ |
335 | #define LG_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(LG, 0xffff)␊ |
336 | ␊ |
337 | /* Fujitsu Siemens */␊ |
338 | #define FS_VENDORID␉␉0x1734␊ |
339 | #define FS_PA1510_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FS, 0x10b8)␊ |
340 | #define FS_SI1848_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FS, 0x10cd)␊ |
341 | #define FS_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FS, 0xffff)␊ |
342 | ␊ |
343 | /* Fujitsu Limited */␊ |
344 | #define FL_VENDORID␉␉0x10cf␊ |
345 | #define FL_S7020D_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FL, 0x1326)␊ |
346 | #define FL_U1010_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FL, 0x142d)␊ |
347 | #define FL_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(FL, 0xffff)␊ |
348 | ␊ |
349 | /* Toshiba */␊ |
350 | #define TOSHIBA_VENDORID␉0x1179␊ |
351 | #define TOSHIBA_U200_SUBVENDOR␉HDA_MODEL_CONSTRUCT(TOSHIBA, 0x0001)␊ |
352 | #define TOSHIBA_A135_SUBVENDOR␉HDA_MODEL_CONSTRUCT(TOSHIBA, 0xff01)␊ |
353 | #define TOSHIBA_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(TOSHIBA, 0xffff)␊ |
354 | ␊ |
355 | /* Micro-Star International (MSI) */␊ |
356 | #define MSI_VENDORID␉␉0x1462␊ |
357 | #define MSI_MS1034_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MSI, 0x0349)␊ |
358 | #define MSI_MS034A_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MSI, 0x034a)␊ |
359 | #define MSI_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(MSI, 0xffff)␊ |
360 | ␊ |
361 | /* Giga-Byte Technology */␊ |
362 | #define GB_VENDORID␉␉0x1458␊ |
363 | #define GB_G33S2H_SUBVENDOR␉HDA_MODEL_CONSTRUCT(GB, 0xa022)␊ |
364 | #define GP_ALL_SUBVENDOR␉HDA_MODEL_CONSTRUCT(GB, 0xffff)␊ |
365 | ␊ |
366 | /* Uniwill ? */␊ |
367 | #define UNIWILL_VENDORID␉0x1584␊ |
368 | #define UNIWILL_9075_SUBVENDOR␉HDA_MODEL_CONSTRUCT(UNIWILL, 0x9075)␊ |
369 | #define UNIWILL_9080_SUBVENDOR␉HDA_MODEL_CONSTRUCT(UNIWILL, 0x9080)␊ |
370 | ␊ |
371 | //#define HDEF_PATH "PciRoot(0x0)/Pci(0x1b,0x0)"␊ |
372 | //#define PINCONF_LEN ( sizeof(default_PinConfiguration) / sizeof(uint8_t) )␊ |
373 | #define HDA0_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) )␊ |
374 | #define HDA1_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) )␊ |
375 | ␊ |
376 | /* codec information */␊ |
377 | #define HDA_CODEC_CONSTRUCT(vendor, id) (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))␊ |
378 | ␊ |
379 | /* Cirrus Logic */␊ |
380 | #define CIRRUSLOGIC_VENDORID 0x1013␊ |
381 | #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206)␊ |
382 | #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207)␊ |
383 | #define HDA_CODEC_CS4210 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4210)␊ |
384 | #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff)␊ |
385 | ␊ |
386 | /* Realtek */␊ |
387 | #define REALTEK_VENDORID 0x10ec␊ |
388 | #define HDA_CODEC_ALC221 HDA_CODEC_CONSTRUCT(REALTEK, 0x0221)␊ |
389 | #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)␊ |
390 | #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)␊ |
391 | #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267)␊ |
392 | #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)␊ |
393 | #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269)␊ |
394 | #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270)␊ |
395 | #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272)␊ |
396 | #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273)␊ |
397 | #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275)␊ |
398 | #define HDA_CODEC_ALC276 HDA_CODEC_CONSTRUCT(REALTEK, 0x0276)␊ |
399 | #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)␊ |
400 | #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662)␊ |
401 | #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663)␊ |
402 | #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665)␊ |
403 | #define HDA_CODEC_ALC670 HDA_CODEC_CONSTRUCT(REALTEK, 0x0670)␊ |
404 | #define HDA_CODEC_ALC680 HDA_CODEC_CONSTRUCT(REALTEK, 0x0680)␊ |
405 | #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)␊ |
406 | #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)␊ |
407 | #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)␊ |
408 | #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)␊ |
409 | #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)␊ |
410 | #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)␊ |
411 | #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887)␊ |
412 | #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)␊ |
413 | #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889)␊ |
414 | #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892)␊ |
415 | #define HDA_CODEC_ALC898 HDA_CODEC_CONSTRUCT(REALTEK, 0x0898)␊ |
416 | #define HDA_CODEC_ALC899 HDA_CODEC_CONSTRUCT(REALTEK, 0x0899)␊ |
417 | #define HDA_CODEC_ALC900 HDA_CODEC_CONSTRUCT(REALTEK, 0x0900)␊ |
418 | #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)␊ |
419 | ␊ |
420 | /* Motorola */␊ |
421 | #define MOTO_VENDORID 0x1057␊ |
422 | #define HDA_CODEC_MOTOXXXX HDA_CODEC_CONSTRUCT(MOTO, 0xffff)␊ |
423 | ␊ |
424 | /* Creative */␊ |
425 | #define CREATIVE_VENDORID 0x1102␊ |
426 | #define HDA_CODEC_CA0110 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000a)␊ |
427 | #define HDA_CODEC_CA0110_2 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000b)␊ |
428 | #define HDA_CODEC_SB0880 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000d)␊ |
429 | #define HDA_CODEC_CA0132 HDA_CODEC_CONSTRUCT(CREATIVE, 0x0011)␊ |
430 | #define HDA_CODEC_CAXXXX HDA_CODEC_CONSTRUCT(CREATIVE, 0xffff)␊ |
431 | ␊ |
432 | /* Analog Devices */␊ |
433 | #define ANALOGDEVICES_VENDORID 0x11d4␊ |
434 | #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a)␊ |
435 | #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882)␊ |
436 | #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883)␊ |
437 | #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884)␊ |
438 | #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a)␊ |
439 | #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b)␊ |
440 | #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)␊ |
441 | #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)␊ |
442 | #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)␊ |
443 | #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)␊ |
444 | #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987)␊ |
445 | #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)␊ |
446 | #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)␊ |
447 | #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a)␊ |
448 | #define HDA_CODEC_AD1989A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989a)␊ |
449 | #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b)␊ |
450 | #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)␊ |
451 | ␊ |
452 | /* CMedia */␊ |
453 | #define CMEDIA_VENDORID 0x13f6␊ |
454 | #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x9880)␊ |
455 | #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)␊ |
456 | ␊ |
457 | #define CMEDIA2_VENDORID 0x434d␊ |
458 | #define HDA_CODEC_CMI98802 HDA_CODEC_CONSTRUCT(CMEDIA2, 0x4980)␊ |
459 | #define HDA_CODEC_CMIXXXX2 HDA_CODEC_CONSTRUCT(CMEDIA2, 0xffff)␊ |
460 | ␊ |
461 | /* Sigmatel */␊ |
462 | #define SIGMATEL_VENDORID 0x8384␊ |
463 | #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612)␊ |
464 | #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613)␊ |
465 | #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614)␊ |
466 | #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615)␊ |
467 | #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616)␊ |
468 | #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617)␊ |
469 | #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)␊ |
470 | #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619)␊ |
471 | #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620)␊ |
472 | #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621)␊ |
473 | #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622)␊ |
474 | #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623)␊ |
475 | #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624)␊ |
476 | #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625)␊ |
477 | #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626)␊ |
478 | #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)␊ |
479 | #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628)␊ |
480 | #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629)␊ |
481 | #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634)␊ |
482 | #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636)␊ |
483 | #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638)␊ |
484 | #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639)␊ |
485 | #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645)␊ |
486 | #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646)␊ |
487 | #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661)␊ |
488 | #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662)␊ |
489 | #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664)␊ |
490 | #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)␊ |
491 | #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)␊ |
492 | #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682)␊ |
493 | #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)␊ |
494 | #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)␊ |
495 | #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691)␊ |
496 | #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698)␊ |
497 | #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699)␊ |
498 | #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0)␊ |
499 | #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1)␊ |
500 | #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2)␊ |
501 | #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3)␊ |
502 | #define HDA_CODEC_STAC9255 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a4)␊ |
503 | #define HDA_CODEC_STAC9255D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a5)␊ |
504 | #define HDA_CODEC_STAC9254 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a6)␊ |
505 | #define HDA_CODEC_STAC9254D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a7)␊ |
506 | #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880)␊ |
507 | #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882)␊ |
508 | #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)␊ |
509 | ␊ |
510 | /* IDT */␊ |
511 | #define IDT_VENDORID 0x111d␊ |
512 | #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603)␊ |
513 | #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604)␊ |
514 | #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605)␊ |
515 | #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608)␊ |
516 | #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674)␊ |
517 | #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675)␊ |
518 | #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676)␊ |
519 | #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0)␊ |
520 | #define HDA_CODEC_IDT92HD71B8_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b1)␊ |
521 | #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2)␊ |
522 | #define HDA_CODEC_IDT92HD71B7_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b3)␊ |
523 | #define HDA_CODEC_IDT92HD71B6 HDA_CODEC_CONSTRUCT(IDT, 0x76b4)␊ |
524 | #define HDA_CODEC_IDT92HD71B6_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b5)␊ |
525 | #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6)␊ |
526 | #define HDA_CODEC_IDT92HD71B5_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b7)␊ |
527 | #define HDA_CODEC_IDT92HD89C3 HDA_CODEC_CONSTRUCT(IDT, 0x76c0)␊ |
528 | #define HDA_CODEC_IDT92HD89C2 HDA_CODEC_CONSTRUCT(IDT, 0x76c1)␊ |
529 | #define HDA_CODEC_IDT92HD89C1 HDA_CODEC_CONSTRUCT(IDT, 0x76c2)␊ |
530 | #define HDA_CODEC_IDT92HD89B3 HDA_CODEC_CONSTRUCT(IDT, 0x76c3)␊ |
531 | #define HDA_CODEC_IDT92HD89B2 HDA_CODEC_CONSTRUCT(IDT, 0x76c4)␊ |
532 | #define HDA_CODEC_IDT92HD89B1 HDA_CODEC_CONSTRUCT(IDT, 0x76c5)␊ |
533 | #define HDA_CODEC_IDT92HD89E3 HDA_CODEC_CONSTRUCT(IDT, 0x76c6)␊ |
534 | #define HDA_CODEC_IDT92HD89E2 HDA_CODEC_CONSTRUCT(IDT, 0x76c7)␊ |
535 | #define HDA_CODEC_IDT92HD89E1 HDA_CODEC_CONSTRUCT(IDT, 0x76c8)␊ |
536 | #define HDA_CODEC_IDT92HD89D3 HDA_CODEC_CONSTRUCT(IDT, 0x76c9)␊ |
537 | #define HDA_CODEC_IDT92HD89D2 HDA_CODEC_CONSTRUCT(IDT, 0x76ca)␊ |
538 | #define HDA_CODEC_IDT92HD89D1 HDA_CODEC_CONSTRUCT(IDT, 0x76cb)␊ |
539 | #define HDA_CODEC_IDT92HD89F3 HDA_CODEC_CONSTRUCT(IDT, 0x76cc)␊ |
540 | #define HDA_CODEC_IDT92HD89F2 HDA_CODEC_CONSTRUCT(IDT, 0x76cd)␊ |
541 | #define HDA_CODEC_IDT92HD89F1 HDA_CODEC_CONSTRUCT(IDT, 0x76ce)␊ |
542 | #define HDA_CODEC_IDT92HD87B1_3 HDA_CODEC_CONSTRUCT(IDT, 0x76d1)␊ |
543 | #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4)␊ |
544 | #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5)␊ |
545 | #define HDA_CODEC_IDT92HD87B2_4 HDA_CODEC_CONSTRUCT(IDT, 0x76d9)␊ |
546 | #define HDA_CODEC_IDT92HD93BXX HDA_CODEC_CONSTRUCT(IDT, 0x76df)␊ |
547 | #define HDA_CODEC_IDT92HD91BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e0)␊ |
548 | #define HDA_CODEC_IDT92HD98BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e3)␊ |
549 | #define HDA_CODEC_IDT92HD99BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e5)␊ |
550 | #define HDA_CODEC_IDT92HD90BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e7)␊ |
551 | #define HDA_CODEC_IDT92HD66B1X5 HDA_CODEC_CONSTRUCT(IDT, 0x76e8)␊ |
552 | #define HDA_CODEC_IDT92HD66B2X5 HDA_CODEC_CONSTRUCT(IDT, 0x76e9)␊ |
553 | #define HDA_CODEC_IDT92HD66B3X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ea)␊ |
554 | #define HDA_CODEC_IDT92HD66C1X5 HDA_CODEC_CONSTRUCT(IDT, 0x76eb)␊ |
555 | #define HDA_CODEC_IDT92HD66C2X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ec)␊ |
556 | #define HDA_CODEC_IDT92HD66C3X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ed)␊ |
557 | #define HDA_CODEC_IDT92HD66B1X3 HDA_CODEC_CONSTRUCT(IDT, 0x76ee)␊ |
558 | #define HDA_CODEC_IDT92HD66B2X3 HDA_CODEC_CONSTRUCT(IDT, 0x76ef)␊ |
559 | #define HDA_CODEC_IDT92HD66B3X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f0)␊ |
560 | #define HDA_CODEC_IDT92HD66C1X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f1)␊ |
561 | #define HDA_CODEC_IDT92HD66C2X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f2)␊ |
562 | #define HDA_CODEC_IDT92HD66C3_65 HDA_CODEC_CONSTRUCT(IDT, 0x76f3)␊ |
563 | #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff)␊ |
564 | ␊ |
565 | /* Silicon Image */␊ |
566 | #define SII_VENDORID 0x1095␊ |
567 | #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390)␊ |
568 | #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392)␊ |
569 | #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff)␊ |
570 | ␊ |
571 | /* Lucent/Agere */␊ |
572 | #define AGERE_VENDORID 0x11c1␊ |
573 | #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff)␊ |
574 | ␊ |
575 | /* Conexant */␊ |
576 | #define CONEXANT_VENDORID 0x14f1␊ |
577 | #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)␊ |
578 | #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)␊ |
579 | #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051)␊ |
580 | #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066)␊ |
581 | #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067)␊ |
582 | #define HDA_CODEC_CX20584 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5068)␊ |
583 | #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069)␊ |
584 | #define HDA_CODEC_CX20588 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506c)␊ |
585 | #define HDA_CODEC_CX20590 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506e)␊ |
586 | #define HDA_CODEC_CX20631 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5097)␊ |
587 | #define HDA_CODEC_CX20632 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5098)␊ |
588 | #define HDA_CODEC_CX20641 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a1)␊ |
589 | #define HDA_CODEC_CX20642 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a2)␊ |
590 | #define HDA_CODEC_CX20651 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ab)␊ |
591 | #define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac)␊ |
592 | #define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8)␊ |
593 | #define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9)␊ |
594 | #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)␊ |
595 | ␊ |
596 | /* VIA */␊ |
597 | #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)␊ |
598 | #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)␊ |
599 | #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)␊ |
600 | #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)␊ |
601 | #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)␊ |
602 | #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)␊ |
603 | #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)␊ |
604 | #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)␊ |
605 | #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)␊ |
606 | #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)␊ |
607 | #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)␊ |
608 | #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)␊ |
609 | #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720)␊ |
610 | #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721)␊ |
611 | #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722)␊ |
612 | #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723)␊ |
613 | #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724)␊ |
614 | #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725)␊ |
615 | #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726)␊ |
616 | #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727)␊ |
617 | #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397)␊ |
618 | #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397)␊ |
619 | #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397)␊ |
620 | #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397)␊ |
621 | #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397)␊ |
622 | #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397)␊ |
623 | #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397)␊ |
624 | #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397)␊ |
625 | #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398)␊ |
626 | #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398)␊ |
627 | #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398)␊ |
628 | #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398)␊ |
629 | #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398)␊ |
630 | #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398)␊ |
631 | #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398)␊ |
632 | #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398)␊ |
633 | #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433)␊ |
634 | #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721)␊ |
635 | #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428)␊ |
636 | #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428)␊ |
637 | #define HDA_CODEC_VT1802_0 HDA_CODEC_CONSTRUCT(VIA, 0x0446)␊ |
638 | #define HDA_CODEC_VT1802_1 HDA_CODEC_CONSTRUCT(VIA, 0x8446)␊ |
639 | #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448)␊ |
640 | #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440)␊ |
641 | #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441)␊ |
642 | #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438)␊ |
643 | #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438)␊ |
644 | #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441)␊ |
645 | #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)␊ |
646 | ␊ |
647 | /* ATI */␊ |
648 | #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c)␊ |
649 | #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919)␊ |
650 | #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a)␊ |
651 | #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01)␊ |
652 | #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff)␊ |
653 | ␊ |
654 | /* NVIDIA */␊ |
655 | #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002)␊ |
656 | #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0003)␊ |
657 | #define HDA_CODEC_NVIDIAMCP78_3 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0005)␊ |
658 | #define HDA_CODEC_NVIDIAMCP78_4 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006)␊ |
659 | #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007)␊ |
660 | #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a)␊ |
661 | #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b)␊ |
662 | #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c)␊ |
663 | #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d)␊ |
664 | #define HDA_CODEC_NVIDIAGTS450 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0011)␊ |
665 | #define HDA_CODEC_NVIDIAGT440 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0014)␊ |
666 | #define HDA_CODEC_NVIDIAGTX550 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0015)␊ |
667 | #define HDA_CODEC_NVIDIAGTX570 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0018)␊ |
668 | #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067)␊ |
669 | #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001)␊ |
670 | #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff)␊ |
671 | ␊ |
672 | /* Chrontel */␊ |
673 | #define CHRONTEL_VENDORID 0x17e8␊ |
674 | #define HDA_CODEC_CHXXXX HDA_CODEC_CONSTRUCT(CHRONTEL, 0xffff)␊ |
675 | ␊ |
676 | /* INTEL */␊ |
677 | #define HDA_CODEC_INTELIP␉HDA_CODEC_CONSTRUCT(INTEL, 0x0054)␊ |
678 | #define HDA_CODEC_INTELBL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2801)␊ |
679 | #define HDA_CODEC_INTELCA␉HDA_CODEC_CONSTRUCT(INTEL, 0x2802)␊ |
680 | #define HDA_CODEC_INTELEL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2803)␊ |
681 | #define HDA_CODEC_INTELIP2␉HDA_CODEC_CONSTRUCT(INTEL, 0x2804)␊ |
682 | #define HDA_CODEC_INTELCPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2805)␊ |
683 | #define HDA_CODEC_INTELPPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2806)␊ |
684 | #define HDA_CODEC_INTELHSW␉HDA_CODEC_CONSTRUCT(INTEL, 0x2807)␊ |
685 | #define HDA_CODEC_INTELCL␉HDA_CODEC_CONSTRUCT(INTEL, 0x29fb)␊ |
686 | #define HDA_CODEC_INTELXXXX␉HDA_CODEC_CONSTRUCT(INTEL, 0xffff)␊ |
687 | ␊ |
688 | /****************************************************************************␊ |
689 | * HDA Controller Register Set␊ |
690 | ****************************************************************************/␊ |
691 | #define HDAC_GCAP␉0x00␉/* 2 - Global Capabilities*/␊ |
692 | #define HDAC_VMIN␉0x02␉/* 1 - Minor Version */␊ |
693 | #define HDAC_VMAJ␉0x03␉/* 1 - Major Version */␊ |
694 | #define␉HDAC_OUTPAY␉0x04␉/* 2 - Output Payload Capability */␊ |
695 | #define HDAC_INPAY␉0x06␉/* 2 - Input Payload Capability */␊ |
696 | #define HDAC_GCTL␉0x08␉/* 4 - Global Control */␊ |
697 | #define HDAC_WAKEEN␉0x0c␉/* 2 - Wake Enable */␊ |
698 | #define HDAC_STATESTS␉0x0e␉/* 2 - State Change Status */␊ |
699 | #define HDAC_GSTS␉0x10␉/* 2 - Global Status */␊ |
700 | #define HDAC_OUTSTRMPAY␉0x18␉/* 2 - Output Stream Payload Capability */␊ |
701 | #define HDAC_INSTRMPAY␉0x1a␉/* 2 - Input Stream Payload Capability */␊ |
702 | #define HDAC_INTCTL␉0x20␉/* 4 - Interrupt Control */␊ |
703 | #define HDAC_INTSTS␉0x24␉/* 4 - Interrupt Status */␊ |
704 | #define HDAC_WALCLK␉0x30␉/* 4 - Wall Clock Counter */␊ |
705 | #define HDAC_SSYNC␉0x38␉/* 4 - Stream Synchronization */␊ |
706 | #define HDAC_CORBLBASE␉0x40␉/* 4 - CORB Lower Base Address */␊ |
707 | #define HDAC_CORBUBASE␉0x44␉/* 4 - CORB Upper Base Address */␊ |
708 | #define HDAC_CORBWP␉0x48␉/* 2 - CORB Write Pointer */␊ |
709 | #define HDAC_CORBRP␉0x4a␉/* 2 - CORB Read Pointer */␊ |
710 | #define HDAC_CORBCTL␉0x4c␉/* 1 - CORB Control */␊ |
711 | #define HDAC_CORBSTS␉0x4d␉/* 1 - CORB Status */␊ |
712 | #define HDAC_CORBSIZE␉0x4e␉/* 1 - CORB Size */␊ |
713 | #define HDAC_RIRBLBASE␉0x50␉/* 4 - RIRB Lower Base Address */␊ |
714 | #define HDAC_RIRBUBASE␉0x54␉/* 4 - RIRB Upper Base Address */␊ |
715 | #define HDAC_RIRBWP␉0x58␉/* 2 - RIRB Write Pointer */␊ |
716 | #define HDAC_RINTCNT␉0x5a␉/* 2 - Response Interrupt Count */␊ |
717 | #define HDAC_RIRBCTL␉0x5c␉/* 1 - RIRB Control */␊ |
718 | #define HDAC_RIRBSTS␉0x5d␉/* 1 - RIRB Status */␊ |
719 | #define HDAC_RIRBSIZE␉0x5e␉/* 1 - RIRB Size */␊ |
720 | #define HDAC_ICOI␉0x60␉/* 4 - Immediate Command Output Interface */␊ |
721 | #define HDAC_ICII␉0x64␉/* 4 - Immediate Command Input Interface */␊ |
722 | #define HDAC_ICIS␉0x68␉/* 2 - Immediate Command Status */␊ |
723 | #define HDAC_DPIBLBASE␉0x70␉/* 4 - DMA Position Buffer Lower Base */␊ |
724 | #define HDAC_DPIBUBASE␉0x74␉/* 4 - DMA Position Buffer Upper Base */␊ |
725 | #define HDAC_SDCTL0␉0x80␉/* 3 - Stream Descriptor Control */␊ |
726 | #define HDAC_SDCTL1␉0x81␉/* 3 - Stream Descriptor Control */␊ |
727 | #define HDAC_SDCTL2␉0x82␉/* 3 - Stream Descriptor Control */␊ |
728 | #define HDAC_SDSTS␉0x83␉/* 1 - Stream Descriptor Status */␊ |
729 | #define HDAC_SDLPIB␉0x84␉/* 4 - Link Position in Buffer */␊ |
730 | #define HDAC_SDCBL␉0x88␉/* 4 - Cyclic Buffer Length */␊ |
731 | #define HDAC_SDLVI␉0x8C␉/* 2 - Last Valid Index */␊ |
732 | #define HDAC_SDFIFOS␉0x90␉/* 2 - FIFOS */␊ |
733 | #define HDAC_SDFMT␉0x92␉/* 2 - fmt */␊ |
734 | #define HDAC_SDBDPL␉0x98␉/* 4 - Buffer Descriptor Pointer Lower Base */␊ |
735 | #define HDAC_SDBDPU␉0x9C␉/* 4 - Buffer Descriptor Pointer Upper Base */␊ |
736 | ␊ |
737 | #define _HDAC_ISDOFFSET(n, iss, oss)␉(0x80 + ((n) * 0x20))␊ |
738 | #define _HDAC_ISDCTL(n, iss, oss)␉(0x00 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
739 | #define _HDAC_ISDSTS(n, iss, oss)␉(0x03 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
740 | #define _HDAC_ISDPICB(n, iss, oss)␉(0x04 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
741 | #define _HDAC_ISDCBL(n, iss, oss)␉(0x08 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
742 | #define _HDAC_ISDLVI(n, iss, oss)␉(0x0c + _HDAC_ISDOFFSET(n, iss, oss))␊ |
743 | #define _HDAC_ISDFIFOD(n, iss, oss)␉(0x10 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
744 | #define _HDAC_ISDFMT(n, iss, oss)␉(0x12 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
745 | #define _HDAC_ISDBDPL(n, iss, oss)␉(0x18 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
746 | #define _HDAC_ISDBDPU(n, iss, oss)␉(0x1c + _HDAC_ISDOFFSET(n, iss, oss))␊ |
747 | ␊ |
748 | #define _HDAC_OSDOFFSET(n, iss, oss)␉(0x80 + ((iss) * 0x20) + ((n) * 0x20))␊ |
749 | #define _HDAC_OSDCTL(n, iss, oss)␉(0x00 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
750 | #define _HDAC_OSDSTS(n, iss, oss)␉(0x03 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
751 | #define _HDAC_OSDPICB(n, iss, oss)␉(0x04 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
752 | #define _HDAC_OSDCBL(n, iss, oss)␉(0x08 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
753 | #define _HDAC_OSDLVI(n, iss, oss)␉(0x0c + _HDAC_OSDOFFSET(n, iss, oss))␊ |
754 | #define _HDAC_OSDFIFOD(n, iss, oss)␉(0x10 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
755 | #define _HDAC_OSDFMT(n, iss, oss)␉(0x12 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
756 | #define _HDAC_OSDBDPL(n, iss, oss)␉(0x18 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
757 | #define _HDAC_OSDBDPU(n, iss, oss)␉(0x1c + _HDAC_OSDOFFSET(n, iss, oss))␊ |
758 | ␊ |
759 | #define _HDAC_BSDOFFSET(n, iss, oss)␉(0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20))␊ |
760 | #define _HDAC_BSDCTL(n, iss, oss)␉(0x00 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
761 | #define _HDAC_BSDSTS(n, iss, oss)␉(0x03 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
762 | #define _HDAC_BSDPICB(n, iss, oss)␉(0x04 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
763 | #define _HDAC_BSDCBL(n, iss, oss)␉(0x08 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
764 | #define _HDAC_BSDLVI(n, iss, oss)␉(0x0c + _HDAC_BSDOFFSET(n, iss, oss))␊ |
765 | #define _HDAC_BSDFIFOD(n, iss, oss)␉(0x10 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
766 | #define _HDAC_BSDFMT(n, iss, oss)␉(0x12 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
767 | #define _HDAC_BSDBDPL(n, iss, oss)␉(0x18 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
768 | #define _HDAC_BSDBDBU(n, iss, oss)␉(0x1c + _HDAC_BSDOFFSET(n, iss, oss))␊ |
769 | ␊ |
770 | /****************************************************************************␊ |
771 | * HDA Controller Register Fields␊ |
772 | ****************************************************************************/␊ |
773 | ␊ |
774 | /* GCAP - Global Capabilities */␊ |
775 | #define HDAC_GCAP_64OK␉␉␉0x0001␊ |
776 | #define HDAC_GCAP_NSDO_MASK␉␉0x0006␊ |
777 | #define HDAC_GCAP_NSDO_SHIFT␉␉1␊ |
778 | #define HDAC_GCAP_BSS_MASK␉␉0x00f8␊ |
779 | #define HDAC_GCAP_BSS_SHIFT␉␉3␊ |
780 | #define HDAC_GCAP_ISS_MASK␉␉0x0f00␊ |
781 | #define HDAC_GCAP_ISS_SHIFT␉␉8␊ |
782 | #define HDAC_GCAP_OSS_MASK␉␉0xf000␊ |
783 | #define HDAC_GCAP_OSS_SHIFT␉␉12␊ |
784 | ␊ |
785 | #define HDAC_GCAP_NSDO_1SDO␉␉0x00␊ |
786 | #define HDAC_GCAP_NSDO_2SDO␉␉0x02␊ |
787 | #define HDAC_GCAP_NSDO_4SDO␉␉0x04␊ |
788 | ␊ |
789 | #define HDAC_GCAP_BSS(gcap)␉␉␉␉␉␉\␊ |
790 | (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT)␊ |
791 | #define HDAC_GCAP_ISS(gcap)␉␉␉␉␉␉\␊ |
792 | (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT)␊ |
793 | #define HDAC_GCAP_OSS(gcap)␉␉␉␉␉␉\␊ |
794 | (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT)␊ |
795 | #define HDAC_GCAP_NSDO(gcap)␉␉␉␉␉␉\␊ |
796 | (((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT)␊ |
797 | ␊ |
798 | /* GCTL - Global Control */␊ |
799 | #define HDAC_GCTL_CRST␉␉␉0x00000001␊ |
800 | #define HDAC_GCTL_FCNTRL␉␉0x00000002␊ |
801 | #define HDAC_GCTL_UNSOL␉␉␉0x00000100␊ |
802 | ␊ |
803 | /* WAKEEN - Wake Enable */␊ |
804 | #define HDAC_WAKEEN_SDIWEN_MASK␉␉0x7fff␊ |
805 | #define HDAC_WAKEEN_SDIWEN_SHIFT␉0␊ |
806 | ␊ |
807 | /* STATESTS - State Change Status */␊ |
808 | #define HDAC_STATESTS_SDIWAKE_MASK␉0x7fff␊ |
809 | #define HDAC_STATESTS_SDIWAKE_SHIFT␉0␊ |
810 | ␊ |
811 | #define HDAC_STATESTS_SDIWAKE(statests, n)␉␉␉␉\␊ |
812 | (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >>␉␉␉\␊ |
813 | HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001)␊ |
814 | ␊ |
815 | /* GSTS - Global Status */␊ |
816 | #define HDAC_GSTS_FSTS␉␉␉0x0002␊ |
817 | ␊ |
818 | /* INTCTL - Interrut Control */␊ |
819 | #define HDAC_INTCTL_SIE_MASK␉␉0x3fffffff␊ |
820 | #define HDAC_INTCTL_SIE_SHIFT␉␉0␊ |
821 | #define HDAC_INTCTL_CIE␉␉␉0x40000000␊ |
822 | #define HDAC_INTCTL_GIE␉␉␉0x80000000␊ |
823 | ␊ |
824 | /* INTSTS - Interrupt Status */␊ |
825 | #define HDAC_INTSTS_SIS_MASK␉␉0x3fffffff␊ |
826 | #define HDAC_INTSTS_SIS_SHIFT␉␉0␊ |
827 | #define HDAC_INTSTS_CIS␉␉␉0x40000000␊ |
828 | #define HDAC_INTSTS_GIS␉␉␉0x80000000␊ |
829 | ␊ |
830 | /* SSYNC - Stream Synchronization */␊ |
831 | #define HDAC_SSYNC_SSYNC_MASK␉␉0x3fffffff␊ |
832 | #define HDAC_SSYNC_SSYNC_SHIFT␉␉0␊ |
833 | ␊ |
834 | /* CORBWP - CORB Write Pointer */␊ |
835 | #define HDAC_CORBWP_CORBWP_MASK␉␉0x00ff␊ |
836 | #define HDAC_CORBWP_CORBWP_SHIFT␉0␊ |
837 | ␊ |
838 | /* CORBRP - CORB Read Pointer */␊ |
839 | #define HDAC_CORBRP_CORBRP_MASK␉␉0x00ff␊ |
840 | #define HDAC_CORBRP_CORBRP_SHIFT␉0␊ |
841 | #define HDAC_CORBRP_CORBRPRST␉␉0x8000␊ |
842 | ␊ |
843 | /* CORBCTL - CORB Control */␊ |
844 | #define HDAC_CORBCTL_CMEIE␉␉0x01␊ |
845 | #define HDAC_CORBCTL_CORBRUN␉␉0x02␊ |
846 | ␊ |
847 | /* CORBSTS - CORB Status */␊ |
848 | #define HDAC_CORBSTS_CMEI␉␉0x01␊ |
849 | ␊ |
850 | /* CORBSIZE - CORB Size */␊ |
851 | #define HDAC_CORBSIZE_CORBSIZE_MASK␉0x03␊ |
852 | #define HDAC_CORBSIZE_CORBSIZE_SHIFT␉0␊ |
853 | #define HDAC_CORBSIZE_CORBSZCAP_MASK␉0xf0␊ |
854 | #define HDAC_CORBSIZE_CORBSZCAP_SHIFT␉4␊ |
855 | ␊ |
856 | #define HDAC_CORBSIZE_CORBSIZE_2␉0x00␊ |
857 | #define HDAC_CORBSIZE_CORBSIZE_16␉0x01␊ |
858 | #define HDAC_CORBSIZE_CORBSIZE_256␉0x02␊ |
859 | ␊ |
860 | #define HDAC_CORBSIZE_CORBSZCAP_2␉0x10␊ |
861 | #define HDAC_CORBSIZE_CORBSZCAP_16␉0x20␊ |
862 | #define HDAC_CORBSIZE_CORBSZCAP_256␉0x40␊ |
863 | ␊ |
864 | #define HDAC_CORBSIZE_CORBSIZE(corbsize)␉␉␉␉\␊ |
865 | (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT)␊ |
866 | ␊ |
867 | /* RIRBWP - RIRB Write Pointer */␊ |
868 | #define HDAC_RIRBWP_RIRBWP_MASK␉␉0x00ff␊ |
869 | #define HDAC_RIRBWP_RIRBWP_SHIFT␉0␊ |
870 | #define HDAC_RIRBWP_RIRBWPRST␉␉0x8000␊ |
871 | ␊ |
872 | /* RINTCTN - Response Interrupt Count */␊ |
873 | #define HDAC_RINTCNT_MASK␉␉0x00ff␊ |
874 | #define HDAC_RINTCNT_SHIFT␉␉0␊ |
875 | ␊ |
876 | /* RIRBCTL - RIRB Control */␊ |
877 | #define HDAC_RIRBCTL_RINTCTL␉␉0x01␊ |
878 | #define HDAC_RIRBCTL_RIRBDMAEN␉␉0x02␊ |
879 | #define HDAC_RIRBCTL_RIRBOIC␉␉0x04␊ |
880 | ␊ |
881 | /* RIRBSTS - RIRB Status */␊ |
882 | #define HDAC_RIRBSTS_RINTFL␉␉0x01␊ |
883 | #define HDAC_RIRBSTS_RIRBOIS␉␉0x04␊ |
884 | ␊ |
885 | /* RIRBSIZE - RIRB Size */␊ |
886 | #define HDAC_RIRBSIZE_RIRBSIZE_MASK␉0x03␊ |
887 | #define HDAC_RIRBSIZE_RIRBSIZE_SHIFT␉0␊ |
888 | #define HDAC_RIRBSIZE_RIRBSZCAP_MASK␉0xf0␊ |
889 | #define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT␉4␊ |
890 | ␊ |
891 | #define HDAC_RIRBSIZE_RIRBSIZE_2␉0x00␊ |
892 | #define HDAC_RIRBSIZE_RIRBSIZE_16␉0x01␊ |
893 | #define HDAC_RIRBSIZE_RIRBSIZE_256␉0x02␊ |
894 | ␊ |
895 | #define HDAC_RIRBSIZE_RIRBSZCAP_2␉0x10␊ |
896 | #define HDAC_RIRBSIZE_RIRBSZCAP_16␉0x20␊ |
897 | #define HDAC_RIRBSIZE_RIRBSZCAP_256␉0x40␊ |
898 | ␊ |
899 | #define HDAC_RIRBSIZE_RIRBSIZE(rirbsize)␉␉␉␉\␊ |
900 | (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT)␊ |
901 | ␊ |
902 | /* DPLBASE - DMA Position Lower Base Address */␊ |
903 | #define HDAC_DPLBASE_DPLBASE_MASK␉0xffffff80␊ |
904 | #define HDAC_DPLBASE_DPLBASE_SHIFT␉7␊ |
905 | #define HDAC_DPLBASE_DPLBASE_DMAPBE␉0x00000001␊ |
906 | ␊ |
907 | /* SDCTL - Stream Descriptor Control */␊ |
908 | #define HDAC_SDCTL_SRST␉␉␉0x000001␊ |
909 | #define HDAC_SDCTL_RUN␉␉␉0x000002␊ |
910 | #define HDAC_SDCTL_IOCE␉␉␉0x000004␊ |
911 | #define HDAC_SDCTL_FEIE␉␉␉0x000008␊ |
912 | #define HDAC_SDCTL_DEIE␉␉␉0x000010␊ |
913 | #define HDAC_SDCTL2_STRIPE_MASK␉␉0x03␊ |
914 | #define HDAC_SDCTL2_STRIPE_SHIFT␉0␊ |
915 | #define HDAC_SDCTL2_TP␉␉␉0x04␊ |
916 | #define HDAC_SDCTL2_DIR␉␉␉0x08␊ |
917 | #define HDAC_SDCTL2_STRM_MASK␉␉0xf0␊ |
918 | #define HDAC_SDCTL2_STRM_SHIFT␉␉4␊ |
919 | ␊ |
920 | #define HDAC_SDSTS_DESE␉␉␉(1 << 4)␊ |
921 | #define HDAC_SDSTS_FIFOE␉␉(1 << 3)␊ |
922 | #define HDAC_SDSTS_BCIS␉␉␉(1 << 2)␊ |
923 | ␊ |
924 | #endif /* !__LIBSAIO_HDA_H */␊ |
925 | |