1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | * Bronya: 2015 Improve AMD support, cleanup and bugfix␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "platform.h"␊ |
9 | #include "cpu.h"␊ |
10 | #include "bootstruct.h"␊ |
11 | #include "boot.h"␊ |
12 | ␊ |
13 | #ifndef DEBUG_CPU␊ |
14 | #define DEBUG_CPU 0␊ |
15 | #endif␊ |
16 | ␊ |
17 | #if DEBUG_CPU␊ |
18 | #define DBG(x...)␉␉printf(x)␊ |
19 | #else␊ |
20 | #define DBG(x...)␊ |
21 | #endif␊ |
22 | ␊ |
23 | ␊ |
24 | #define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊ |
25 | ␊ |
26 | clock_frequency_info_t gPEClockFrequencyInfo;␊ |
27 | ␊ |
28 | static inline uint32_t __unused clockspeed_rdtsc(void)␊ |
29 | {␊ |
30 | ␉uint32_t out;␊ |
31 | ␉__asm__ volatile (␊ |
32 | "rdtsc\n"␊ |
33 | "shl $32,%%edx\n"␊ |
34 | "or %%edx,%%eax\n"␊ |
35 | : "=a" (out)␊ |
36 | :␊ |
37 | : "%edx"␊ |
38 | );␊ |
39 | ␉return out;␊ |
40 | }␊ |
41 | ␊ |
42 | /*␊ |
43 | * timeRDTSC()␊ |
44 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
45 | * It pauses until the value is latched in the counter␊ |
46 | * and then reads the time stamp counter to return to the caller.␊ |
47 | */␊ |
48 | static uint64_t timeRDTSC(void)␊ |
49 | {␊ |
50 | ␉int␉␉attempts = 0;␊ |
51 | ␉uint64_t ␉latchTime;␊ |
52 | ␉uint64_t␉saveTime,intermediate;␊ |
53 | ␉unsigned int␉timerValue, lastValue;␊ |
54 | ␉//boolean_t␉int_enabled;␊ |
55 | ␉/*␊ |
56 | ␉ * Table of correction factors to account for␊ |
57 | ␉ *␉ - timer counter quantization errors, and␊ |
58 | ␉ *␉ - undercounts 0..5␊ |
59 | ␉ */␊ |
60 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
61 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
62 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
63 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
64 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
65 | ␉uint64_t␉scale[6] = {␊ |
66 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
67 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
68 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
69 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
70 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
71 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
72 | ␉};␊ |
73 | ␊ |
74 | ␉//int_enabled = ml_set_interrupts_enabled(false);␊ |
75 | ␊ |
76 | restart:␊ |
77 | ␉if (attempts >= 3) // increase to up to 9 attempts.␊ |
78 | ␉{␊ |
79 | ␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊ |
80 | ␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
81 | ␉}␊ |
82 | ␉attempts++;␊ |
83 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
84 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
85 | ␉latchTime = rdtsc64();␉// get the time stamp to time␊ |
86 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
87 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
88 | ␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
89 | ␉get_PIT2(&lastValue);␊ |
90 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
91 | ␉do {␊ |
92 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
93 | ␉␉if (timerValue > lastValue)␊ |
94 | ␉␉{␊ |
95 | ␉␉␉// Timer wrapped␊ |
96 | ␉␉␉set_PIT2(0);␊ |
97 | ␉␉␉disable_PIT2();␊ |
98 | ␉␉␉goto restart;␊ |
99 | ␉␉}␊ |
100 | ␉␉lastValue = timerValue;␊ |
101 | ␉} while (timerValue > 5);␊ |
102 | ␉//printf("timerValue␉ %d\n",timerValue);␊ |
103 | ␉//printf("intermediate 0x%016llX\n",intermediate);␊ |
104 | ␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊ |
105 | ␊ |
106 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
107 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
108 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
109 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
110 | ␊ |
111 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
112 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
113 | ␊ |
114 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
115 | ␉return intermediate;␊ |
116 | }␊ |
117 | ␊ |
118 | /*␊ |
119 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
120 | */␊ |
121 | static uint64_t __unused measure_tsc_frequency(void)␊ |
122 | {␊ |
123 | ␉uint64_t tscStart;␊ |
124 | ␉uint64_t tscEnd;␊ |
125 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
126 | ␉unsigned long pollCount;␊ |
127 | ␉uint64_t retval = 0;␊ |
128 | ␉int i;␊ |
129 | ␊ |
130 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
131 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
132 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
133 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
134 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
135 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
136 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
137 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
138 | ␉ */␊ |
139 | ␉for(i = 0; i < 10; ++i)␊ |
140 | ␉{␊ |
141 | ␉␉enable_PIT2();␊ |
142 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
143 | ␉␉tscStart = rdtsc64();␊ |
144 | ␉␉pollCount = poll_PIT2_gate();␊ |
145 | ␉␉tscEnd = rdtsc64();␊ |
146 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
147 | ␉␉if (pollCount <= 1)␊ |
148 | ␉␉{␊ |
149 | ␉␉␉continue;␊ |
150 | ␉␉}␊ |
151 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
152 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
153 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
154 | ␉␉ */␊ |
155 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
156 | ␉␉{␊ |
157 | ␉␉␉continue;␊ |
158 | ␉␉}␊ |
159 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
160 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
161 | ␉␉{␊ |
162 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
163 | ␉␉}␊ |
164 | ␉}␊ |
165 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
166 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
167 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
168 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
169 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
170 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
171 | ␉ */␊ |
172 | ␊ |
173 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
174 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
175 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
176 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
177 | ␉ */␊ |
178 | ␉if (tscDelta > (1ULL<<32))␊ |
179 | ␉{␊ |
180 | ␉␉retval = 0;␊ |
181 | ␉}␊ |
182 | ␉else␊ |
183 | ␉{␊ |
184 | ␉␉retval = tscDelta * 1000 / 30;␊ |
185 | ␉}␊ |
186 | ␉disable_PIT2();␊ |
187 | ␉return retval;␊ |
188 | }␊ |
189 | ␊ |
190 | static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊ |
191 | #define RTC_FAST_DENOM␉0xFFFFFFFF␊ |
192 | ␊ |
193 | inline static uint32_t␊ |
194 | create_mul_quant_GHZ(int shift, uint32_t quant)␊ |
195 | {␊ |
196 | ␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊ |
197 | }␊ |
198 | ␊ |
199 | struct␉{␊ |
200 | ␉mach_timespec_t␉␉␉calend_offset;␊ |
201 | ␉boolean_t␉␉␉calend_is_set;␊ |
202 | ␊ |
203 | ␉int64_t␉␉␉␉calend_adjtotal;␊ |
204 | ␉int32_t␉␉␉␉calend_adjdelta;␊ |
205 | ␊ |
206 | ␉uint32_t␉␉␉boottime;␊ |
207 | ␊ |
208 | ␉mach_timebase_info_data_t␉timebase_const;␊ |
209 | ␊ |
210 | ␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊ |
211 | } rtclock;␊ |
212 | ␊ |
213 | uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊ |
214 | uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊ |
215 | uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊ |
216 | uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊ |
217 | //uint64_t cpuFreq;␊ |
218 | ␊ |
219 | static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊ |
220 | {␊ |
221 | ␊ |
222 | ␉if (cycles > (NSEC_PER_SEC/20))␊ |
223 | ␉{␊ |
224 | ␉␉// we can use just a "fast" multiply to get nanos␊ |
225 | ␉␉rtc_quant_shift = 32;␊ |
226 | ␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊ |
227 | ␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊ |
228 | ␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊ |
229 | ␉}␊ |
230 | ␉else␊ |
231 | ␉{␊ |
232 | ␉␉rtc_quant_shift = 26;␊ |
233 | ␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊ |
234 | ␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊ |
235 | ␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊ |
236 | ␉}␊ |
237 | ␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊ |
238 | ␉// BUT we also want to calculate...␊ |
239 | ␊ |
240 | ␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊ |
241 | / UI_CPUFREQ_ROUNDING_FACTOR)␊ |
242 | ␉* UI_CPUFREQ_ROUNDING_FACTOR;␊ |
243 | ␊ |
244 | ␉/*␊ |
245 | ␉ * Set current measured speed.␊ |
246 | ␉ */␊ |
247 | ␉if (cycles >= 0x100000000ULL)␊ |
248 | ␉{␊ |
249 | ␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊ |
250 | ␉}␊ |
251 | ␉else␊ |
252 | ␉{␊ |
253 | ␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊ |
254 | ␉}␊ |
255 | ␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊ |
256 | ␊ |
257 | ␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊ |
258 | ␉return(rtc_cyc_per_sec);␊ |
259 | }␊ |
260 | ␊ |
261 | /*␊ |
262 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
263 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
264 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
265 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
266 | * - busFrequency = tscFrequency / multi␊ |
267 | * - cpuFrequency = busFrequency * multi␊ |
268 | */␊ |
269 | ␊ |
270 | /* Decimal powers: */␊ |
271 | #define kilo (1000ULL)␊ |
272 | #define Mega (kilo * kilo)␊ |
273 | #define Giga (kilo * Mega)␊ |
274 | #define Tera (kilo * Giga)␊ |
275 | #define Peta (kilo * Tera)␊ |
276 | ␊ |
277 | #define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊ |
278 | ␊ |
279 | void scan_cpu(PlatformInfo_t *p)␊ |
280 | {␊ |
281 | //␉scan();␊ |
282 | ␉uint64_t␉busFCvtt2n;␊ |
283 | ␉uint64_t␉tscFCvtt2n;␊ |
284 | ␉uint64_t␉tscFreq␉␉␉= 0;␊ |
285 | ␉uint64_t␉busFrequency␉␉= 0;␊ |
286 | ␉uint64_t␉cpuFrequency␉␉= 0;␊ |
287 | ␉uint64_t␉msr␉␉␉= 0;␊ |
288 | ␉uint64_t␉flex_ratio␉␉= 0;␊ |
289 | ␉uint64_t␉cpuid_features;␊ |
290 | ␊ |
291 | ␉uint32_t␉max_ratio␉␉= 0;␊ |
292 | ␉uint32_t␉min_ratio␉␉= 0;␊ |
293 | ␉uint32_t␉reg[4];␊ |
294 | ␉uint32_t␉cores_per_package␉= 0;␊ |
295 | ␉uint32_t␉logical_per_package␉= 1;␊ |
296 | ␉uint32_t␉threads_per_core␉= 1;␊ |
297 | ␊ |
298 | ␉uint8_t␉␉bus_ratio_max␉␉= 0;␊ |
299 | ␉uint8_t␉␉bus_ratio_min␉␉= 0;␊ |
300 | ␉uint8_t␉␉currdiv␉␉␉= 0;␊ |
301 | ␉uint8_t␉␉currcoef␉␉= 0;␊ |
302 | ␉uint8_t␉␉maxdiv␉␉␉= 0;␊ |
303 | ␉uint8_t␉␉maxcoef␉␉␉= 0;␊ |
304 | ␉uint8_t␉␉pic0_mask;␊ |
305 | ␉uint8_t␉␉cpuMultN2␉␉= 0;␊ |
306 | ␊ |
307 | ␉const char␉*newratio;␊ |
308 | ␉char␉␉str[128];␊ |
309 | ␉char␉␉*s␉␉␉= 0;␊ |
310 | ␊ |
311 | ␉int␉␉len␉␉␉= 0;␊ |
312 | ␉int␉␉myfsb␉␉␉= 0;␊ |
313 | ␉int␉␉i␉␉␉= 0;␊ |
314 | ␊ |
315 | ␊ |
316 | /* http://www.flounder.com/cpuid_explorer2.htm␊ |
317 | EAX (Intel):␊ |
318 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
319 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
320 | |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊ |
321 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
322 | ␊ |
323 | EAX (AMD):␊ |
324 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
325 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
326 | |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊ |
327 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
328 | */␊ |
329 | ␉///////////////////-- MaxFn,Vendor --////////////////////////␊ |
330 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊ |
331 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
332 | ␉/////////////////////////////////////////////////////////////␊ |
333 | ␊ |
334 | ␉///////////////////-- Signature, stepping, features -- //////␊ |
335 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊ |
336 | ␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]);␊ |
337 | ␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊ |
338 | ␉{␊ |
339 | ␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊ |
340 | ␉}␊ |
341 | ␉else␊ |
342 | ␉{␊ |
343 | ␉␉logical_per_package = 1;␊ |
344 | ␉}␊ |
345 | //␉printf("logical %d\n",logical_per_package);␊ |
346 | ␊ |
347 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
348 | ␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊ |
349 | ␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊ |
350 | ␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊ |
351 | ␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
352 | ␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
353 | ␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
354 | ␊ |
355 | ␉if (p->CPU.Family == 0x0f)␊ |
356 | ␉{␊ |
357 | ␉␉p->CPU.Family += p->CPU.ExtFamily;␊ |
358 | ␉}␊ |
359 | ␊ |
360 | ␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊ |
361 | ␉{␊ |
362 | ␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
363 | ␉}␊ |
364 | ␊ |
365 | ␉/* get BrandString (if supported) */␊ |
366 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
367 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
368 | ␉{␊ |
369 | ␉␉bzero(str, 128);␊ |
370 | ␉␉/*␊ |
371 | ␉␉ * The BrandString 48 bytes (max), guaranteed to␊ |
372 | ␉␉ * be NULL terminated.␊ |
373 | ␉␉ */␊ |
374 | ␉␉do_cpuid(0x80000002, reg);␊ |
375 | ␉␉memcpy(&str[0], (char *)reg, 16);␊ |
376 | ␉␉do_cpuid(0x80000003, reg);␊ |
377 | ␉␉memcpy(&str[16], (char *)reg, 16);␊ |
378 | ␉␉do_cpuid(0x80000004, reg);␊ |
379 | ␉␉memcpy(&str[32], (char *)reg, 16);␊ |
380 | ␉␉for (s = str; *s != '\0'; s++)␊ |
381 | ␉␉{␊ |
382 | ␉␉␉if (*s != ' ')␊ |
383 | ␉␉␉{␊ |
384 | ␉␉␉␉break;␊ |
385 | ␉␉␉}␊ |
386 | ␉␉}␊ |
387 | ␉␉strlcpy(p->CPU.BrandString, s, 48);␊ |
388 | ␊ |
389 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
390 | ␉␉{␊ |
391 | ␉␉␉/*␊ |
392 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
393 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
394 | ␉␉␉ */␊ |
395 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
396 | ␉␉}␊ |
397 | ␉␉p->CPU.BrandString[47] = '\0';␊ |
398 | //␉␉DBG("Brandstring = %s\n", p->CPU.BrandString);␊ |
399 | ␉}␊ |
400 | ␊ |
401 | ␉//char *vendor = p->CPU.cpuid_vendor;␊ |
402 | ␉switch (p->CPU.Vendor){␊ |
403 | ␉␉case CPUID_VENDOR_INTEL:␊ |
404 | ␉␉{␊ |
405 | ␊ |
406 | do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊ |
407 | ␊ |
408 | do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊ |
409 | ␊ |
410 | /* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊ |
411 | if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊ |
412 | {␊ |
413 | for (i = 0; i < 0xFF; i++) // safe loop␊ |
414 | {␊ |
415 | do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊ |
416 | if (bitfield(reg[eax], 4, 0) == 0)␊ |
417 | {␊ |
418 | break;␊ |
419 | }␊ |
420 | cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊ |
421 | }␊ |
422 | }␊ |
423 | ␊ |
424 | do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
425 | ␊ |
426 | if (i > 0)␊ |
427 | {␊ |
428 | cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊ |
429 | threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊ |
430 | }␊ |
431 | ␊ |
432 | if (cores_per_package == 0)␊ |
433 | {␊ |
434 | cores_per_package = 1;␊ |
435 | }␊ |
436 | ␊ |
437 | if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊ |
438 | {␊ |
439 | do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
440 | }␊ |
441 | ␊ |
442 | if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊ |
443 | {␊ |
444 | do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
445 | }␊ |
446 | ␊ |
447 | do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
448 | ␊ |
449 | if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
450 | {␊ |
451 | do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
452 | do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
453 | }␊ |
454 | else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
455 | {␊ |
456 | do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
457 | }␊ |
458 | ␊ |
459 | ␉␉switch (p->CPU.Model)␊ |
460 | ␉␉{␊ |
461 | ␉␉␉case CPUID_MODEL_NEHALEM:␊ |
462 | ␉␉␉case CPUID_MODEL_FIELDS:␊ |
463 | ␉␉␉case CPUID_MODEL_CLARKDALE:␊ |
464 | ␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
465 | ␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
466 | ␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
467 | ␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
468 | ␉␉␉case CPUID_MODEL_HASWELL_U5:␊ |
469 | ␉␉␉case CPUID_MODEL_ATOM_3700:␊ |
470 | ␉␉␉case CPUID_MODEL_HASWELL:␊ |
471 | ␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
472 | ␉␉␉//case CPUID_MODEL_HASWELL_H:␊ |
473 | ␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
474 | ␉␉␉case CPUID_MODEL_HASWELL_ULX:␊ |
475 | ␉␉␉//case CPUID_MODEL_:␊ |
476 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊ |
477 | ␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊ |
478 | ␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
479 | ␉␉␉␉break;␊ |
480 | ␊ |
481 | ␉␉␉case CPUID_MODEL_DALES:␊ |
482 | ␉␉␉case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core␊ |
483 | ␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
484 | ␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
485 | ␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊ |
486 | ␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
487 | ␉␉␉␉break;␊ |
488 | ␉␉}␊ |
489 | ␊ |
490 | ␉␉if (p->CPU.NoCores == 0)␊ |
491 | ␉␉{␊ |
492 | ␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊ |
493 | ␉␉␉p->CPU.NoThreads␉= logical_per_package;␊ |
494 | ␉␉}␊ |
495 | ␊ |
496 | ␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
497 | ␉␉//workaround for N270. I don't know why it detected wrong␊ |
498 | ␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊ |
499 | ␉␉{␊ |
500 | ␉␉␉p->CPU.NoCores␉␉= 1;␊ |
501 | ␉␉␉p->CPU.NoThreads␉= 2;␊ |
502 | ␉␉}␊ |
503 | ␊ |
504 | ␉␉//workaround for Quad␊ |
505 | ␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊ |
506 | ␉␉{␊ |
507 | ␉␉␉p->CPU.NoCores␉␉= 4;␊ |
508 | ␉␉␉p->CPU.NoThreads␉= 4;␊ |
509 | ␉␉}␊ |
510 | ␉}␊ |
511 | ␊ |
512 | ␉break;␊ |
513 | ␊ |
514 | ␉case CPUID_VENDOR_AMD:␊ |
515 | ␉{␊ |
516 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊ |
517 | ␊ |
518 | ␉␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
519 | ␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
520 | ␉␉{␊ |
521 | ␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
522 | ␉␉}␊ |
523 | ␊ |
524 | ␉␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
525 | ␉␉{␊ |
526 | ␉␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
527 | ␉␉}␊ |
528 | ␊ |
529 | ␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊ |
530 | ␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊ |
531 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
532 | ␊ |
533 | ␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊ |
534 | ␉␉threads_per_core = cores_per_package;␊ |
535 | ␊ |
536 | ␉␉if (cores_per_package == 0)␊ |
537 | ␉␉{␊ |
538 | ␉␉␉cores_per_package = 1;␊ |
539 | ␉␉}␊ |
540 | ␊ |
541 | ␉␉p->CPU.NoCores␉␉= cores_per_package;␊ |
542 | ␉␉p->CPU.NoThreads␉= logical_per_package;␊ |
543 | ␊ |
544 | ␉␉if (p->CPU.NoCores == 0)␊ |
545 | ␉␉{␊ |
546 | ␉␉␉p->CPU.NoCores = 1;␊ |
547 | ␉␉␉p->CPU.NoThreads␉= 1;␊ |
548 | ␉␉}␊ |
549 | ␉}␊ |
550 | ␉break;␊ |
551 | ␉default :␊ |
552 | ␉␉stop("Unsupported CPU detected! System halted.");␊ |
553 | ␉}␊ |
554 | ␊ |
555 | ␉/* setup features */␊ |
556 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
557 | ␉{␊ |
558 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
559 | ␉}␊ |
560 | ␊ |
561 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
562 | ␉{␊ |
563 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
564 | ␉}␊ |
565 | ␊ |
566 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
567 | ␉{␊ |
568 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
569 | ␉}␊ |
570 | ␊ |
571 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
572 | ␉{␊ |
573 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
574 | ␉}␊ |
575 | ␊ |
576 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
577 | ␉{␊ |
578 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
579 | ␉}␊ |
580 | ␊ |
581 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
582 | ␉{␊ |
583 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
584 | ␉}␊ |
585 | ␊ |
586 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
587 | ␉{␊ |
588 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
589 | ␉}␊ |
590 | ␊ |
591 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
592 | ␉{␊ |
593 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
594 | ␉}␊ |
595 | ␊ |
596 | ␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊ |
597 | ␉{␊ |
598 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
599 | ␉}␊ |
600 | ␊ |
601 | ␉pic0_mask = inb(0x21U);␊ |
602 | ␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊ |
603 | ␊ |
604 | ␉uint64_t cycles;␊ |
605 | ␉cycles = timeRDTSC();␊ |
606 | ␉tscFreq = rtc_set_cyc_per_sec(cycles);␊ |
607 | ␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊ |
608 | ␉// if usual method failed␊ |
609 | ␉if ( tscFreq < 1000 )␉//TEST␊ |
610 | ␉{␊ |
611 | ␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊ |
612 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
613 | ␉}␊ |
614 | ␊ |
615 | ␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊ |
616 | ␉{␊ |
617 | ␉␉int intelCPU = p->CPU.Model;␊ |
618 | ␉␉if (p->CPU.Family == 0x06)␊ |
619 | ␉␉{␊ |
620 | ␉␉␉/* Nehalem CPU model */␊ |
621 | ␉␉␉switch (p->CPU.Model)␊ |
622 | ␉␉␉{␊ |
623 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
624 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
625 | ␉␉␉␉case CPUID_MODEL_CLARKDALE:␊ |
626 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
627 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
628 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
629 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
630 | /* --------------------------------------------------------- */␊ |
631 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
632 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
633 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
634 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
635 | ␉␉␉␉case CPUID_MODEL_ATOM_3700:␊ |
636 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
637 | ␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊ |
638 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
639 | ␊ |
640 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
641 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊ |
642 | /* --------------------------------------------------------- */␊ |
643 | ␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
644 | ␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
645 | ␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
646 | ␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
647 | ␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
648 | ␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
649 | ␉␉␉␉␉if (bitfield(msr, 16, 16))␊ |
650 | ␉␉␉␉␉{␊ |
651 | ␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
652 | ␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊ |
653 | ␉␉␉␉␉␉// where the cpu multipler can't be changed to␊ |
654 | ␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
655 | ␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊ |
656 | ␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊ |
657 | ␉␉␉␉␉␉// causing the system to crash since tscGranularity␊ |
658 | ␉␉␉␉␉␉// is inadvertently set to 0.␊ |
659 | ␊ |
660 | ␉␉␉␉␉␉if (flex_ratio == 0)␊ |
661 | ␉␉␉␉␉␉{␊ |
662 | ␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊ |
663 | ␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
664 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
665 | ␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
666 | ␉␉␉␉␉␉}␊ |
667 | ␉␉␉␉␉␉else␊ |
668 | ␉␉␉␉␉␉{␊ |
669 | ␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
670 | ␉␉␉␉␉␉␉{␊ |
671 | ␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
672 | ␉␉␉␉␉␉␉}␊ |
673 | ␉␉␉␉␉␉}␊ |
674 | ␉␉␉␉␉}␊ |
675 | ␊ |
676 | ␉␉␉␉␉if (bus_ratio_max)␊ |
677 | ␉␉␉␉␉{␊ |
678 | ␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊ |
679 | ␉␉␉␉␉}␊ |
680 | ␊ |
681 | ␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
682 | ␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
683 | ␉␉␉␉␉{␊ |
684 | ␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
685 | ␊ |
686 | ␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊ |
687 | ␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
688 | ␉␉␉␉␉}␊ |
689 | ␉␉␉␉␉else␊ |
690 | ␉␉␉␉␉{␊ |
691 | ␉␉␉␉␉␉cpuFrequency = tscFreq;␊ |
692 | ␉␉␉␉␉}␊ |
693 | ␊ |
694 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
695 | ␉␉␉␉␉{␊ |
696 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
697 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
698 | ␉␉␉␉␉␉if (len >= 3)␊ |
699 | ␉␉␉␉␉␉{␊ |
700 | ␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
701 | ␉␉␉␉␉␉}␊ |
702 | ␊ |
703 | ␉␉␉␉␉␉verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
704 | ␊ |
705 | ␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
706 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
707 | ␉␉␉␉␉␉{␊ |
708 | ␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊ |
709 | ␉␉␉␉␉␉␉if (len >= 3)␊ |
710 | ␉␉␉␉␉␉␉{␊ |
711 | ␉␉␉␉␉␉␉␉maxdiv = 1;␊ |
712 | ␉␉␉␉␉␉␉}␊ |
713 | ␉␉␉␉␉␉␉else␊ |
714 | ␉␉␉␉␉␉␉{␊ |
715 | ␉␉␉␉␉␉␉␉maxdiv = 0;␊ |
716 | ␉␉␉␉␉␉␉}␊ |
717 | ␉␉␉␉␉␉}␊ |
718 | ␉␉␉␉␉␉else␊ |
719 | ␉␉␉␉␉␉{␊ |
720 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
721 | ␉␉␉␉␉␉}␊ |
722 | ␉␉␉␉␉}␊ |
723 | ␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
724 | ␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊ |
725 | ␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
726 | ␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
727 | ␊ |
728 | ␉␉␉␉myfsb = busFrequency / 1000000;␊ |
729 | ␉␉␉␉verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
730 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
731 | ␊ |
732 | ␉␉␉␉break;␊ |
733 | ␊ |
734 | ␉␉␉default:␊ |
735 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
736 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
737 | ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
738 | ␉␉␉␉// Non-integer bus ratio for the max-multi␊ |
739 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
740 | ␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊ |
741 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
742 | ␊ |
743 | ␉␉␉␉// This will always be model >= 3␊ |
744 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
745 | ␉␉␉␉{␊ |
746 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
747 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
748 | ␉␉␉␉}␊ |
749 | ␉␉␉␉else␊ |
750 | ␉␉␉␉{␊ |
751 | ␉␉␉␉␉// On lower models, currcoef defines TSC freq␊ |
752 | ␉␉␉␉␉// XXX␊ |
753 | ␉␉␉␉␉maxcoef = currcoef;␊ |
754 | ␉␉␉␉}␊ |
755 | ␊ |
756 | ␉␉␉␉if (!currcoef)␊ |
757 | ␉␉␉␉{␊ |
758 | ␉␉␉␉␉currcoef = maxcoef;␊ |
759 | ␉␉␉␉}␊ |
760 | ␊ |
761 | ␉␉␉␉if (maxcoef)␊ |
762 | ␉␉␉␉{␊ |
763 | ␉␉␉␉␉if (maxdiv)␊ |
764 | ␉␉␉␉␉{␊ |
765 | ␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊ |
766 | ␉␉␉␉␉}␊ |
767 | ␉␉␉␉␉else␊ |
768 | ␉␉␉␉␉{␊ |
769 | ␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊ |
770 | ␉␉␉␉␉}␊ |
771 | ␊ |
772 | ␉␉␉␉␉if (currdiv)␊ |
773 | ␉␉␉␉␉{␊ |
774 | ␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊ |
775 | ␉␉␉␉␉}␊ |
776 | ␉␉␉␉␉else␊ |
777 | ␉␉␉␉␉{␊ |
778 | ␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊ |
779 | ␉␉␉␉␉}␊ |
780 | ␊ |
781 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
782 | ␉␉␉␉}␊ |
783 | ␉␉␉␉break;␊ |
784 | ␉␉␉}␊ |
785 | ␉␉}␊ |
786 | ␉␉// Mobile CPU␊ |
787 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
788 | ␉␉{␊ |
789 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
790 | ␉␉}␊ |
791 | ␉}␊ |
792 | ␊ |
793 | ␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊ |
794 | ␉{␊ |
795 | ␉␉switch(p->CPU.Family)␊ |
796 | ␉␉{␊ |
797 | ␉␉␉case 0xF: /* K8 */␊ |
798 | ␉␉␉{␊ |
799 | ␉␉␉␉uint64_t fidvid = 0;␊ |
800 | ␉␉␉␉uint64_t cpuMult;␊ |
801 | ␉␉␉␉uint64_t fid;␊ |
802 | ␊ |
803 | ␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊ |
804 | ␉␉␉␉fid = bitfield(fidvid, 5, 0);␊ |
805 | ␊ |
806 | ␉␉␉␉cpuMult = (fid + 8) / 2;␊ |
807 | ␉␉␉␉currcoef = cpuMult;␊ |
808 | ␊ |
809 | ␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊ |
810 | ␉␉␉␉currdiv = cpuMultN2;␊ |
811 | ␉␉␉␉/****** Addon END ******/␊ |
812 | ␉␉␉}␊ |
813 | ␉␉␉␉break;␊ |
814 | ␊ |
815 | ␉␉␉case 0x10: /*** AMD Family 10h ***/␊ |
816 | ␉␉␉{␊ |
817 | ␉␉␉␉uint64_t cofvid = 0;␊ |
818 | ␉␉␉␉uint64_t cpuMult;␊ |
819 | ␉␉␉␉uint64_t divisor = 0;␊ |
820 | ␉␉␉␉uint64_t did;␊ |
821 | ␉␉␉␉uint64_t fid;␊ |
822 | ␊ |
823 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
824 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
825 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
826 | ␉␉␉␉if (did == 0) divisor = 2;␊ |
827 | ␉␉␉␉else if (did == 1) divisor = 4;␊ |
828 | ␉␉␉␉else if (did == 2) divisor = 8;␊ |
829 | ␉␉␉␉else if (did == 3) divisor = 16;␊ |
830 | ␉␉␉␉else if (did == 4) divisor = 32;␊ |
831 | ␊ |
832 | ␉␉␉␉cpuMult = (fid + 16) / divisor;␊ |
833 | ␉␉␉␉currcoef = cpuMult;␊ |
834 | ␊ |
835 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
836 | ␉␉␉␉currdiv = cpuMultN2;␊ |
837 | ␊ |
838 | ␉␉␉␉/****** Addon END ******/␊ |
839 | ␉␉␉}␊ |
840 | ␉␉␉break;␊ |
841 | ␊ |
842 | ␉␉␉case 0x11: /*** AMD Family 11h ***/␊ |
843 | ␉␉␉{␊ |
844 | ␉␉␉␉uint64_t cofvid = 0;␊ |
845 | ␉␉␉␉uint64_t cpuMult;␊ |
846 | ␉␉␉␉uint64_t divisor = 0;␊ |
847 | ␉␉␉␉uint64_t did;␊ |
848 | ␉␉␉␉uint64_t fid;␊ |
849 | ␊ |
850 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
851 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
852 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
853 | ␉␉␉␉if (did == 0) divisor = 2;␊ |
854 | ␉␉␉␉else if (did == 1) divisor = 4;␊ |
855 | ␉␉␉␉else if (did == 2) divisor = 8;␊ |
856 | ␉␉␉␉else if (did == 3) divisor = 16;␊ |
857 | ␉␉␉␉else if (did == 4) divisor = 32;␊ |
858 | ␊ |
859 | ␉␉␉␉cpuMult = (fid + 8) / divisor;␊ |
860 | ␉␉␉␉currcoef = cpuMult;␊ |
861 | ␊ |
862 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
863 | ␉␉␉␉currdiv = cpuMultN2;␊ |
864 | ␊ |
865 | ␉␉␉␉/****** Addon END ******/␊ |
866 | ␉␉␉}␊ |
867 | break;␊ |
868 | ␊ |
869 | ␉␉␉case 0x12: /*** AMD Family 12h ***/␊ |
870 | ␉␉␉{␊ |
871 | ␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊ |
872 | ␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊ |
873 | ␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊ |
874 | ␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊ |
875 | ␊ |
876 | ␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊ |
877 | ␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊ |
878 | ␉␉␉␉uint64_t divisor;␊ |
879 | ␉␉␉␉switch (CpuDid)␊ |
880 | ␉␉␉␉{␊ |
881 | ␉␉␉␉␉case 0: divisor = 1; break;␊ |
882 | ␉␉␉␉␉case 1: divisor = (3/2); break;␊ |
883 | ␉␉␉␉␉case 2: divisor = 2; break;␊ |
884 | ␉␉␉␉␉case 3: divisor = 3; break;␊ |
885 | ␉␉␉␉␉case 4: divisor = 4; break;␊ |
886 | ␉␉␉␉␉case 5: divisor = 6; break;␊ |
887 | ␉␉␉␉␉case 6: divisor = 8; break;␊ |
888 | ␉␉␉␉␉case 7: divisor = 12; break;␊ |
889 | ␉␉␉␉␉case 8: divisor = 16; break;␊ |
890 | ␉␉␉␉␉default: divisor = 1; break;␊ |
891 | ␉␉␉␉}␊ |
892 | ␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊ |
893 | ␊ |
894 | ␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊ |
895 | ␉␉␉␉currdiv = cpuMultN2;␊ |
896 | ␊ |
897 | ␉␉␉}␊ |
898 | ␉␉␉␉break;␊ |
899 | ␊ |
900 | ␉␉␉case 0x14: /* K14 */␊ |
901 | ␊ |
902 | ␉␉␉{␊ |
903 | ␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊ |
904 | ␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊ |
905 | ␉␉␉␉uint64_t prfsts;␊ |
906 | ␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊ |
907 | ␊ |
908 | ␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊ |
909 | ␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊ |
910 | ␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊ |
911 | ␊ |
912 | ␉␉␉␉uint64_t frequencyId = 0x10;␊ |
913 | ␉␉␉␉currcoef = (frequencyId + 0x10) /␊ |
914 | ␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊ |
915 | ␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊ |
916 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
917 | ␊ |
918 | ␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊ |
919 | ␉␉␉␉currdiv = cpuMultN2;␊ |
920 | ␉␉␉}␊ |
921 | ␊ |
922 | ␉␉␉␉break;␊ |
923 | ␊ |
924 | ␉␉␉case 0x15: /*** AMD Family 15h ***/␊ |
925 | ␉␉␉case 0x06: /*** AMD Family 06h ***/␊ |
926 | ␉␉␉{␊ |
927 | ␊ |
928 | ␉␉␉␉uint64_t cofvid = 0;␊ |
929 | ␉␉␉␉uint64_t cpuMult;␊ |
930 | ␉␉␉␉uint64_t divisor = 0;␊ |
931 | ␉␉␉␉uint64_t did;␊ |
932 | ␉␉␉␉uint64_t fid;␊ |
933 | ␊ |
934 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
935 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
936 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
937 | ␉␉␉␉if (did == 0) divisor = 2;␊ |
938 | ␉␉␉␉else if (did == 1) divisor = 4;␊ |
939 | ␉␉␉␉else if (did == 2) divisor = 8;␊ |
940 | ␉␉␉␉else if (did == 3) divisor = 16;␊ |
941 | ␉␉␉␉else if (did == 4) divisor = 32;␊ |
942 | ␊ |
943 | ␉␉␉␉cpuMult = (fid + 16) / divisor;␊ |
944 | ␉␉␉␉currcoef = cpuMult;␊ |
945 | ␊ |
946 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
947 | ␉␉␉␉currdiv = cpuMultN2;␊ |
948 | ␉␉␉}␊ |
949 | ␉␉␉␉break;␊ |
950 | ␊ |
951 | ␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊ |
952 | ␉␉␉{␊ |
953 | ␉␉␉␉uint64_t cofvid = 0;␊ |
954 | ␉␉␉␉uint64_t cpuMult;␊ |
955 | ␉␉␉␉uint64_t divisor = 0;␊ |
956 | ␉␉␉␉uint64_t did;␊ |
957 | ␉␉␉␉uint64_t fid;␊ |
958 | ␊ |
959 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
960 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
961 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
962 | ␉␉␉␉if (did == 0) divisor = 1;␊ |
963 | ␉␉␉␉else if (did == 1) divisor = 2;␊ |
964 | ␉␉␉␉else if (did == 2) divisor = 4;␊ |
965 | ␉␉␉␉else if (did == 3) divisor = 8;␊ |
966 | ␉␉␉␉else if (did == 4) divisor = 16;␊ |
967 | ␊ |
968 | ␉␉␉␉cpuMult = (fid + 16) / divisor;␊ |
969 | ␉␉␉␉currcoef = cpuMult;␊ |
970 | ␊ |
971 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
972 | ␉␉␉␉currdiv = cpuMultN2;␊ |
973 | ␉␉␉␉/****** Addon END ******/␊ |
974 | ␉␉␉}␊ |
975 | ␉␉␉␉break;␊ |
976 | ␊ |
977 | ␉␉␉default:␊ |
978 | ␉␉␉{␊ |
979 | ␉␉␉␉typedef unsigned long long vlong;␊ |
980 | ␉␉␉␉uint64_t prfsts;␊ |
981 | ␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊ |
982 | ␉␉␉␉uint64_t r;␊ |
983 | ␉␉␉␉vlong hz;␊ |
984 | ␉␉␉␉r = (prfsts>>6) & 0x07;␊ |
985 | ␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊ |
986 | ␊ |
987 | ␉␉␉␉currcoef = hz / (200 * Mega);␊ |
988 | ␉␉␉}␊ |
989 | ␉␉}␊ |
990 | ␊ |
991 | ␉␉if (currcoef)␊ |
992 | ␉␉{␊ |
993 | ␉␉␉if (currdiv)␊ |
994 | ␉␉␉{␊ |
995 | ␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊ |
996 | ␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊ |
997 | ␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊ |
998 | ␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊ |
999 | ␊ |
1000 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
1001 | ␉␉␉}␊ |
1002 | ␉␉␉else␊ |
1003 | ␉␉␉{␊ |
1004 | ␉␉␉␉busFrequency = (tscFreq / currcoef);␊ |
1005 | ␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊ |
1006 | ␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊ |
1007 | ␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊ |
1008 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
1009 | ␉␉␉}␊ |
1010 | ␉␉}␊ |
1011 | ␉␉else if (!cpuFrequency)␊ |
1012 | ␉␉{␊ |
1013 | ␉␉␉cpuFrequency = tscFreq;␊ |
1014 | ␉␉}␊ |
1015 | ␉}␊ |
1016 | ␊ |
1017 | #if 0␊ |
1018 | ␉if (!busFrequency)␊ |
1019 | ␉{␊ |
1020 | ␉␉busFrequency = (DEFAULT_FSB * 1000);␊ |
1021 | ␉␉DBG("CPU: busFrequency = 0! using the default value for FSB!\n");␊ |
1022 | ␉␉cpuFrequency = tscFreq;␊ |
1023 | ␉}␊ |
1024 | ␊ |
1025 | ␉DBG("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
1026 | ␊ |
1027 | #endif␊ |
1028 | ␊ |
1029 | ␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊ |
1030 | ␊ |
1031 | ␉p->CPU.MaxCoef = maxcoef = currcoef;␊ |
1032 | ␉p->CPU.MaxDiv = maxdiv = currdiv;␊ |
1033 | ␉p->CPU.CurrCoef = currcoef;␊ |
1034 | ␉p->CPU.CurrDiv = currdiv;␊ |
1035 | ␉p->CPU.TSCFrequency = tscFreq;␊ |
1036 | ␉p->CPU.FSBFrequency = busFrequency;␊ |
1037 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
1038 | ␊ |
1039 | ␉// keep formatted with spaces instead of tabs␊ |
1040 | ␉DBG("\n------------------------------\n");␊ |
1041 | ␉DBG("\tCPU INFO\n");␊ |
1042 | ␉DBG("------------------------------\n");␊ |
1043 | ␊ |
1044 | ␉DBG("CPUID Raw Values:\n");␊ |
1045 | ␉for (i = 0; i < CPUID_MAX; i++)␊ |
1046 | ␉{␊ |
1047 | ␉␉DBG("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊ |
1048 | ␉}␊ |
1049 | ␉DBG("\n");␊ |
1050 | ␉DBG("Brand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊ |
1051 | ␉DBG("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊ |
1052 | ␉DBG("Family: 0x%X\n",␉␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊ |
1053 | ␉DBG("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊ |
1054 | ␉DBG("Signature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊ |
1055 | ␉/*switch (p->CPU.Type) {␊ |
1056 | ␉␉case PT_OEM:␊ |
1057 | ␉␉␉DBG("Processor type: Intel Original OEM Processor\n");␊ |
1058 | ␉␉␉break;␊ |
1059 | ␉␉case PT_OD:␊ |
1060 | ␉␉␉DBG("Processor type: Intel Over Drive Processor\n");␊ |
1061 | ␉␉␉break;␊ |
1062 | ␉␉case PT_DUAL:␊ |
1063 | ␉␉␉DBG("Processor type: Intel Dual Processor\n");␊ |
1064 | ␉␉␉break;␊ |
1065 | ␉␉case PT_RES:␊ |
1066 | ␉␉␉DBG("Processor type: Intel Reserved\n");␊ |
1067 | ␉␉␉break;␊ |
1068 | ␉␉default:␊ |
1069 | ␉␉␉break;␊ |
1070 | ␉}*/␊ |
1071 | ␉DBG("Model: 0x%X\n",␉␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊ |
1072 | ␉DBG("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊ |
1073 | ␉DBG("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊ |
1074 | ␉DBG("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊ |
1075 | ␉DBG("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊ |
1076 | ␉DBG("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊ |
1077 | ␉DBG("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊ |
1078 | ␉DBG("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊ |
1079 | ␉DBG("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊ |
1080 | ␉DBG("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊ |
1081 | ␉DBG("Cores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊ |
1082 | ␉DBG("Logical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊ |
1083 | ␉DBG("Features: 0x%08x\n",␉p->CPU.Features);␊ |
1084 | ␊ |
1085 | ␉DBG("\n---------------------------------------------\n");␊ |
1086 | #if DEBUG_CPU␊ |
1087 | ␉pause();␊ |
1088 | #endif␊ |
1089 | }␊ |
1090 | |